diff options
| author | Tom Rini <[email protected]> | 2025-07-30 08:23:49 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-07-30 09:53:54 -0600 |
| commit | 79f3e77133bd7248e4579827effc13f97a32a8a8 (patch) | |
| tree | a07b12ad88df86101ab26cf978668bc4c1872377 /dts/upstream/src/mips | |
| parent | 9773b27e127af0e3192d98c6ca45dee64657a78f (diff) | |
| parent | ecec23fc9a9f0eb48b761722c492cbbd4bb2e546 (diff) | |
Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git
Perform a few fixups in our dts* files to match upstream changes.
Signed-off-by: Tom Rini <[email protected]>
Diffstat (limited to 'dts/upstream/src/mips')
| -rw-r--r-- | dts/upstream/src/mips/econet/en751221.dtsi | 67 | ||||
| -rw-r--r-- | dts/upstream/src/mips/econet/en751221_smartfiber_xp8421-b.dts | 19 | ||||
| -rw-r--r-- | dts/upstream/src/mips/loongson/loongson64c_4core_ls7a.dts | 1 | ||||
| -rw-r--r-- | dts/upstream/src/mips/pic32/pic32mzda.dtsi | 2 | ||||
| -rw-r--r-- | dts/upstream/src/mips/realtek/rtl930x.dtsi | 33 |
5 files changed, 121 insertions, 1 deletions
diff --git a/dts/upstream/src/mips/econet/en751221.dtsi b/dts/upstream/src/mips/econet/en751221.dtsi new file mode 100644 index 00000000000..66197e73d4f --- /dev/null +++ b/dts/upstream/src/mips/econet/en751221.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/ { + compatible = "econet,en751221"; + #address-cells = <1>; + #size-cells = <1>; + + hpt_clock: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; /* 200 MHz */ + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24KEc"; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + intc: interrupt-controller@1fb40000 { + compatible = "econet,en751221-intc"; + reg = <0x1fb40000 0x100>; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + + interrupt-controller; + #interrupt-cells = <1>; + econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + }; + + uart: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&intc>; + interrupts = <0>; + /* + * Conversion of baud rate to clock frequency requires a + * computation that is not in the ns16550 driver, so this + * uart is fixed at 115200 baud. + */ + clock-frequency = <1843200>; + }; + + timer_hpt: timer@1fbf0400 { + compatible = "econet,en751221-timer"; + reg = <0x1fbf0400 0x100>; + + interrupt-parent = <&intc>; + interrupts = <30>; + clocks = <&hpt_clock>; + }; +}; diff --git a/dts/upstream/src/mips/econet/en751221_smartfiber_xp8421-b.dts b/dts/upstream/src/mips/econet/en751221_smartfiber_xp8421-b.dts new file mode 100644 index 00000000000..8223c5bce67 --- /dev/null +++ b/dts/upstream/src/mips/econet/en751221_smartfiber_xp8421-b.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +#include "en751221.dtsi" + +/ { + model = "SmartFiber XP8421-B"; + compatible = "smartfiber,xp8421-b", "econet,en751221"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x1c000000>; + }; + + chosen { + stdout-path = "/serial@1fbf0000:115200"; + linux,usable-memory-range = <0x00020000 0x1bfe0000>; + }; +}; diff --git a/dts/upstream/src/mips/loongson/loongson64c_4core_ls7a.dts b/dts/upstream/src/mips/loongson/loongson64c_4core_ls7a.dts index c7ea4f1c0bb..6c277ab83d4 100644 --- a/dts/upstream/src/mips/loongson/loongson64c_4core_ls7a.dts +++ b/dts/upstream/src/mips/loongson/loongson64c_4core_ls7a.dts @@ -29,6 +29,7 @@ compatible = "loongson,pch-msi-1.0"; reg = <0 0x2ff00000 0 0x8>; interrupt-controller; + #interrupt-cells = <1>; msi-controller; loongson,msi-base-vec = <64>; loongson,msi-num-vecs = <64>; diff --git a/dts/upstream/src/mips/pic32/pic32mzda.dtsi b/dts/upstream/src/mips/pic32/pic32mzda.dtsi index fdc721b414a..feca35ba56a 100644 --- a/dts/upstream/src/mips/pic32/pic32mzda.dtsi +++ b/dts/upstream/src/mips/pic32/pic32mzda.dtsi @@ -225,7 +225,7 @@ gpio-ranges = <&pic32_pinctrl 0 144 16>; }; - sdhci: sdhci@1f8ec000 { + sdhci: mmc@1f8ec000 { compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; diff --git a/dts/upstream/src/mips/realtek/rtl930x.dtsi b/dts/upstream/src/mips/realtek/rtl930x.dtsi index f2e57ea3a60..101bab72a95 100644 --- a/dts/upstream/src/mips/realtek/rtl930x.dtsi +++ b/dts/upstream/src/mips/realtek/rtl930x.dtsi @@ -69,6 +69,39 @@ #size-cells = <0>; status = "disabled"; }; + + mdio_controller: mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + mdio0: mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio1: mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio2: mdio-bus@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mdio3: mdio-bus@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; soc: soc@18000000 { |
