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authorQuentin Schulz <[email protected]>2025-08-13 16:07:39 +0200
committerKever Yang <[email protected]>2025-08-30 23:28:20 +0800
commit4e3d2972d1bb3f891a8c827553524328d6679d14 (patch)
treee94845d9632c8e76c2dc602f757334a5bfbf8504 /dts/upstream
parent50c8b58eeab7708e76f82cf9a93bb7c5feb60ed6 (diff)
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever the PMIC is reset either programmatically or via some external pins (e.g. PWRCTRL or RESETB). The following modes exist: - 0; restart PMU, - 1; reset all power off reset registers and force state to switch to ACTIVE mode, - 2; same as mode 1 and also pull RESETB pin down for 5ms, For example, some hardware may require a full restart (mode 0) in order to function properly as regulators are shortly interrupted in this mode. This is the case for RK3588 Jaguar and RK3588 Tiger which have a companion microcontroller running on an independent power supply and monitoring the PMIC power rail to know the state of the main system. When it detects a restart, it resets its own IPs exposed to the main system as if to simulate its own reset. Failing to perform this fake reset of the microcontroller may break things (e.g. watchdog not automatically disabled, buzzer still running until manually disabled, leftover configuration from previous main system state, etc...). Some other systems may be depending on the power rails to not be interrupted even for a small amount of time[1]. This allows to specify how the PMIC should perform on the hardware level and may differ between hardware designs, so a DT property seems warranted. I unfortunately do not see how this could be made generic enough to make it a non-vendor property. [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/ Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: "Rob Herring (Arm)" <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lee Jones <[email protected]> [ upstream commit: 404005d1083997daec7236620b9ba14bccdce449 ] (cherry picked from commit 8ee72356e9844265334fd344bc05139d1f615c4d) Reviewed-by: Kever Yang <[email protected]>
Diffstat (limited to 'dts/upstream')
-rw-r--r--dts/upstream/Bindings/mfd/rockchip,rk806.yaml21
1 files changed, 21 insertions, 0 deletions
diff --git a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
index 3c2b06629b7..eb5bca31948 100644
--- a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
+++ b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml
@@ -31,6 +31,27 @@ properties:
system-power-controller: true
+ rockchip,reset-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ description:
+ Mode to use when a reset of the PMIC is triggered.
+
+ The reset can be triggered either programmatically, via one of
+ the PWRCTRL pins (provided additional configuration) or
+ asserting RESETB pin low.
+
+ The following modes are supported
+
+ - 0; restart PMU,
+ - 1; reset all power off reset registers and force state to
+ switch to ACTIVE mode,
+ - 2; same as mode 1 and also pull RESETB pin down for 5ms,
+
+ For example, some hardware may require a full restart (mode 0)
+ in order to function properly as regulators are shortly
+ interrupted in this mode.
+
vcc1-supply:
description:
The input supply for dcdc-reg1.