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authorWolfgang Denk <[email protected]>2010-03-30 22:22:47 +0200
committerWolfgang Denk <[email protected]>2010-03-30 22:22:47 +0200
commitf3dfbb681620798d212f7e4edfda6c578fe79870 (patch)
treea92f5378163f69c67f2592912eb822af0424184e /include/asm-ppc/processor.h
parent7d3ef4fa20a048008b979466f1326992aadad8ce (diff)
parent9ff32d8ccf0e23b5577c25610f001af8d761b4a2 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/asm-ppc/processor.h')
-rw-r--r--include/asm-ppc/processor.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index c6da4116308..9b3d616a671 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -485,10 +485,12 @@
#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
+#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
+#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */