Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

To quote Andre:

One prominent feature is the restructering of the clock driver, which
allows to end up with one actual driver for all variants, although we
still only compile in support for one SoC.
Also contained are some initial SPI fixes, which should fix some
problems, and enable SPI flash support for the F1C100s SoC. Those
patches revealed more problems, I will queue fixes later on, but for
now it should at least still work.
Apart from some smaller fixes (for instance for NAND operation), there
is also preparation for the upcoming Allwinner D1 support, in form of
the USB PHY driver. There are more driver support patches to come.

The gitlab CI completed successfully, including the build test for all
160 sunxi boards. I also boot tested on a few boards, but didn't have
time for more elaborate tests this time.

1 files changed, 4 insertions, 17 deletions

diff --git a/include/clk/sunxi.h b/include/clk/sunxi.h
index c4a9dee5ebf..c298195c51e 100644
--- a/include/clk/sunxi.h
+++ b/include/clk/sunxi.h
@@ -70,34 +70,21 @@ struct ccu_reset {
 struct ccu_desc {
 	const struct ccu_clk_gate *gates;
 	const struct ccu_reset *resets;
+	u8 num_gates;
+	u8 num_resets;
 };
 
 /**
- * struct ccu_priv - sunxi clock control unit
+ * struct ccu_plat - sunxi clock control unit platform data
  *
  * @base:	base address
  * @desc:	ccu descriptor
  */
-struct ccu_priv {
+struct ccu_plat {
 	void *base;
 	const struct ccu_desc *desc;
 };
 
-/**
- * sunxi_clk_probe - common sunxi clock probe
- * @dev:	clock device
- */
-int sunxi_clk_probe(struct udevice *dev);
-
 extern struct clk_ops sunxi_clk_ops;
 
-/**
- * sunxi_reset_bind() - reset binding
- *
- * @dev:       reset device
- * @count:     reset count
- * Return: 0 success, or error value
- */
-int sunxi_reset_bind(struct udevice *dev, ulong count);
-
 #endif /* _CLK_SUNXI_H */