diff options
| author | Tom Rini <[email protected]> | 2022-11-16 13:10:37 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-12-05 16:06:07 -0500 |
| commit | aa6e94deabb45154cea07ad44c4a5c047bca078b (patch) | |
| tree | 1131ae8e3635f3d0c91f8df892ab05e4d9595785 /include/configs/at91sam9263ek.h | |
| parent | aec118ebe63f7f0ab60916f9906fb3cb680abf7a (diff) | |
global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.
Signed-off-by: Tom Rini <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Diffstat (limited to 'include/configs/at91sam9263ek.h')
| -rw-r--r-- | include/configs/at91sam9263ek.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index bba8574b1c8..aefa9fc60c4 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -23,8 +23,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 @@ -100,22 +100,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ |