diff options
| author | Haiying Wang <[email protected]> | 2007-06-19 14:18:34 -0400 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <[email protected]> | 2007-08-14 01:46:08 -0500 |
| commit | c59e4091ffe0148398b9e9ff14a019ea038b7432 (patch) | |
| tree | 6d741c960be02243bff591c1ef1d98ad112e94a7 /include/configs | |
| parent | d111d6382c99fdea08c2312eeeae8786945e189a (diff) | |
Add PCI support for MPC8568MDS board
This patch is against u-boot-mpc85xx.git of www.denx.com
Signed-off-by: Haiying Wang <[email protected]>
Signed-off-by: Ebony Zhu <[email protected]>
Diffstat (limited to 'include/configs')
| -rw-r--r-- | include/configs/MPC8568MDS.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index eef168c252d..5bc953adc42 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -33,7 +33,7 @@ #define CONFIG_MPC8568 1 /* MPC8568 specific */ #define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */ -#undef CONFIG_PCI +#define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -306,11 +306,14 @@ extern unsigned long get_clock_freq(void); #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR 0x52 #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 /* * General PCI @@ -318,7 +321,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE -#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */ |