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authorE Shattow <[email protected]>2025-10-15 03:22:45 -0700
committerLeo Yu-Chi Liang <[email protected]>2025-10-28 19:29:43 +0800
commit2b26cda14f8567680613e079e4b63c86edf4fedb (patch)
tree349f66be75481ff14315700f32362d44075e649e /include/debug_uart.h
parent417ad9b0c71bd242923050173daf2e7b95e28229 (diff)
riscv: dts: starfive: jh7110: add DMC memory controller
Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]> [ upstream commit: 7114969021ec5c4c0f3df1da3a8790f75dda92e2 ] (cherry picked from commit 8d5c520b73b7c29b714f75e99ed48baa55fc5fa1)
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