diff options
| author | Neil Armstrong <[email protected]> | 2024-10-11 16:38:25 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-10-21 15:27:33 -0600 |
| commit | 73ab8196886c145983d5ff5514c179487df0c6e1 (patch) | |
| tree | 3cc8dfda8b31c962a6b7419833e66e4dd5dd8bb5 /include/debug_uart.h | |
| parent | ef6f4f8e3c0de80f5f6dc4a77d6b18078e6fd2df (diff) | |
usb: dwc3: fix dcache flush range calculation
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with CACHELINE_SIZE.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the buffer and also
flush the previous and last cacheline.
Reviewed-by: Mattijs Korpershoek <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include/debug_uart.h')
0 files changed, 0 insertions, 0 deletions