Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver

2 files changed, 38 insertions, 25 deletions

diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0cb324c8b0c..744dffe0a2d 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -895,6 +895,19 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
 int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device);
 
 /**
+ * ofnode_read_eth_phy_id() - look up eth phy vendor and device id
+ *
+ * Look at the compatible property of a device node that represents a eth phy
+ * device and extract phy vendor id and device id from it.
+ *
+ * @param node		node to examine
+ * @param vendor	vendor id of the eth phy device
+ * @param device	device id of the eth phy device
+ * @return 0 if ok, negative on error
+ */
+int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device);
+
+/**
  * ofnode_read_addr_cells() - Get the number of address cells for a node
  *
  * This walks back up the tree to find the closest #address-cells property
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 8b869c4fbfb..a09b242fd99 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -7,7 +7,7 @@
 #define __PINCTRL_H
 
 #define PINNAME_SIZE	10
-#define PINMUX_SIZE	40
+#define PINMUX_SIZE	80
 
 /**
  * struct pinconf_param - pin config parameters
@@ -453,30 +453,30 @@ struct pinctrl_ops {
  *	presented using the packed format.
  */
 enum pin_config_param {
-	PIN_CONFIG_BIAS_BUS_HOLD,
-	PIN_CONFIG_BIAS_DISABLE,
-	PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
-	PIN_CONFIG_BIAS_PULL_DOWN,
-	PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
-	PIN_CONFIG_BIAS_PULL_UP,
-	PIN_CONFIG_DRIVE_OPEN_DRAIN,
-	PIN_CONFIG_DRIVE_OPEN_SOURCE,
-	PIN_CONFIG_DRIVE_PUSH_PULL,
-	PIN_CONFIG_DRIVE_STRENGTH,
-	PIN_CONFIG_DRIVE_STRENGTH_UA,
-	PIN_CONFIG_INPUT_DEBOUNCE,
-	PIN_CONFIG_INPUT_ENABLE,
-	PIN_CONFIG_INPUT_SCHMITT,
-	PIN_CONFIG_INPUT_SCHMITT_ENABLE,
-	PIN_CONFIG_LOW_POWER_MODE,
-	PIN_CONFIG_OUTPUT_ENABLE,
-	PIN_CONFIG_OUTPUT,
-	PIN_CONFIG_POWER_SOURCE,
-	PIN_CONFIG_SLEEP_HARDWARE_STATE,
-	PIN_CONFIG_SLEW_RATE,
-	PIN_CONFIG_SKEW_DELAY,
-	PIN_CONFIG_END = 0x7F,
-	PIN_CONFIG_MAX = 0xFF,
+	PIN_CONFIG_BIAS_BUS_HOLD = 0,
+	PIN_CONFIG_BIAS_DISABLE = 1,
+	PIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,
+	PIN_CONFIG_BIAS_PULL_DOWN = 3,
+	PIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,
+	PIN_CONFIG_BIAS_PULL_UP = 5,
+	PIN_CONFIG_DRIVE_OPEN_DRAIN = 6,
+	PIN_CONFIG_DRIVE_OPEN_SOURCE = 7,
+	PIN_CONFIG_DRIVE_PUSH_PULL = 8,
+	PIN_CONFIG_DRIVE_STRENGTH = 9,
+	PIN_CONFIG_DRIVE_STRENGTH_UA = 10,
+	PIN_CONFIG_INPUT_DEBOUNCE = 11,
+	PIN_CONFIG_INPUT_ENABLE = 12,
+	PIN_CONFIG_INPUT_SCHMITT = 13,
+	PIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,
+	PIN_CONFIG_LOW_POWER_MODE = 15,
+	PIN_CONFIG_OUTPUT_ENABLE = 16,
+	PIN_CONFIG_OUTPUT = 17,
+	PIN_CONFIG_POWER_SOURCE = 18,
+	PIN_CONFIG_SLEEP_HARDWARE_STATE = 19,
+	PIN_CONFIG_SLEW_RATE = 20,
+	PIN_CONFIG_SKEW_DELAY = 21,
+	PIN_CONFIG_END = 127,	/* 0x7F */
+	PIN_CONFIG_MAX = 255, /* 0xFF */
 };
 
 #if CONFIG_IS_ENABLED(PINCTRL_GENERIC)