Merge tag 'u-boot-amlogic-next-20241113' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

- khadas-vim3{l}: fix userdata size for android config
- drop A1 dtsi and other bindings includes in favor of Upstream ones

4 files changed, 0 insertions, 387 deletions

diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
deleted file mode 100644
index 06f198ee762..00000000000
--- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <[email protected]>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <[email protected]>
- */
-
-#ifndef __A1_PERIPHERALS_CLKC_H
-#define __A1_PERIPHERALS_CLKC_H
-
-#define CLKID_XTAL_IN		0
-#define CLKID_FIXPLL_IN		1
-#define CLKID_USB_PHY_IN	2
-#define CLKID_USB_CTRL_IN	3
-#define CLKID_HIFIPLL_IN	4
-#define CLKID_SYSPLL_IN		5
-#define CLKID_DDS_IN		6
-#define CLKID_SYS		7
-#define CLKID_CLKTREE		8
-#define CLKID_RESET_CTRL	9
-#define CLKID_ANALOG_CTRL	10
-#define CLKID_PWR_CTRL		11
-#define CLKID_PAD_CTRL		12
-#define CLKID_SYS_CTRL		13
-#define CLKID_TEMP_SENSOR	14
-#define CLKID_AM2AXI_DIV	15
-#define CLKID_SPICC_B		16
-#define CLKID_SPICC_A		17
-#define CLKID_MSR		18
-#define CLKID_AUDIO		19
-#define CLKID_JTAG_CTRL		20
-#define CLKID_SARADC_EN		21
-#define CLKID_PWM_EF		22
-#define CLKID_PWM_CD		23
-#define CLKID_PWM_AB		24
-#define CLKID_CEC		25
-#define CLKID_I2C_S		26
-#define CLKID_IR_CTRL		27
-#define CLKID_I2C_M_D		28
-#define CLKID_I2C_M_C		29
-#define CLKID_I2C_M_B		30
-#define CLKID_I2C_M_A		31
-#define CLKID_ACODEC		32
-#define CLKID_OTP		33
-#define CLKID_SD_EMMC_A		34
-#define CLKID_USB_PHY		35
-#define CLKID_USB_CTRL		36
-#define CLKID_SYS_DSPB		37
-#define CLKID_SYS_DSPA		38
-#define CLKID_DMA		39
-#define CLKID_IRQ_CTRL		40
-#define CLKID_NIC		41
-#define CLKID_GIC		42
-#define CLKID_UART_C		43
-#define CLKID_UART_B		44
-#define CLKID_UART_A		45
-#define CLKID_SYS_PSRAM		46
-#define CLKID_RSA		47
-#define CLKID_CORESIGHT		48
-#define CLKID_AM2AXI_VAD	49
-#define CLKID_AUDIO_VAD		50
-#define CLKID_AXI_DMC		51
-#define CLKID_AXI_PSRAM		52
-#define CLKID_RAMB		53
-#define CLKID_RAMA		54
-#define CLKID_AXI_SPIFC		55
-#define CLKID_AXI_NIC		56
-#define CLKID_AXI_DMA		57
-#define CLKID_CPU_CTRL		58
-#define CLKID_ROM		59
-#define CLKID_PROC_I2C		60
-#define CLKID_DSPA_SEL		61
-#define CLKID_DSPB_SEL		62
-#define CLKID_DSPA_EN		63
-#define CLKID_DSPA_EN_NIC	64
-#define CLKID_DSPB_EN		65
-#define CLKID_DSPB_EN_NIC	66
-#define CLKID_RTC		67
-#define CLKID_CECA_32K		68
-#define CLKID_CECB_32K		69
-#define CLKID_24M		70
-#define CLKID_12M		71
-#define CLKID_FCLK_DIV2_DIVN	72
-#define CLKID_GEN		73
-#define CLKID_SARADC_SEL	74
-#define CLKID_SARADC		75
-#define CLKID_PWM_A		76
-#define CLKID_PWM_B		77
-#define CLKID_PWM_C		78
-#define CLKID_PWM_D		79
-#define CLKID_PWM_E		80
-#define CLKID_PWM_F		81
-#define CLKID_SPICC		82
-#define CLKID_TS		83
-#define CLKID_SPIFC		84
-#define CLKID_USB_BUS		85
-#define CLKID_SD_EMMC		86
-#define CLKID_PSRAM		87
-#define CLKID_DMC		88
-#define CLKID_SYS_A_SEL		89
-#define CLKID_SYS_A_DIV		90
-#define CLKID_SYS_A		91
-#define CLKID_SYS_B_SEL		92
-#define CLKID_SYS_B_DIV		93
-#define CLKID_SYS_B		94
-#define CLKID_DSPA_A_SEL	95
-#define CLKID_DSPA_A_DIV	96
-#define CLKID_DSPA_A		97
-#define CLKID_DSPA_B_SEL	98
-#define CLKID_DSPA_B_DIV	99
-#define CLKID_DSPA_B		100
-#define CLKID_DSPB_A_SEL	101
-#define CLKID_DSPB_A_DIV	102
-#define CLKID_DSPB_A		103
-#define CLKID_DSPB_B_SEL	104
-#define CLKID_DSPB_B_DIV	105
-#define CLKID_DSPB_B		106
-#define CLKID_RTC_32K_IN	107
-#define CLKID_RTC_32K_DIV	108
-#define CLKID_RTC_32K_XTAL	109
-#define CLKID_RTC_32K_SEL	110
-#define CLKID_CECB_32K_IN	111
-#define CLKID_CECB_32K_DIV	112
-#define CLKID_CECB_32K_SEL_PRE	113
-#define CLKID_CECB_32K_SEL	114
-#define CLKID_CECA_32K_IN	115
-#define CLKID_CECA_32K_DIV	116
-#define CLKID_CECA_32K_SEL_PRE	117
-#define CLKID_CECA_32K_SEL	118
-#define CLKID_DIV2_PRE		119
-#define CLKID_24M_DIV2		120
-#define CLKID_GEN_SEL		121
-#define CLKID_GEN_DIV		122
-#define CLKID_SARADC_DIV	123
-#define CLKID_PWM_A_SEL		124
-#define CLKID_PWM_A_DIV		125
-#define CLKID_PWM_B_SEL		126
-#define CLKID_PWM_B_DIV		127
-#define CLKID_PWM_C_SEL		128
-#define CLKID_PWM_C_DIV		129
-#define CLKID_PWM_D_SEL		130
-#define CLKID_PWM_D_DIV		131
-#define CLKID_PWM_E_SEL		132
-#define CLKID_PWM_E_DIV		133
-#define CLKID_PWM_F_SEL		134
-#define CLKID_PWM_F_DIV		135
-#define CLKID_SPICC_SEL		136
-#define CLKID_SPICC_DIV		137
-#define CLKID_SPICC_SEL2	138
-#define CLKID_TS_DIV		139
-#define CLKID_SPIFC_SEL		140
-#define CLKID_SPIFC_DIV		141
-#define CLKID_SPIFC_SEL2	142
-#define CLKID_USB_BUS_SEL	143
-#define CLKID_USB_BUS_DIV	144
-#define CLKID_SD_EMMC_SEL	145
-#define CLKID_SD_EMMC_DIV	146
-#define CLKID_SD_EMMC_SEL2	147
-#define CLKID_PSRAM_SEL		148
-#define CLKID_PSRAM_DIV		149
-#define CLKID_PSRAM_SEL2	150
-#define CLKID_DMC_SEL		151
-#define CLKID_DMC_DIV		152
-#define CLKID_DMC_SEL2		153
-
-#endif /* __A1_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
deleted file mode 100644
index 2b660c0f2c9..00000000000
--- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
-/*
- * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
- * Author: Jian Hu <[email protected]>
- *
- * Copyright (c) 2023, SberDevices. All Rights Reserved.
- * Author: Dmitry Rokosov <[email protected]>
- */
-
-#ifndef __A1_PLL_CLKC_H
-#define __A1_PLL_CLKC_H
-
-#define CLKID_FIXED_PLL_DCO	0
-#define CLKID_FIXED_PLL		1
-#define CLKID_FCLK_DIV2_DIV	2
-#define CLKID_FCLK_DIV3_DIV	3
-#define CLKID_FCLK_DIV5_DIV	4
-#define CLKID_FCLK_DIV7_DIV	5
-#define CLKID_FCLK_DIV2		6
-#define CLKID_FCLK_DIV3		7
-#define CLKID_FCLK_DIV5		8
-#define CLKID_FCLK_DIV7		9
-#define CLKID_HIFI_PLL		10
-
-#endif /* __A1_PLL_CLKC_H */
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
deleted file mode 100644
index f561f5c5ef8..00000000000
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
-/*
- * Copyright (c) 2018 Baylibre SAS.
- * Author: Jerome Brunet <[email protected]>
- */
-
-#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
-#define __AXG_AUDIO_CLKC_BINDINGS_H
-
-#define AUD_CLKID_DDR_ARB		29
-#define AUD_CLKID_PDM			30
-#define AUD_CLKID_TDMIN_A		31
-#define AUD_CLKID_TDMIN_B		32
-#define AUD_CLKID_TDMIN_C		33
-#define AUD_CLKID_TDMIN_LB		34
-#define AUD_CLKID_TDMOUT_A		35
-#define AUD_CLKID_TDMOUT_B		36
-#define AUD_CLKID_TDMOUT_C		37
-#define AUD_CLKID_FRDDR_A		38
-#define AUD_CLKID_FRDDR_B		39
-#define AUD_CLKID_FRDDR_C		40
-#define AUD_CLKID_TODDR_A		41
-#define AUD_CLKID_TODDR_B		42
-#define AUD_CLKID_TODDR_C		43
-#define AUD_CLKID_LOOPBACK		44
-#define AUD_CLKID_SPDIFIN		45
-#define AUD_CLKID_SPDIFOUT		46
-#define AUD_CLKID_RESAMPLE		47
-#define AUD_CLKID_POWER_DETECT		48
-#define AUD_CLKID_MST_A_MCLK		49
-#define AUD_CLKID_MST_B_MCLK		50
-#define AUD_CLKID_MST_C_MCLK		51
-#define AUD_CLKID_MST_D_MCLK		52
-#define AUD_CLKID_MST_E_MCLK		53
-#define AUD_CLKID_MST_F_MCLK		54
-#define AUD_CLKID_SPDIFOUT_CLK		55
-#define AUD_CLKID_SPDIFIN_CLK		56
-#define AUD_CLKID_PDM_DCLK		57
-#define AUD_CLKID_PDM_SYSCLK		58
-#define AUD_CLKID_MST_A_SCLK		79
-#define AUD_CLKID_MST_B_SCLK		80
-#define AUD_CLKID_MST_C_SCLK		81
-#define AUD_CLKID_MST_D_SCLK		82
-#define AUD_CLKID_MST_E_SCLK		83
-#define AUD_CLKID_MST_F_SCLK		84
-#define AUD_CLKID_MST_A_LRCLK		86
-#define AUD_CLKID_MST_B_LRCLK		87
-#define AUD_CLKID_MST_C_LRCLK		88
-#define AUD_CLKID_MST_D_LRCLK		89
-#define AUD_CLKID_MST_E_LRCLK		90
-#define AUD_CLKID_MST_F_LRCLK		91
-#define AUD_CLKID_TDMIN_A_SCLK_SEL	116
-#define AUD_CLKID_TDMIN_B_SCLK_SEL	117
-#define AUD_CLKID_TDMIN_C_SCLK_SEL	118
-#define AUD_CLKID_TDMIN_LB_SCLK_SEL	119
-#define AUD_CLKID_TDMOUT_A_SCLK_SEL	120
-#define AUD_CLKID_TDMOUT_B_SCLK_SEL	121
-#define AUD_CLKID_TDMOUT_C_SCLK_SEL	122
-#define AUD_CLKID_TDMIN_A_SCLK		123
-#define AUD_CLKID_TDMIN_B_SCLK		124
-#define AUD_CLKID_TDMIN_C_SCLK		125
-#define AUD_CLKID_TDMIN_LB_SCLK		126
-#define AUD_CLKID_TDMOUT_A_SCLK		127
-#define AUD_CLKID_TDMOUT_B_SCLK		128
-#define AUD_CLKID_TDMOUT_C_SCLK		129
-#define AUD_CLKID_TDMIN_A_LRCLK		130
-#define AUD_CLKID_TDMIN_B_LRCLK		131
-#define AUD_CLKID_TDMIN_C_LRCLK		132
-#define AUD_CLKID_TDMIN_LB_LRCLK	133
-#define AUD_CLKID_TDMOUT_A_LRCLK	134
-#define AUD_CLKID_TDMOUT_B_LRCLK	135
-#define AUD_CLKID_TDMOUT_C_LRCLK	136
-#define AUD_CLKID_SPDIFOUT_B		151
-#define AUD_CLKID_SPDIFOUT_B_CLK	152
-#define AUD_CLKID_TDM_MCLK_PAD0		155
-#define AUD_CLKID_TDM_MCLK_PAD1		156
-#define AUD_CLKID_TDM_LRCLK_PAD0	157
-#define AUD_CLKID_TDM_LRCLK_PAD1	158
-#define AUD_CLKID_TDM_LRCLK_PAD2	159
-#define AUD_CLKID_TDM_SCLK_PAD0		160
-#define AUD_CLKID_TDM_SCLK_PAD1		161
-#define AUD_CLKID_TDM_SCLK_PAD2		162
-#define AUD_CLKID_TOP			163
-#define AUD_CLKID_TORAM			164
-#define AUD_CLKID_EQDRC			165
-#define AUD_CLKID_RESAMPLE_B		166
-#define AUD_CLKID_TOVAD			167
-#define AUD_CLKID_LOCKER		168
-#define AUD_CLKID_SPDIFIN_LB		169
-#define AUD_CLKID_FRDDR_D		170
-#define AUD_CLKID_TODDR_D		171
-#define AUD_CLKID_LOOPBACK_B		172
-
-#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
deleted file mode 100644
index 93752ea107e..00000000000
--- a/include/dt-bindings/clock/axg-clkc.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Meson-AXG clock tree IDs
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- */
-
-#ifndef __AXG_CLKC_H
-#define __AXG_CLKC_H
-
-#define CLKID_SYS_PLL				0
-#define CLKID_FIXED_PLL				1
-#define CLKID_FCLK_DIV2				2
-#define CLKID_FCLK_DIV3				3
-#define CLKID_FCLK_DIV4				4
-#define CLKID_FCLK_DIV5				5
-#define CLKID_FCLK_DIV7				6
-#define CLKID_GP0_PLL				7
-#define CLKID_CLK81				10
-#define CLKID_MPLL0				11
-#define CLKID_MPLL1				12
-#define CLKID_MPLL2				13
-#define CLKID_MPLL3				14
-#define CLKID_DDR				15
-#define CLKID_AUDIO_LOCKER			16
-#define CLKID_MIPI_DSI_HOST			17
-#define CLKID_ISA				18
-#define CLKID_PL301				19
-#define CLKID_PERIPHS				20
-#define CLKID_SPICC0				21
-#define CLKID_I2C				22
-#define CLKID_RNG0				23
-#define CLKID_UART0				24
-#define CLKID_MIPI_DSI_PHY			25
-#define CLKID_SPICC1				26
-#define CLKID_PCIE_A				27
-#define CLKID_PCIE_B				28
-#define CLKID_HIU_IFACE				29
-#define CLKID_ASSIST_MISC			30
-#define CLKID_SD_EMMC_B				31
-#define CLKID_SD_EMMC_C				32
-#define CLKID_DMA				33
-#define CLKID_SPI				34
-#define CLKID_AUDIO				35
-#define CLKID_ETH				36
-#define CLKID_UART1				37
-#define CLKID_G2D				38
-#define CLKID_USB0				39
-#define CLKID_USB1				40
-#define CLKID_RESET				41
-#define CLKID_USB				42
-#define CLKID_AHB_ARB0				43
-#define CLKID_EFUSE				44
-#define CLKID_BOOT_ROM				45
-#define CLKID_AHB_DATA_BUS			46
-#define CLKID_AHB_CTRL_BUS			47
-#define CLKID_USB1_DDR_BRIDGE			48
-#define CLKID_USB0_DDR_BRIDGE			49
-#define CLKID_MMC_PCLK				50
-#define CLKID_VPU_INTR				51
-#define CLKID_SEC_AHB_AHB3_BRIDGE		52
-#define CLKID_GIC				53
-#define CLKID_AO_MEDIA_CPU			54
-#define CLKID_AO_AHB_SRAM			55
-#define CLKID_AO_AHB_BUS			56
-#define CLKID_AO_IFACE				57
-#define CLKID_AO_I2C				58
-#define CLKID_SD_EMMC_B_CLK0			59
-#define CLKID_SD_EMMC_C_CLK0			60
-#define CLKID_HIFI_PLL				69
-#define CLKID_PCIE_CML_EN0			79
-#define CLKID_PCIE_CML_EN1			80
-#define CLKID_GEN_CLK				84
-#define CLKID_VPU_0_SEL				92
-#define CLKID_VPU_0				93
-#define CLKID_VPU_1_SEL				95
-#define CLKID_VPU_1				96
-#define CLKID_VPU				97
-#define CLKID_VAPB_0_SEL			99
-#define CLKID_VAPB_0				100
-#define CLKID_VAPB_1_SEL			102
-#define CLKID_VAPB_1				103
-#define CLKID_VAPB_SEL				104
-#define CLKID_VAPB				105
-#define CLKID_VCLK				106
-#define CLKID_VCLK2				107
-#define CLKID_VCLK_DIV1				122
-#define CLKID_VCLK_DIV2				123
-#define CLKID_VCLK_DIV4				124
-#define CLKID_VCLK_DIV6				125
-#define CLKID_VCLK_DIV12			126
-#define CLKID_VCLK2_DIV1			127
-#define CLKID_VCLK2_DIV2			128
-#define CLKID_VCLK2_DIV4			129
-#define CLKID_VCLK2_DIV6			130
-#define CLKID_VCLK2_DIV12			131
-#define CLKID_CTS_ENCL				133
-#define CLKID_VDIN_MEAS				136
-
-#endif /* __AXG_CLKC_H */