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authorMichael Walle <[email protected]>2021-10-13 18:14:26 +0200
committerPriyanka Jain <[email protected]>2021-11-09 17:18:23 +0530
commit7f900eabf7d665ccd1ae8cdf7743a0ea46ec13b2 (patch)
tree0796f7941858d56faadde6957eb5c2e8205a3f8b /include/dt-bindings/clock
parentd08011d7f9b4dfb846b61dbdd5ced92d0ba2a259 (diff)
arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the linux kernel v5.14.12. Notable changes: - second watchdog added - the number of chip selects of the SPI controller is now correct and reflects what the hardware offers - the LPUARTs have the correct clock parent - USB controllers are enabled by default, which was already the case before this sync because all board enabled all the USB controller nodes. A linux patch to fix this is pending. - the eSDHC controller changes from big-endian to little-endian, but that property seems to be not used at all. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Priyanka Jain <[email protected]>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/fsl,qoriq-clockgen.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
new file mode 100644
index 00000000000..ddec7d0bdc7
--- /dev/null
+++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
+
+#define QORIQ_CLK_SYSCLK 0
+#define QORIQ_CLK_CMUX 1
+#define QORIQ_CLK_HWACCEL 2
+#define QORIQ_CLK_FMAN 3
+#define QORIQ_CLK_PLATFORM_PLL 4
+#define QORIQ_CLK_CORECLK 5
+
+#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
+
+#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */