include/dt-bindings: Remove functionally identical headers

As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and differ only in combinations of spacing changes and/or
switching to SPDX license tags. We can safely remove the copies under
include/dt-bindings now to prevent future conflicts.

Signed-off-by: Tom Rini <[email protected]>

7 files changed, 0 insertions, 347 deletions

diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
deleted file mode 100644
index 765c385f7b2..00000000000
--- a/include/dt-bindings/pinctrl/dra.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This header provides constants for DRA pinctrl bindings.
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- * Author: Rajendra Nayak <[email protected]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_DRA_H
-#define _DT_BINDINGS_PINCTRL_DRA_H
-
-/* DRA7 mux mode options for each pin. See TRM for options */
-#define MUX_MODE0	0x0
-#define MUX_MODE1	0x1
-#define MUX_MODE2	0x2
-#define MUX_MODE3	0x3
-#define MUX_MODE4	0x4
-#define MUX_MODE5	0x5
-#define MUX_MODE6	0x6
-#define MUX_MODE7	0x7
-#define MUX_MODE8	0x8
-#define MUX_MODE9	0x9
-#define MUX_MODE10	0xa
-#define MUX_MODE11	0xb
-#define MUX_MODE12	0xc
-#define MUX_MODE13	0xd
-#define MUX_MODE14	0xe
-#define MUX_MODE15	0xf
-
-/* Certain pins need virtual mode, but note: they may glitch */
-#define MUX_VIRTUAL_MODE0	(MODE_SELECT | (0x0 << 4))
-#define MUX_VIRTUAL_MODE1	(MODE_SELECT | (0x1 << 4))
-#define MUX_VIRTUAL_MODE2	(MODE_SELECT | (0x2 << 4))
-#define MUX_VIRTUAL_MODE3	(MODE_SELECT | (0x3 << 4))
-#define MUX_VIRTUAL_MODE4	(MODE_SELECT | (0x4 << 4))
-#define MUX_VIRTUAL_MODE5	(MODE_SELECT | (0x5 << 4))
-#define MUX_VIRTUAL_MODE6	(MODE_SELECT | (0x6 << 4))
-#define MUX_VIRTUAL_MODE7	(MODE_SELECT | (0x7 << 4))
-#define MUX_VIRTUAL_MODE8	(MODE_SELECT | (0x8 << 4))
-#define MUX_VIRTUAL_MODE9	(MODE_SELECT | (0x9 << 4))
-#define MUX_VIRTUAL_MODE10	(MODE_SELECT | (0xa << 4))
-#define MUX_VIRTUAL_MODE11	(MODE_SELECT | (0xb << 4))
-#define MUX_VIRTUAL_MODE12	(MODE_SELECT | (0xc << 4))
-#define MUX_VIRTUAL_MODE13	(MODE_SELECT | (0xd << 4))
-#define MUX_VIRTUAL_MODE14	(MODE_SELECT | (0xe << 4))
-#define MUX_VIRTUAL_MODE15	(MODE_SELECT | (0xf << 4))
-
-#define MODE_SELECT		(1 << 8)
-
-#define PULL_ENA		(0 << 16)
-#define PULL_DIS		(1 << 16)
-#define PULL_UP			(1 << 17)
-#define INPUT_EN		(1 << 18)
-#define SLEWCONTROL		(1 << 19)
-#define WAKEUP_EN		(1 << 24)
-#define WAKEUP_EVENT		(1 << 25)
-
-/* Active pin states */
-#define PIN_OUTPUT		(0 | PULL_DIS)
-#define PIN_OUTPUT_PULLUP	(PULL_UP)
-#define PIN_OUTPUT_PULLDOWN	(0)
-#define PIN_INPUT		(INPUT_EN | PULL_DIS)
-#define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
-#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
-
-/*
- * Macro to allow using the absolute physical address instead of the
- * padconf registers instead of the offset from padconf base.
- */
-#define DRA7XX_CORE_IOPAD(pa, val)	(((pa) & 0xffff) - 0x3400) (val)
-
-/* DRA7 IODELAY configuration parameters */
-#define A_DELAY_PS(val)			((val) & 0xffff)
-#define G_DELAY_PS(val)			((val) & 0xffff)
-#endif
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
deleted file mode 100644
index 0359bfdc911..00000000000
--- a/include/dt-bindings/pinctrl/hisi.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This header provides constants for hisilicon pinctrl bindings.
- *
- * Copyright (c) 2015 Hisilicon Limited.
- * Copyright (c) 2015 Linaro Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_HISI_H
-#define _DT_BINDINGS_PINCTRL_HISI_H
-
-/* iomg bit definition */
-#define MUX_M0		0
-#define MUX_M1		1
-#define MUX_M2		2
-#define MUX_M3		3
-#define MUX_M4		4
-#define MUX_M5		5
-#define MUX_M6		6
-#define MUX_M7		7
-
-/* iocg bit definition */
-#define PULL_MASK	(3)
-#define PULL_DIS	(0)
-#define PULL_UP		(1 << 0)
-#define PULL_DOWN	(1 << 1)
-
-/* drive strength definition */
-#define DRIVE_MASK	(7 << 4)
-#define DRIVE1_02MA	(0 << 4)
-#define DRIVE1_04MA	(1 << 4)
-#define DRIVE1_08MA	(2 << 4)
-#define DRIVE1_10MA	(3 << 4)
-#define DRIVE2_02MA	(0 << 4)
-#define DRIVE2_04MA	(1 << 4)
-#define DRIVE2_08MA	(2 << 4)
-#define DRIVE2_10MA	(3 << 4)
-#define DRIVE3_04MA	(0 << 4)
-#define DRIVE3_08MA	(1 << 4)
-#define DRIVE3_12MA	(2 << 4)
-#define DRIVE3_16MA	(3 << 4)
-#define DRIVE3_20MA	(4 << 4)
-#define DRIVE3_24MA	(5 << 4)
-#define DRIVE3_32MA	(6 << 4)
-#define DRIVE3_40MA	(7 << 4)
-#define DRIVE4_02MA	(0 << 4)
-#define DRIVE4_04MA	(2 << 4)
-#define DRIVE4_08MA	(4 << 4)
-#define DRIVE4_10MA	(6 << 4)
-
-/* drive strength definition for hi3660 */
-#define DRIVE6_MASK	(15 << 4)
-#define DRIVE6_04MA	(0 << 4)
-#define DRIVE6_12MA	(4 << 4)
-#define DRIVE6_19MA	(8 << 4)
-#define DRIVE6_27MA	(10 << 4)
-#define DRIVE6_32MA	(15 << 4)
-#define DRIVE7_02MA	(0 << 4)
-#define DRIVE7_04MA	(1 << 4)
-#define DRIVE7_06MA	(2 << 4)
-#define DRIVE7_08MA	(3 << 4)
-#define DRIVE7_10MA	(4 << 4)
-#define DRIVE7_12MA	(5 << 4)
-#define DRIVE7_14MA	(6 << 4)
-#define DRIVE7_16MA	(7 << 4)
-#endif
diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h
deleted file mode 100644
index fbea8d35bcf..00000000000
--- a/include/dt-bindings/pinctrl/mt65xx.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2022 MediaTek Inc.
- * Author: Hongzhou.Yang <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H
-#define _DT_BINDINGS_PINCTRL_MT65XX_H
-
-#define MTK_PIN_NO(x)		((x) << 8)
-#define MTK_GET_PIN_NO(x)	((x) >> 8)
-#define MTK_GET_PIN_FUNC(x)	((x) & 0xf)
-
-#define MTK_PUPD_SET_R1R0_00	100
-#define MTK_PUPD_SET_R1R0_01	101
-#define MTK_PUPD_SET_R1R0_10	102
-#define MTK_PUPD_SET_R1R0_11	103
-
-#define MTK_PULL_SET_RSEL_000	200
-#define MTK_PULL_SET_RSEL_001	201
-#define MTK_PULL_SET_RSEL_010	202
-#define MTK_PULL_SET_RSEL_011	203
-#define MTK_PULL_SET_RSEL_100	204
-#define MTK_PULL_SET_RSEL_101	205
-#define MTK_PULL_SET_RSEL_110	206
-#define MTK_PULL_SET_RSEL_111	207
-
-#define MTK_DRIVE_2mA		2
-#define MTK_DRIVE_4mA		4
-#define MTK_DRIVE_6mA		6
-#define MTK_DRIVE_8mA		8
-#define MTK_DRIVE_10mA		10
-#define MTK_DRIVE_12mA		12
-#define MTK_DRIVE_14mA		14
-#define MTK_DRIVE_16mA		16
-#define MTK_DRIVE_20mA		20
-#define MTK_DRIVE_24mA		24
-#define MTK_DRIVE_28mA		28
-#define MTK_DRIVE_32mA		32
-
-#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
deleted file mode 100644
index 4c060ee0e0a..00000000000
--- a/include/dt-bindings/pinctrl/omap.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for OMAP pinctrl bindings.
- *
- * Copyright (C) 2009 Nokia
- * Copyright (C) 2009-2010 Texas Instruments
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
-#define _DT_BINDINGS_PINCTRL_OMAP_H
-
-/* 34xx mux mode options for each pin. See TRM for options */
-#define MUX_MODE0	0
-#define MUX_MODE1	1
-#define MUX_MODE2	2
-#define MUX_MODE3	3
-#define MUX_MODE4	4
-#define MUX_MODE5	5
-#define MUX_MODE6	6
-#define MUX_MODE7	7
-
-/* 24xx/34xx mux bit defines */
-#define PULL_ENA		(1 << 3)
-#define PULL_UP			(1 << 4)
-#define ALTELECTRICALSEL	(1 << 5)
-
-/* omap3/4/5 specific mux bit defines */
-#define INPUT_EN		(1 << 8)
-#define OFF_EN			(1 << 9)
-#define OFFOUT_EN		(1 << 10)
-#define OFFOUT_VAL		(1 << 11)
-#define OFF_PULL_EN		(1 << 12)
-#define OFF_PULL_UP		(1 << 13)
-#define WAKEUP_EN		(1 << 14)
-#define WAKEUP_EVENT		(1 << 15)
-
-/* Active pin states */
-#define PIN_OUTPUT		0
-#define PIN_OUTPUT_PULLUP	(PIN_OUTPUT | PULL_ENA | PULL_UP)
-#define PIN_OUTPUT_PULLDOWN	(PIN_OUTPUT | PULL_ENA)
-#define PIN_INPUT		INPUT_EN
-#define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
-
-/* Off mode states */
-#define PIN_OFF_NONE		0
-#define PIN_OFF_OUTPUT_HIGH	(OFF_EN | OFFOUT_EN | OFFOUT_VAL)
-#define PIN_OFF_OUTPUT_LOW	(OFF_EN | OFFOUT_EN)
-#define PIN_OFF_INPUT_PULLUP	(OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP)
-#define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFFOUT_EN | OFF_PULL_EN)
-#define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
-
-/*
- * Macros to allow using the absolute physical address instead of the
- * padconf registers instead of the offset from padconf base.
- */
-#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
-
-#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
-#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
-#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
-#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
-#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
-#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
-#define DM814X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define DM816X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
-#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0)
-#define AM33XX_PADCONF(pa, conf, mux)	OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux)
-
-/*
- * Macros to allow using the offset from the padconf physical address
- * instead  of the offset from padconf base.
- */
-#define OMAP_PADCONF_OFFSET(offset, base_offset)	((offset) - (base_offset))
-
-#define OMAP4_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
-#define OMAP5_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
-
-/*
- * Define some commonly used pins configured by the boards.
- * Note that some boards use alternative pins, so check
- * the schematics before using these.
- */
-#define OMAP3_UART1_RX		0x152
-#define OMAP3_UART2_RX		0x14a
-#define OMAP3_UART3_RX		0x16e
-#define OMAP4_UART2_RX		0xdc
-#define OMAP4_UART3_RX		0x104
-#define OMAP4_UART4_RX		0x11c
-
-#endif
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
deleted file mode 100644
index 914d56da932..00000000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
-
-#define TEGRA_XUSB_PADCTL_PCIE 0
-#define TEGRA_XUSB_PADCTL_SATA 1
-
-#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h
deleted file mode 100644
index c9b57408de6..00000000000
--- a/include/dt-bindings/pinctrl/pinctrl-tegra.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for Tegra pinctrl bindings.
- *
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * Author: Laxman Dewangan <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
-#define _DT_BINDINGS_PINCTRL_TEGRA_H
-
-/*
- * Enable/disable for diffeent dt properties. This is applicable for
- * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
- * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
- */
-#define TEGRA_PIN_DISABLE				0
-#define TEGRA_PIN_ENABLE				1
-
-#define TEGRA_PIN_PULL_NONE				0
-#define TEGRA_PIN_PULL_DOWN				1
-#define TEGRA_PIN_PULL_UP				2
-
-/* Low power mode driver */
-#define TEGRA_PIN_LP_DRIVE_DIV_8			0
-#define TEGRA_PIN_LP_DRIVE_DIV_4			1
-#define TEGRA_PIN_LP_DRIVE_DIV_2			2
-#define TEGRA_PIN_LP_DRIVE_DIV_1			3
-
-/* Rising/Falling slew rate */
-#define TEGRA_PIN_SLEW_RATE_FASTEST			0
-#define TEGRA_PIN_SLEW_RATE_FAST			1
-#define TEGRA_PIN_SLEW_RATE_SLOW			2
-#define TEGRA_PIN_SLEW_RATE_SLOWEST			3
-
-#endif
diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
deleted file mode 100644
index 31ee37610eb..00000000000
--- a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Defines macros and constants for Renesas RZ/A1 pin controller pin
- * muxing functions.
- */
-#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
-#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H
-
-#define RZA1_PINS_PER_PORT	16
-
-/*
- * Create the pin index from its bank and position numbers and store in
- * the upper 16 bits the alternate function identifier
- */
-#define RZA1_PINMUX(b, p, f)	\
-	((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16))
-
-#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */