include/dt-bindings: Remove functionally identical headers

As part of moving to using OF_UPSTREAM and so the upstream dt-bindings
headers we have a number of these headers that are in our include
directory and differ only in combinations of spacing changes and/or
switching to SPDX license tags. We can safely remove the copies under
include/dt-bindings now to prevent future conflicts.

Signed-off-by: Tom Rini <[email protected]>

10 files changed, 0 insertions, 629 deletions

diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h
deleted file mode 100644
index acb0bbf4f9f..00000000000
--- a/include/dt-bindings/reset/altr,rst-mgr-a10.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2014, Steffen Trumtrar <[email protected]>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
-
-/* MPUMODRST */
-#define CPU0_RESET		0
-#define CPU1_RESET		1
-#define WDS_RESET		2
-#define SCUPER_RESET		3
-
-/* PER0MODRST */
-#define EMAC0_RESET		32
-#define EMAC1_RESET		33
-#define EMAC2_RESET		34
-#define USB0_RESET		35
-#define USB1_RESET		36
-#define NAND_RESET		37
-#define QSPI_RESET		38
-#define SDMMC_RESET		39
-#define EMAC0_OCP_RESET		40
-#define EMAC1_OCP_RESET		41
-#define EMAC2_OCP_RESET		42
-#define USB0_OCP_RESET		43
-#define USB1_OCP_RESET		44
-#define NAND_OCP_RESET		45
-#define QSPI_OCP_RESET		46
-#define SDMMC_OCP_RESET		47
-#define DMA_RESET		48
-#define SPIM0_RESET		49
-#define SPIM1_RESET		50
-#define SPIS0_RESET		51
-#define SPIS1_RESET		52
-#define DMA_OCP_RESET		53
-#define EMAC_PTP_RESET		54
-/* 55 is empty*/
-#define DMAIF0_RESET		56
-#define DMAIF1_RESET		57
-#define DMAIF2_RESET		58
-#define DMAIF3_RESET		59
-#define DMAIF4_RESET		60
-#define DMAIF5_RESET		61
-#define DMAIF6_RESET		62
-#define DMAIF7_RESET		63
-
-/* PER1MODRST */
-#define L4WD0_RESET		64
-#define L4WD1_RESET		65
-#define L4SYSTIMER0_RESET	66
-#define L4SYSTIMER1_RESET	67
-#define SPTIMER0_RESET		68
-#define SPTIMER1_RESET		69
-/* 70-71 is reserved */
-#define I2C0_RESET		72
-#define I2C1_RESET		73
-#define I2C2_RESET		74
-#define I2C3_RESET		75
-#define I2C4_RESET		76
-/* 77-79 is reserved */
-#define UART0_RESET		80
-#define UART1_RESET		81
-/* 82-87 is reserved */
-#define GPIO0_RESET		88
-#define GPIO1_RESET		89
-#define GPIO2_RESET		90
-
-/* BRGMODRST */
-#define HPS2FPGA_RESET		96
-#define LWHPS2FPGA_RESET	97
-#define FPGA2HPS_RESET		98
-#define F2SSDRAM0_RESET		99
-#define F2SSDRAM1_RESET		100
-#define F2SSDRAM2_RESET		101
-#define DDRSCH_RESET		102
-
-/* SYSMODRST*/
-#define ROM_RESET		128
-#define OCRAM_RESET		129
-/* 130 is reserved */
-#define FPGAMGR_RESET		131
-#define S2F_RESET		132
-#define SYSDBG_RESET		133
-#define OCRAM_OCP_RESET		134
-
-/* COLDMODRST */
-#define CLKMGRCOLD_RESET	160
-/* 161-162 is reserved */
-#define S2FCOLD_RESET		163
-#define TIMESTAMPCOLD_RESET	164
-#define TAPCOLD_RESET		165
-#define HMCCOLD_RESET		166
-#define IOMGRCOLD_RESET		167
-
-/* NRSTMODRST */
-#define NRSTPINOE_RESET		192
-
-/* DBGMODRST */
-#define DBG_RESET		224
-#endif
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h
deleted file mode 100644
index 5b7ad739652..00000000000
--- a/include/dt-bindings/reset/altr,rst-mgr.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2014, Steffen Trumtrar <[email protected]>
- */
-
-#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
-#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
-
-/* MPUMODRST */
-#define CPU0_RESET		0
-#define CPU1_RESET		1
-#define WDS_RESET		2
-#define SCUPER_RESET		3
-#define L2_RESET		4
-
-/* PERMODRST */
-#define EMAC0_RESET		32
-#define EMAC1_RESET		33
-#define USB0_RESET		34
-#define USB1_RESET		35
-#define NAND_RESET		36
-#define QSPI_RESET		37
-#define L4WD0_RESET		38
-#define L4WD1_RESET		39
-#define OSC1TIMER0_RESET	40
-#define OSC1TIMER1_RESET	41
-#define SPTIMER0_RESET		42
-#define SPTIMER1_RESET		43
-#define I2C0_RESET		44
-#define I2C1_RESET		45
-#define I2C2_RESET		46
-#define I2C3_RESET		47
-#define UART0_RESET		48
-#define UART1_RESET		49
-#define SPIM0_RESET		50
-#define SPIM1_RESET		51
-#define SPIS0_RESET		52
-#define SPIS1_RESET		53
-#define SDMMC_RESET		54
-#define CAN0_RESET		55
-#define CAN1_RESET		56
-#define GPIO0_RESET		57
-#define GPIO1_RESET		58
-#define GPIO2_RESET		59
-#define DMA_RESET		60
-#define SDR_RESET		61
-
-/* PER2MODRST */
-#define DMAIF0_RESET		64
-#define DMAIF1_RESET		65
-#define DMAIF2_RESET		66
-#define DMAIF3_RESET		67
-#define DMAIF4_RESET		68
-#define DMAIF5_RESET		69
-#define DMAIF6_RESET		70
-#define DMAIF7_RESET		71
-
-/* BRGMODRST */
-#define HPS2FPGA_RESET		96
-#define LWHPS2FPGA_RESET	97
-#define FPGA2HPS_RESET		98
-
-/* MISCMODRST*/
-#define ROM_RESET		128
-#define OCRAM_RESET		129
-#define SYSMGR_RESET		130
-#define SYSMGRCOLD_RESET	131
-#define FPGAMGR_RESET		132
-#define ACPIDMAP_RESET		133
-#define S2F_RESET		134
-#define S2FCOLD_RESET		135
-#define NRSTPIN_RESET		136
-#define TIMESTAMPCOLD_RESET	137
-#define CLKMGRCOLD_RESET	138
-#define SCANMGR_RESET		139
-#define FRZCTRLCOLD_RESET	140
-#define SYSDBG_RESET		141
-#define DBG_RESET		142
-#define TAPCOLD_RESET		143
-#define SDRCOLD_RESET		144
-
-#endif
diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h
deleted file mode 100644
index f2dd4f79cc6..00000000000
--- a/include/dt-bindings/reset/bcm6328-reset.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6328_H
-#define __DT_BINDINGS_RESET_BCM6328_H
-
-#define BCM6328_RST_SPI		0
-#define BCM6328_RST_EPHY	1
-#define BCM6328_RST_SAR		2
-#define BCM6328_RST_ENETSW	3
-#define BCM6328_RST_USBS	4
-#define BCM6328_RST_USBH	5
-#define BCM6328_RST_PCM		6
-#define BCM6328_RST_PCIE_CORE	7
-#define BCM6328_RST_PCIE	8
-#define BCM6328_RST_PCIE_EXT	9
-#define BCM6328_RST_PCIE_HARD	10
-
-#endif /* __DT_BINDINGS_RESET_BCM6328_H */
diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h
deleted file mode 100644
index 075706eff7a..00000000000
--- a/include/dt-bindings/reset/bcm6358-reset.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6358_H
-#define __DT_BINDINGS_RESET_BCM6358_H
-
-#define BCM6358_RST_SPI		0
-#define BCM6358_RST_ENET	2
-#define BCM6358_RST_MPI		3
-#define BCM6358_RST_EPHY	6
-#define BCM6358_RST_SAR		7
-#define BCM6358_RST_USBH	12
-#define BCM6358_RST_PCM		13
-#define BCM6358_RST_ADSL	14
-
-#endif /* __DT_BINDINGS_RESET_BCM6358_H */
diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h
deleted file mode 100644
index 8202e499190..00000000000
--- a/include/dt-bindings/reset/bcm6362-reset.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Álvaro Fernández Rojas <[email protected]>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6362_H
-#define __DT_BINDINGS_RESET_BCM6362_H
-
-#define BCM6362_RST_SPI		0
-#define BCM6362_RST_IPSEC	1
-#define BCM6362_RST_EPHY	2
-#define BCM6362_RST_SAR		3
-#define BCM6362_RST_ENETSW	4
-#define BCM6362_RST_USBD	5
-#define BCM6362_RST_USBH	6
-#define BCM6362_RST_PCM		7
-#define BCM6362_RST_PCIE_CORE	8
-#define BCM6362_RST_PCIE	9
-#define BCM6362_RST_PCIE_EXT	10
-#define BCM6362_RST_WLAN_SHIM	11
-#define BCM6362_RST_DDR_PHY	12
-#define BCM6362_RST_FAP		13
-#define BCM6362_RST_WLAN_UBUS	14
-
-#endif /* __DT_BINDINGS_RESET_BCM6362_H */
diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h
deleted file mode 100644
index 0038a7ccf5c..00000000000
--- a/include/dt-bindings/reset/bcm6368-reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
- *
- * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
- */
-
-#ifndef __DT_BINDINGS_RESET_BCM6368_H
-#define __DT_BINDINGS_RESET_BCM6368_H
-
-#define BCM6368_RST_SPI		0
-#define BCM6368_RST_MPI		3
-#define BCM6368_RST_IPSEC	4
-#define BCM6368_RST_EPHY	6
-#define BCM6368_RST_SAR		7
-#define BCM6368_RST_SWITCH	10
-#define BCM6368_RST_USBD	11
-#define BCM6368_RST_USBH	12
-#define BCM6368_RST_PCM		13
-
-#endif /* __DT_BINDINGS_RESET_BCM6368_H */
diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
deleted file mode 100644
index 757f5e34c81..00000000000
--- a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-// Copyright (c) 2020 Nuvoton Technology corporation.
-
-#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
-#define _DT_BINDINGS_NPCM7XX_RESET_H
-
-#define NPCM7XX_RESET_IPSRST1		0x20
-#define NPCM7XX_RESET_IPSRST2		0x24
-#define NPCM7XX_RESET_IPSRST3		0x34
-
-/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
-#define NPCM7XX_RESET_FIU3		1
-#define NPCM7XX_RESET_UDC1		5
-#define NPCM7XX_RESET_EMC1		6
-#define NPCM7XX_RESET_UART_2_3		7
-#define NPCM7XX_RESET_UDC2		8
-#define NPCM7XX_RESET_PECI		9
-#define NPCM7XX_RESET_AES		10
-#define NPCM7XX_RESET_UART_0_1		11
-#define NPCM7XX_RESET_MC		12
-#define NPCM7XX_RESET_SMB2		13
-#define NPCM7XX_RESET_SMB3		14
-#define NPCM7XX_RESET_SMB4		15
-#define NPCM7XX_RESET_SMB5		16
-#define NPCM7XX_RESET_PWM_M0		18
-#define NPCM7XX_RESET_TIMER_0_4		19
-#define NPCM7XX_RESET_TIMER_5_9		20
-#define NPCM7XX_RESET_EMC2		21
-#define NPCM7XX_RESET_UDC4		22
-#define NPCM7XX_RESET_UDC5		23
-#define NPCM7XX_RESET_UDC6		24
-#define NPCM7XX_RESET_UDC3		25
-#define NPCM7XX_RESET_ADC		27
-#define NPCM7XX_RESET_SMB6		28
-#define NPCM7XX_RESET_SMB7		29
-#define NPCM7XX_RESET_SMB0		30
-#define NPCM7XX_RESET_SMB1		31
-
-/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
-#define NPCM7XX_RESET_MFT0		0
-#define NPCM7XX_RESET_MFT1		1
-#define NPCM7XX_RESET_MFT2		2
-#define NPCM7XX_RESET_MFT3		3
-#define NPCM7XX_RESET_MFT4		4
-#define NPCM7XX_RESET_MFT5		5
-#define NPCM7XX_RESET_MFT6		6
-#define NPCM7XX_RESET_MFT7		7
-#define NPCM7XX_RESET_MMC		8
-#define NPCM7XX_RESET_SDHC		9
-#define NPCM7XX_RESET_GFX_SYS		10
-#define NPCM7XX_RESET_AHB_PCIBRG	11
-#define NPCM7XX_RESET_VDMA		12
-#define NPCM7XX_RESET_ECE		13
-#define NPCM7XX_RESET_VCD		14
-#define NPCM7XX_RESET_OTP		16
-#define NPCM7XX_RESET_SIOX1		18
-#define NPCM7XX_RESET_SIOX2		19
-#define NPCM7XX_RESET_3DES		21
-#define NPCM7XX_RESET_PSPI1		22
-#define NPCM7XX_RESET_PSPI2		23
-#define NPCM7XX_RESET_GMAC2		25
-#define NPCM7XX_RESET_USB_HOST		26
-#define NPCM7XX_RESET_GMAC1		28
-#define NPCM7XX_RESET_CP		31
-
-/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
-#define NPCM7XX_RESET_PWM_M1		0
-#define NPCM7XX_RESET_SMB12		1
-#define NPCM7XX_RESET_SPIX		2
-#define NPCM7XX_RESET_SMB13		3
-#define NPCM7XX_RESET_UDC0		4
-#define NPCM7XX_RESET_UDC7		5
-#define NPCM7XX_RESET_UDC8		6
-#define NPCM7XX_RESET_UDC9		7
-#define NPCM7XX_RESET_PCI_MAILBOX	9
-#define NPCM7XX_RESET_SMB14		12
-#define NPCM7XX_RESET_SHA		13
-#define NPCM7XX_RESET_SEC_ECC		14
-#define NPCM7XX_RESET_PCIE_RC		15
-#define NPCM7XX_RESET_TIMER_10_14	16
-#define NPCM7XX_RESET_RNG		17
-#define NPCM7XX_RESET_SMB15		18
-#define NPCM7XX_RESET_SMB8		19
-#define NPCM7XX_RESET_SMB9		20
-#define NPCM7XX_RESET_SMB10		21
-#define NPCM7XX_RESET_SMB11		22
-#define NPCM7XX_RESET_ESPI		23
-#define NPCM7XX_RESET_USB_PHY_1		24
-#define NPCM7XX_RESET_USB_PHY_2		25
-
-#endif
diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h
deleted file mode 100644
index 070e4f6e748..00000000000
--- a/include/dt-bindings/reset/tegra124-car.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * This header provides Tegra124-specific constants for binding
- * nvidia,tegra124-car.
- */
-
-#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
-#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
-
-#define TEGRA124_RESET(x)		(6 * 32 + (x))
-#define TEGRA124_RST_DFLL_DVCO		TEGRA124_RESET(0)
-
-#endif	/* _DT_BINDINGS_RESET_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h
deleted file mode 100644
index 7efec920053..00000000000
--- a/include/dt-bindings/reset/tegra186-reset.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION.
- */
-
-#ifndef _ABI_MACH_T186_RESET_T186_H_
-#define _ABI_MACH_T186_RESET_T186_H_
-
-#define TEGRA186_RESET_ACTMON			0
-#define TEGRA186_RESET_AFI			1
-#define TEGRA186_RESET_CEC			2
-#define TEGRA186_RESET_CSITE			3
-#define TEGRA186_RESET_DP2			4
-#define TEGRA186_RESET_DPAUX			5
-#define TEGRA186_RESET_DSI			6
-#define TEGRA186_RESET_DSIB			7
-#define TEGRA186_RESET_DTV			8
-#define TEGRA186_RESET_DVFS			9
-#define TEGRA186_RESET_ENTROPY			10
-#define TEGRA186_RESET_EXTPERIPH1		11
-#define TEGRA186_RESET_EXTPERIPH2		12
-#define TEGRA186_RESET_EXTPERIPH3		13
-#define TEGRA186_RESET_GPU			14
-#define TEGRA186_RESET_HDA			15
-#define TEGRA186_RESET_HDA2CODEC_2X		16
-#define TEGRA186_RESET_HDA2HDMICODEC		17
-#define TEGRA186_RESET_HOST1X			18
-#define TEGRA186_RESET_I2C1			19
-#define TEGRA186_RESET_I2C2			20
-#define TEGRA186_RESET_I2C3			21
-#define TEGRA186_RESET_I2C4			22
-#define TEGRA186_RESET_I2C5			23
-#define TEGRA186_RESET_I2C6			24
-#define TEGRA186_RESET_ISP			25
-#define TEGRA186_RESET_KFUSE			26
-#define TEGRA186_RESET_LA			27
-#define TEGRA186_RESET_MIPI_CAL			28
-#define TEGRA186_RESET_PCIE			29
-#define TEGRA186_RESET_PCIEXCLK			30
-#define TEGRA186_RESET_SATA			31
-#define TEGRA186_RESET_SATACOLD			32
-#define TEGRA186_RESET_SDMMC1			33
-#define TEGRA186_RESET_SDMMC2			34
-#define TEGRA186_RESET_SDMMC3			35
-#define TEGRA186_RESET_SDMMC4			36
-#define TEGRA186_RESET_SE			37
-#define TEGRA186_RESET_SOC_THERM		38
-#define TEGRA186_RESET_SOR0			39
-#define TEGRA186_RESET_SPI1			40
-#define TEGRA186_RESET_SPI2			41
-#define TEGRA186_RESET_SPI3			42
-#define TEGRA186_RESET_SPI4			43
-#define TEGRA186_RESET_TMR			44
-#define TEGRA186_RESET_TRIG_SYS			45
-#define TEGRA186_RESET_TSEC			46
-#define TEGRA186_RESET_UARTA			47
-#define TEGRA186_RESET_UARTB			48
-#define TEGRA186_RESET_UARTC			49
-#define TEGRA186_RESET_UARTD			50
-#define TEGRA186_RESET_VI			51
-#define TEGRA186_RESET_VIC			52
-#define TEGRA186_RESET_XUSB_DEV			53
-#define TEGRA186_RESET_XUSB_HOST		54
-#define TEGRA186_RESET_XUSB_PADCTL		55
-#define TEGRA186_RESET_XUSB_SS			56
-#define TEGRA186_RESET_AON_APB			57
-#define TEGRA186_RESET_AXI_CBB			58
-#define TEGRA186_RESET_BPMP_APB			59
-#define TEGRA186_RESET_CAN1			60
-#define TEGRA186_RESET_CAN2			61
-#define TEGRA186_RESET_DMIC5			62
-#define TEGRA186_RESET_DSIC			63
-#define TEGRA186_RESET_DSID			64
-#define TEGRA186_RESET_EMC_EMC			65
-#define TEGRA186_RESET_EMC_MEM			66
-#define TEGRA186_RESET_EMCSB_EMC		67
-#define TEGRA186_RESET_EMCSB_MEM		68
-#define TEGRA186_RESET_EQOS			69
-#define TEGRA186_RESET_GPCDMA			70
-#define TEGRA186_RESET_GPIO_CTL0		71
-#define TEGRA186_RESET_GPIO_CTL1		72
-#define TEGRA186_RESET_GPIO_CTL2		73
-#define TEGRA186_RESET_GPIO_CTL3		74
-#define TEGRA186_RESET_GPIO_CTL4		75
-#define TEGRA186_RESET_GPIO_CTL5		76
-#define TEGRA186_RESET_I2C10			77
-#define TEGRA186_RESET_I2C12			78
-#define TEGRA186_RESET_I2C13			79
-#define TEGRA186_RESET_I2C14			80
-#define TEGRA186_RESET_I2C7			81
-#define TEGRA186_RESET_I2C8			82
-#define TEGRA186_RESET_I2C9			83
-#define TEGRA186_RESET_JTAG2AXI			84
-#define TEGRA186_RESET_MPHY_IOBIST		85
-#define TEGRA186_RESET_MPHY_L0_RX		86
-#define TEGRA186_RESET_MPHY_L0_TX		87
-#define TEGRA186_RESET_NVCSI			88
-#define TEGRA186_RESET_NVDISPLAY0_HEAD0		89
-#define TEGRA186_RESET_NVDISPLAY0_HEAD1		90
-#define TEGRA186_RESET_NVDISPLAY0_HEAD2		91
-#define TEGRA186_RESET_NVDISPLAY0_MISC		92
-#define TEGRA186_RESET_NVDISPLAY0_WGRP0		93
-#define TEGRA186_RESET_NVDISPLAY0_WGRP1		94
-#define TEGRA186_RESET_NVDISPLAY0_WGRP2		95
-#define TEGRA186_RESET_NVDISPLAY0_WGRP3		96
-#define TEGRA186_RESET_NVDISPLAY0_WGRP4		97
-#define TEGRA186_RESET_NVDISPLAY0_WGRP5		98
-#define TEGRA186_RESET_PWM1			99
-#define TEGRA186_RESET_PWM2			100
-#define TEGRA186_RESET_PWM3			101
-#define TEGRA186_RESET_PWM4			102
-#define TEGRA186_RESET_PWM5			103
-#define TEGRA186_RESET_PWM6			104
-#define TEGRA186_RESET_PWM7			105
-#define TEGRA186_RESET_PWM8			106
-#define TEGRA186_RESET_SCE_APB			107
-#define TEGRA186_RESET_SOR1			108
-#define TEGRA186_RESET_TACH			109
-#define TEGRA186_RESET_TSC			110
-#define TEGRA186_RESET_UARTF			111
-#define TEGRA186_RESET_UARTG			112
-#define TEGRA186_RESET_UFSHC			113
-#define TEGRA186_RESET_UFSHC_AXI_M		114
-#define TEGRA186_RESET_UPHY			115
-#define TEGRA186_RESET_ADSP			116
-#define TEGRA186_RESET_ADSPDBG			117
-#define TEGRA186_RESET_ADSPINTF			118
-#define TEGRA186_RESET_ADSPNEON			119
-#define TEGRA186_RESET_ADSPPERIPH		120
-#define TEGRA186_RESET_ADSPSCU			121
-#define TEGRA186_RESET_ADSPWDT			122
-#define TEGRA186_RESET_APE			123
-#define TEGRA186_RESET_DPAUX1			124
-#define TEGRA186_RESET_NVDEC			125
-#define TEGRA186_RESET_NVENC			126
-#define TEGRA186_RESET_NVJPG			127
-#define TEGRA186_RESET_PEX_USB_UPHY		128
-#define TEGRA186_RESET_QSPI			129
-#define TEGRA186_RESET_TSECB			130
-#define TEGRA186_RESET_VI_I2C			131
-#define TEGRA186_RESET_UARTE			132
-#define TEGRA186_RESET_TOP_GTE			133
-#define TEGRA186_RESET_SHSP			134
-#define TEGRA186_RESET_PEX_USB_UPHY_L5		135
-#define TEGRA186_RESET_PEX_USB_UPHY_L4		136
-#define TEGRA186_RESET_PEX_USB_UPHY_L3		137
-#define TEGRA186_RESET_PEX_USB_UPHY_L2		138
-#define TEGRA186_RESET_PEX_USB_UPHY_L1		139
-#define TEGRA186_RESET_PEX_USB_UPHY_L0		140
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL1	141
-#define TEGRA186_RESET_PEX_USB_UPHY_PLL0	142
-#define TEGRA186_RESET_TSCTNVI			143
-#define TEGRA186_RESET_EXTPERIPH4		144
-#define TEGRA186_RESET_DSIPADCTL		145
-#define TEGRA186_RESET_AUD_MCLK			146
-#define TEGRA186_RESET_MPHY_CLK_CTL		147
-#define TEGRA186_RESET_MPHY_L1_RX		148
-#define TEGRA186_RESET_MPHY_L1_TX		149
-#define TEGRA186_RESET_UFSHC_LP			150
-#define TEGRA186_RESET_BPMP_NIC			151
-#define TEGRA186_RESET_BPMP_NSYSPORESET		152
-#define TEGRA186_RESET_BPMP_NRESET		153
-#define TEGRA186_RESET_BPMP_DBGRESETN		154
-#define TEGRA186_RESET_BPMP_PRESETDBGN		155
-#define TEGRA186_RESET_BPMP_PM			156
-#define TEGRA186_RESET_BPMP_CVC			157
-#define TEGRA186_RESET_BPMP_DMA			158
-#define TEGRA186_RESET_BPMP_HSP			159
-#define TEGRA186_RESET_TSCTNBPMP		160
-#define TEGRA186_RESET_BPMP_TKE			161
-#define TEGRA186_RESET_BPMP_GTE			162
-#define TEGRA186_RESET_BPMP_PM_ACTMON		163
-#define TEGRA186_RESET_AON_NIC			164
-#define TEGRA186_RESET_AON_NSYSPORESET		165
-#define TEGRA186_RESET_AON_NRESET		166
-#define TEGRA186_RESET_AON_DBGRESETN		167
-#define TEGRA186_RESET_AON_PRESETDBGN		168
-#define TEGRA186_RESET_AON_ACTMON		169
-#define TEGRA186_RESET_AOPM			170
-#define TEGRA186_RESET_AOVC			171
-#define TEGRA186_RESET_AON_DMA			172
-#define TEGRA186_RESET_AON_GPIO			173
-#define TEGRA186_RESET_AON_HSP			174
-#define TEGRA186_RESET_TSCTNAON			175
-#define TEGRA186_RESET_AON_TKE			176
-#define TEGRA186_RESET_AON_GTE			177
-#define TEGRA186_RESET_SCE_NIC			178
-#define TEGRA186_RESET_SCE_NSYSPORESET		179
-#define TEGRA186_RESET_SCE_NRESET		180
-#define TEGRA186_RESET_SCE_DBGRESETN		181
-#define TEGRA186_RESET_SCE_PRESETDBGN		182
-#define TEGRA186_RESET_SCE_ACTMON		183
-#define TEGRA186_RESET_SCE_PM			184
-#define TEGRA186_RESET_SCE_DMA			185
-#define TEGRA186_RESET_SCE_HSP			186
-#define TEGRA186_RESET_TSCTNSCE			187
-#define TEGRA186_RESET_SCE_TKE			188
-#define TEGRA186_RESET_SCE_GTE			189
-#define TEGRA186_RESET_SCE_CFG			190
-#define TEGRA186_RESET_ADSP_ALL			191
-/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */
-#define TEGRA186_RESET_UFSHC_LP_SEQ		192
-#define TEGRA186_RESET_SIZE			193
-
-#endif
diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h
deleted file mode 100644
index 1427ff140f1..00000000000
--- a/include/dt-bindings/reset/ti-syscon.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * TI Syscon Reset definitions
- *
- * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__
-#define __DT_BINDINGS_RESET_TI_SYSCON_H__
-
-/*
- * The reset does not support the feature and corresponding
- * values are not valid
- */
-#define ASSERT_NONE	(1 << 0)
-#define DEASSERT_NONE	(1 << 1)
-#define STATUS_NONE	(1 << 2)
-
-/* When set this function is activated by setting(vs clearing) this bit */
-#define ASSERT_SET	(1 << 3)
-#define DEASSERT_SET	(1 << 4)
-#define STATUS_SET	(1 << 5)
-
-/* The following are the inverse of the above and are added for consistency */
-#define ASSERT_CLEAR	(0 << 3)
-#define DEASSERT_CLEAR	(0 << 4)
-#define STATUS_CLEAR	(0 << 5)
-
-#endif