summaryrefslogtreecommitdiff
path: root/include/env
diff options
context:
space:
mode:
authorSvyatoslav Ryhel <[email protected]>2025-03-05 15:05:30 +0200
committerSvyatoslav Ryhel <[email protected]>2025-03-19 11:04:41 +0200
commit03f61b153965101f21783e8e6a1e5e86496598ff (patch)
tree8feefa87c48b417d82322096012b12dc910a1745 /include/env
parent13af58edb29d3ef840ff06e23fd7311b8c8aad9f (diff)
board: ouya: add Ouya Game Console support
The Ouya microconsole is build on Nvidia Tegra 3 (T33) SoC, featuring a quad-core 1.7 GHz ARM Cortex-A9 CPU and a ULP GeForce GPU, paired with 1GB of DDR3 RAM and 8GB of internal flash storage. Running a modified Android 4.1 (Jelly Bean) OS with a custom launcher, it aimed for open-source gaming via a digital storefront. This implementation is mostly based on upstream Linux device tree and fragments of work done by previous developers. Co-developed-by: Peter Geis <[email protected]> Signed-off-by: Peter Geis <[email protected]> Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'include/env')
-rw-r--r--include/env/nvidia/prod_upd.env5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/env/nvidia/prod_upd.env b/include/env/nvidia/prod_upd.env
index f4e381994be..6a457d1b75b 100644
--- a/include/env/nvidia/prod_upd.env
+++ b/include/env/nvidia/prod_upd.env
@@ -3,6 +3,7 @@ boot_block_size=0x1000
bootloader_file=u-boot-dtb-tegra.bin
spi_size=0x400000
boot_dev=0
+boot_interface=mmc
flash_uboot=echo Preparing RAM;
mw ${kernel_addr_r} 0 ${boot_block_size_r};
@@ -11,9 +12,9 @@ flash_uboot=echo Preparing RAM;
mmc dev 0 1;
mmc read ${kernel_addr_r} 0 ${boot_block_size};
echo Reading bootloader;
- if load mmc ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
+ if load ${boot_interface} ${boot_dev}:1 ${ramdisk_addr_r} ${bootloader_file};
then echo Calculating bootloader size;
- size mmc ${boot_dev}:1 ${bootloader_file};
+ size ${boot_interface} ${boot_dev}:1 ${bootloader_file};
ebtupdate ${kernel_addr_r} ${ramdisk_addr_r} ${filesize};
echo Writing bootloader to eMMC;
mmc dev 0 1;