diff options
| author | Marek Vasut <[email protected]> | 2024-07-23 01:28:34 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-07-29 15:01:04 -0600 |
| commit | 6627fbba203f89a316299d35f6a2ff3f33dd15c8 (patch) | |
| tree | cce8ae95fef0efc70c6ee256b3f007951aaec56f /include/gt64120.h | |
| parent | a1af57b70ad14fc490b5227d11c0edd954a81978 (diff) | |
include: Remove duplicate newlines
Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include/gt64120.h')
| -rw-r--r-- | include/gt64120.h | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/include/gt64120.h b/include/gt64120.h index b58afe3c4af..b8d3f03a5e0 100644 --- a/include/gt64120.h +++ b/include/gt64120.h @@ -221,7 +221,6 @@ #define GT_PCI0_HICMASK_OFS 0xca4 #define GT_PCI1_SERR1MASK_OFS 0xca8 - /* * I2O Support Registers */ @@ -283,7 +282,6 @@ #define GT_CPU_WR_DXDXDXDX 0 #define GT_CPU_WR_DDDD 1 - #define GT_PCI_DCRM_SHF 21 #define GT_PCI_LD_SHF 0 #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) @@ -292,7 +290,6 @@ #define GT_PCI_REMAP_SHF 0 #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) - #define GT_CFGADDR_CFGEN_SHF 31 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK @@ -309,7 +306,6 @@ #define GT_CFGADDR_REGNUM_SHF 2 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) - #define GT_SDRAM_BM_ORDER_SHF 2 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK @@ -318,7 +314,6 @@ #define GT_SDRAM_BM_RSVD_ALL1 0xffb - #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) #define GT_SDRAM_ADDRDECODE_ADDR_0 0 @@ -330,7 +325,6 @@ #define GT_SDRAM_ADDRDECODE_ADDR_6 6 #define GT_SDRAM_ADDRDECODE_ADDR_7 7 - #define GT_SDRAM_B0_CASLAT_SHF 0 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) #define GT_SDRAM_B0_CASLAT_2 1 @@ -396,7 +390,6 @@ #define GT_SDRAM_B0_BLEN_8 0 #define GT_SDRAM_B0_BLEN_4 1 - #define GT_SDRAM_CFG_REFINT_SHF 0 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) @@ -443,7 +436,6 @@ #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK - #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK \ (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) @@ -481,7 +473,6 @@ #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK - #define GT_INTRCAUSE_MASABORT0_SHF 18 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK @@ -490,7 +481,6 @@ #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - #define GT_PCI0_CMD_MBYTESWAP_SHF 0 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK |