diff options
| author | Tom Rini <[email protected]> | 2021-05-12 10:07:21 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2021-05-12 10:07:21 -0400 |
| commit | ea184cbff99ea1d82dcf94c95afe054e95da5069 (patch) | |
| tree | 48553e6cf25f0b5f34483c3fddafdebbbc240b55 /include/linux/soc/ti/ti_sci_protocol.h | |
| parent | 59a2b9e605c5a5e2dff35506a13b51f33d3051b4 (diff) | |
| parent | bbc9da58b332bd44e51ac5579040ea984b2f963b (diff) | |
Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti
- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
Diffstat (limited to 'include/linux/soc/ti/ti_sci_protocol.h')
| -rw-r--r-- | include/linux/soc/ti/ti_sci_protocol.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index eb916ba1019..794737923cf 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops { #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2 +#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3 + +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0 +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1 + /* UDMAP TX/RX channel valid_params common declarations */ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) @@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14) /** * Configures a Navigator Subsystem UDMAP transmit channel @@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16) u16 nav_id; u16 index; u8 tx_pause_on_err; @@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { u8 tx_orderid; u16 fdepth; u8 tx_sched_priority; + u8 tx_burst_size; + u8 tx_tdtype; + u8 extended_ch_type; }; /** @@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg { u8 rx_chan_type; u8 rx_ignore_short; u8 rx_ignore_long; + u8 rx_burst_size; }; /** |