diff options
| author | Patrice Chotard <[email protected]> | 2018-02-08 17:20:49 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2018-03-13 21:45:37 -0400 |
| commit | e8fb9ed2542ab6ca1946bec34a5232bde785f141 (patch) | |
| tree | 95e115e585b41b95a80b4f702ecf1be2d7619896 /include/linux/unaligned/be_byteshift.h | |
| parent | 1038e033e1e999b11568c8daf0a4e19b31086266 (diff) | |
clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock
Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.
PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.
Signed-off-by: Patrice Chotard <[email protected]>
Diffstat (limited to 'include/linux/unaligned/be_byteshift.h')
0 files changed, 0 insertions, 0 deletions