arm: aspeed: add ASPEED AST2700 SoC family support

Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35)
Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th
generation BMC and uses a dual-die architecture: SoC0 (the "CPU"
die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000,
while SoC1 (the "IO" die) hosts the peripherals and its own SCU at
0x14c02000.

This commit adds:
  - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir
    (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*)
  - arm64 MMU map covering the SoC device window and the DRAM
    region at 0x4_0000_0000 (up to 8 GiB)
  - lowlevel_init.S for early CPU bring-up
  - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants)
    and reset cause (cold reset, EXT reset, WDT reset)
  - board_common: dram_init via UCLASS_RAM, AHBC timeout init
  - platform: env_get_location() that selects SPI/eMMC based on
    the IO-die HW strap; arch_misc_init() that exposes
    ${boot_device} and ${verify} to the boot script
  - SCU0/SCU1 register layout header (scu_ast2700.h)
  - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h
    for the AST2700 EVB board

The defconfig depends on ast2700-evb.dts, which is introduced in
a subsequent patch; this commit must be applied with the
remaining series for evb-ast2700_defconfig to build.

Signed-off-by: Ryan Chen <[email protected]>

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