Merge patch series "ti: add speed grades support for AM62a"

Anshul Dalal <[email protected]> says:

TI offers SoCs in various speed grades, each speed grade specifies a
certain maximum operating frequency of the clocks for each core.

In K3's boot flow, the R5 SPL starts the A53 or A72 core and configures
the correct clocks and power using the K3 ARM64 rproc driver
(compatible: ti,am654-rproc). However, the driver expects the dt node
for the ARM64 core to be set with a correct "assigned-clock-rates"
value.

Currently the dt has a value of 1.2GHz for the A53 core on AM62a, this
is incorrect for lower speed grades. Therefore this patch set adds
support for fixing this value at runtime based on the detected speed
grade from the efuse MMR.

For the speed grade table, refer to Table 6-1 of the AM62a datasheet.

Link: https://www.ti.com/lit/ds/symlink/am62a7.pdf
Link: https://lore.kernel.org/r/[email protected]

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