diff options
| author | Murali Karicheri <[email protected]> | 2018-06-28 14:26:34 -0500 |
|---|---|---|
| committer | Joe Hershberger <[email protected]> | 2018-07-26 14:08:21 -0500 |
| commit | 63d319298452084d7aed2fe066d916605601939e (patch) | |
| tree | 5fbc4f3cef4cde164f29b8f2e9d285b7c5d938e0 /include/linux | |
| parent | fb7310769882c2fb9716352a78744327e72c2430 (diff) | |
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).
It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.
Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Signed-off-by: Murali Karicheri <[email protected]>
Reviewed-by: Hannes Schmelzer <[email protected]>
Acked-by: Joe Hershberger <[email protected]>
Tested-by: Siva Durga Prasad Paladugu <[email protected]>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions