diff options
| author | Frantisek Bohacek <[email protected]> | 2025-05-22 08:07:03 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-06-02 09:13:48 +0200 |
| commit | 90df44fb4f0e1cbe18b02080ef8bf9e365f867b8 (patch) | |
| tree | cc18ea08b8264845460d36274221293de903a248 /include/linux | |
| parent | 85f181b194c7d3810db4a0df8ea2386287b26be0 (diff) | |
phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)
Signed-off-by: Frantisek Bohacek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions