Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers

1 files changed, 1 insertions, 1 deletions

diff --git a/include/phy.h b/include/phy.h
index 9ea4bd42db4..5e3da4b01b6 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -479,7 +479,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  *			or NULL otherwise
  */
 struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
-				      phy_interface_t interface);
+				      int phyaddr, phy_interface_t interface);
 
 static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 {