power: regulator: mt6359: add driver for MT6359P

Add a new regulator driver for MT6359P and similar PMIC chips.

The MT6359P is a eco version for MT6359 regulator. For the MT8391
platform, we use the MT6359P (MT6365) as the main PMIC. The MT6359 and
MT6359P have different register maps. Therefore, on the MT8391 platform,
we only provide support for the MT6359P. If support for the MT6359 PMIC
it can be added later.

Signed-off-by: Bo-Chen Chen <[email protected]>
Signed-off-by: David Lechner <[email protected]>
Signed-off-by: Peng Fan <[email protected]>

2 files changed, 455 insertions, 0 deletions

diff --git a/include/power/mt6359.h b/include/power/mt6359.h
new file mode 100644
index 00000000000..1e0380e87b0
--- /dev/null
+++ b/include/power/mt6359.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 MediaTek Inc. All Rights Reserved.
+ * Author: Bo-Chen Chen <[email protected]>
+ */
+
+#ifndef __MT6359_H_
+#define __MT6359_H_
+
+#define MT6359_REGULATOR_DRIVER	"mt6359_regulator"
+
+enum {
+	MT6359_ID_VS1 = 0,
+	MT6359_ID_VGPU11,
+	MT6359_ID_VMODEM,
+	MT6359_ID_VPU,
+	MT6359_ID_VCORE,
+	MT6359_ID_VS2,
+	MT6359_ID_VPA,
+	MT6359_ID_VPROC2,
+	MT6359_ID_VPROC1,
+	MT6359_ID_VCORE_SSHUB,
+	MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB,
+	MT6359_ID_VAUD18 = 10,
+	MT6359_ID_VSIM1,
+	MT6359_ID_VIBR,
+	MT6359_ID_VRF12,
+	MT6359_ID_VUSB,
+	MT6359_ID_VSRAM_PROC2,
+	MT6359_ID_VIO18,
+	MT6359_ID_VCAMIO,
+	MT6359_ID_VCN18,
+	MT6359_ID_VFE28,
+	MT6359_ID_VCN13,
+	MT6359_ID_VCN33_1_BT,
+	MT6359_ID_VCN33_1_WIFI,
+	MT6359_ID_VAUX18,
+	MT6359_ID_VSRAM_OTHERS,
+	MT6359_ID_VEFUSE,
+	MT6359_ID_VXO22,
+	MT6359_ID_VRFCK,
+	MT6359_ID_VBIF28,
+	MT6359_ID_VIO28,
+	MT6359_ID_VEMC,
+	MT6359_ID_VCN33_2_BT,
+	MT6359_ID_VCN33_2_WIFI,
+	MT6359_ID_VA12,
+	MT6359_ID_VA09,
+	MT6359_ID_VRF18,
+	MT6359_ID_VSRAM_MD,
+	MT6359_ID_VUFS,
+	MT6359_ID_VM18,
+	MT6359_ID_VBBCK,
+	MT6359_ID_VSRAM_PROC1,
+	MT6359_ID_VSIM2,
+	MT6359_ID_VSRAM_OTHERS_SSHUB,
+	MT6359_ID_RG_MAX,
+};
+
+
+/* PMIC Registers */
+#define MT6359_BUCK_VPU_CON0			0x1488
+#define MT6359_BUCK_VPU_DBG1			0x14a8
+#define MT6359_BUCK_VPU_ELR0			0x14ac
+#define MT6359_BUCK_VCORE_CON0			0x1508
+#define MT6359_BUCK_VCORE_DBG1			0x1528
+#define MT6359_BUCK_VGPU11_CON0			0x1588
+#define MT6359_BUCK_VGPU11_DBG1			0x15a8
+#define MT6359_BUCK_VMODEM_CON0			0x1688
+#define MT6359_BUCK_VMODEM_DBG1			0x16a8
+#define MT6359_BUCK_VMODEM_ELR0			0x16ae
+#define MT6359_BUCK_VPROC1_CON0			0x1708
+#define MT6359_BUCK_VPROC1_DBG1			0x1728
+#define MT6359_BUCK_VPROC1_ELR0			0x172e
+#define MT6359_BUCK_VPROC2_CON0			0x1788
+#define MT6359_BUCK_VPROC2_DBG1			0x17a8
+#define MT6359_BUCK_VPROC2_ELR0			0x17b2
+#define MT6359_BUCK_VS1_CON0			0x1808
+#define MT6359_BUCK_VS1_DBG1			0x1828
+#define MT6359_BUCK_VS1_ELR0			0x1834
+#define MT6359_BUCK_VS2_CON0			0x1888
+#define MT6359_BUCK_VS2_DBG1			0x18a8
+#define MT6359_BUCK_VS2_ELR0			0x18b4
+#define MT6359_BUCK_VPA_CON0			0x1908
+#define MT6359_BUCK_VPA_CON1			0x190e
+#define MT6359_BUCK_VPA_DBG1			0x1916
+#define MT6359_VGPUVCORE_ANA_CON2		0x198e
+#define MT6359_VGPUVCORE_ANA_CON13		0x19a4
+#define MT6359_VPROC1_ANA_CON3			0x19b2
+#define MT6359_VPROC2_ANA_CON3			0x1a0e
+#define MT6359_VMODEM_ANA_CON3			0x1a1a
+#define MT6359_VPU_ANA_CON3			0x1a26
+#define MT6359_VS1_ANA_CON0			0x1a2c
+#define MT6359_VS2_ANA_CON0			0x1a34
+#define MT6359_VPA_ANA_CON0			0x1a3c
+
+#define MT6359_RG_BUCK_VPU_EN_ADDR			MT6359_BUCK_VPU_CON0
+#define MT6359_RG_BUCK_VPU_LP_ADDR			MT6359_BUCK_VPU_CON0
+#define MT6359_RG_BUCK_VPU_LP_SHIFT			1
+#define MT6359_DA_VPU_EN_ADDR				MT6359_BUCK_VPU_DBG1
+#define MT6359_RG_BUCK_VPU_VOSEL_ADDR			MT6359_BUCK_VPU_ELR0
+#define MT6359_RG_BUCK_VPU_VOSEL_MASK			0x7F
+#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT			0
+#define MT6359_RG_BUCK_VCORE_EN_ADDR			MT6359_BUCK_VCORE_CON0
+#define MT6359_RG_BUCK_VCORE_LP_ADDR			MT6359_BUCK_VCORE_CON0
+#define MT6359_RG_BUCK_VCORE_LP_SHIFT			1
+#define MT6359_DA_VCORE_EN_ADDR				MT6359_BUCK_VCORE_DBG1
+#define MT6359_RG_BUCK_VCORE_VOSEL_MASK			0x7F
+#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT		0
+#define MT6359_RG_BUCK_VGPU11_EN_ADDR			MT6359_BUCK_VGPU11_CON0
+#define MT6359_RG_BUCK_VGPU11_LP_ADDR			MT6359_BUCK_VGPU11_CON0
+#define MT6359_RG_BUCK_VGPU11_LP_SHIFT			1
+#define MT6359_DA_VGPU11_EN_ADDR			MT6359_BUCK_VGPU11_DBG1
+#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK		0x7F
+#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT		0
+#define MT6359_RG_BUCK_VMODEM_EN_ADDR			MT6359_BUCK_VMODEM_CON0
+#define MT6359_RG_BUCK_VMODEM_LP_ADDR			MT6359_BUCK_VMODEM_CON0
+#define MT6359_RG_BUCK_VMODEM_LP_SHIFT			1
+#define MT6359_DA_VMODEM_EN_ADDR			MT6359_BUCK_VMODEM_DBG1
+#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR		MT6359_BUCK_VMODEM_ELR0
+#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK		0x7F
+#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT		0
+#define MT6359_RG_BUCK_VPROC1_EN_ADDR			MT6359_BUCK_VPROC1_CON0
+#define MT6359_RG_BUCK_VPROC1_LP_ADDR			MT6359_BUCK_VPROC1_CON0
+#define MT6359_RG_BUCK_VPROC1_LP_SHIFT			1
+#define MT6359_DA_VPROC1_EN_ADDR			MT6359_BUCK_VPROC1_DBG1
+#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR		MT6359_BUCK_VPROC1_ELR0
+#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK		0x7F
+#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT		0
+#define MT6359_RG_BUCK_VPROC2_EN_ADDR			MT6359_BUCK_VPROC2_CON0
+#define MT6359_RG_BUCK_VPROC2_LP_ADDR			MT6359_BUCK_VPROC2_CON0
+#define MT6359_RG_BUCK_VPROC2_LP_SHIFT			1
+#define MT6359_DA_VPROC2_EN_ADDR			MT6359_BUCK_VPROC2_DBG1
+#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR		MT6359_BUCK_VPROC2_ELR0
+#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK		0x7F
+#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT		0
+#define MT6359_RG_BUCK_VS1_EN_ADDR			MT6359_BUCK_VS1_CON0
+#define MT6359_RG_BUCK_VS1_LP_ADDR			MT6359_BUCK_VS1_CON0
+#define MT6359_RG_BUCK_VS1_LP_SHIFT			1
+#define MT6359_DA_VS1_EN_ADDR				MT6359_BUCK_VS1_DBG1
+#define MT6359_RG_BUCK_VS1_VOSEL_ADDR			MT6359_BUCK_VS1_ELR0
+#define MT6359_RG_BUCK_VS1_VOSEL_MASK			0x7F
+#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT			0
+#define MT6359_RG_BUCK_VS2_EN_ADDR			MT6359_BUCK_VS2_CON0
+#define MT6359_RG_BUCK_VS2_LP_ADDR			MT6359_BUCK_VS2_CON0
+#define MT6359_RG_BUCK_VS2_LP_SHIFT			1
+#define MT6359_DA_VS2_EN_ADDR				MT6359_BUCK_VS2_DBG1
+#define MT6359_RG_BUCK_VS2_VOSEL_ADDR			MT6359_BUCK_VS2_ELR0
+#define MT6359_RG_BUCK_VS2_VOSEL_MASK			0x7F
+#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT			0
+#define MT6359_RG_BUCK_VPA_EN_ADDR			MT6359_BUCK_VPA_CON0
+#define MT6359_RG_BUCK_VPA_LP_ADDR			MT6359_BUCK_VPA_CON0
+#define MT6359_RG_BUCK_VPA_LP_SHIFT			1
+#define MT6359_RG_BUCK_VPA_VOSEL_ADDR			MT6359_BUCK_VPA_CON1
+#define MT6359_RG_BUCK_VPA_VOSEL_MASK			0x3F
+#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT			0
+#define MT6359_DA_VPA_EN_ADDR				MT6359_BUCK_VPA_DBG1
+#define MT6359_RG_VGPU11_FCCM_ADDR			MT6359_VGPUVCORE_ANA_CON2
+#define MT6359_RG_VGPU11_FCCM_SHIFT			9
+#define MT6359_RG_VCORE_FCCM_ADDR			MT6359_VGPUVCORE_ANA_CON13
+#define MT6359_RG_VCORE_FCCM_SHIFT			5
+#define MT6359_RG_VPROC1_FCCM_ADDR			MT6359_VPROC1_ANA_CON3
+#define MT6359_RG_VPROC1_FCCM_SHIFT			1
+#define MT6359_RG_VPROC2_FCCM_ADDR			MT6359_VPROC2_ANA_CON3
+#define MT6359_RG_VPROC2_FCCM_SHIFT			1
+#define MT6359_RG_VMODEM_FCCM_ADDR			MT6359_VMODEM_ANA_CON3
+#define MT6359_RG_VMODEM_FCCM_SHIFT			1
+#define MT6359_RG_VPU_FCCM_ADDR				MT6359_VPU_ANA_CON3
+#define MT6359_RG_VPU_FCCM_SHIFT			1
+#define MT6359_RG_VS1_FPWM_ADDR				MT6359_VS1_ANA_CON0
+#define MT6359_RG_VS1_FPWM_SHIFT			3
+#define MT6359_RG_VS2_FPWM_ADDR				MT6359_VS2_ANA_CON0
+#define MT6359_RG_VS2_FPWM_SHIFT			3
+#define MT6359_RG_VPA_MODESET_ADDR			MT6359_VPA_ANA_CON0
+#define MT6359_RG_VPA_MODESET_SHIFT			1
+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK		0x7F
+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT		0
+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK		0x7F
+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT		0
+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK		0x7F
+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT		0
+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK		0x7F
+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT		0
+#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT		0
+#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT		15
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK	0x7F
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT	1
+#define MT6359_RG_VCN33_1_VOSEL_MASK			0xF
+#define MT6359_RG_VCN33_1_VOSEL_SHIFT			8
+#define MT6359_RG_VCN33_2_VOSEL_MASK			0xF
+#define MT6359_RG_VCN33_2_VOSEL_SHIFT			8
+#define MT6359_RG_VSIM1_VOSEL_MASK			0xF
+#define MT6359_RG_VSIM1_VOSEL_SHIFT			8
+#define MT6359_RG_VSIM2_VOSEL_MASK			0xF
+#define MT6359_RG_VSIM2_VOSEL_SHIFT			8
+#define MT6359_RG_VIO28_VOSEL_MASK			0xF
+#define MT6359_RG_VIO28_VOSEL_SHIFT			8
+#define MT6359_RG_VIBR_VOSEL_MASK			0xF
+#define MT6359_RG_VIBR_VOSEL_SHIFT			8
+#define MT6359_RG_VRF18_VOSEL_MASK			0xF
+#define MT6359_RG_VRF18_VOSEL_SHIFT			8
+#define MT6359_RG_VEFUSE_VOSEL_MASK			0xF
+#define MT6359_RG_VEFUSE_VOSEL_SHIFT			8
+#define MT6359_RG_VCAMIO_VOSEL_MASK			0xF
+#define MT6359_RG_VCAMIO_VOSEL_SHIFT			8
+#define MT6359_RG_VIO18_VOSEL_MASK			0xF
+#define MT6359_RG_VIO18_VOSEL_SHIFT			8
+#define MT6359_RG_VM18_VOSEL_MASK			0xF
+#define MT6359_RG_VM18_VOSEL_SHIFT			8
+#define MT6359_RG_VUFS_VOSEL_MASK			0xF
+#define MT6359_RG_VUFS_VOSEL_SHIFT			8
+#define MT6359_RG_VRF12_VOSEL_MASK			0xF
+#define MT6359_RG_VRF12_VOSEL_SHIFT			8
+#define MT6359_RG_VCN13_VOSEL_MASK			0xF
+#define MT6359_RG_VCN13_VOSEL_SHIFT			8
+#define MT6359_RG_VA09_VOSEL_MASK			0xF
+#define MT6359_RG_VA09_VOSEL_SHIFT			8
+#define MT6359_RG_VA12_VOSEL_MASK			0xF
+#define MT6359_RG_VA12_VOSEL_SHIFT			8
+#define MT6359_RG_VXO22_VOSEL_MASK			0xF
+#define MT6359_RG_VXO22_VOSEL_SHIFT			8
+#define MT6359_RG_VRFCK_VOSEL_MASK			0xF
+#define MT6359_RG_VRFCK_VOSEL_SHIFT			8
+
+#endif
diff --git a/include/power/mt6359p.h b/include/power/mt6359p.h
new file mode 100644
index 00000000000..506b5d38c68
--- /dev/null
+++ b/include/power/mt6359p.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 MediaTek Inc. All Rights Reserved.
+ * Author: Bo-Chen Chen <[email protected]>
+ */
+
+#ifndef __MT6359P_H_
+#define __MT6359P_H_
+
+#define MT6359P_CHIP_VER 0x5930
+
+/* PMIC Registers */
+#define MT6359P_HWCID				0x8
+#define MT6359P_TOP_TRAP			0x50
+#define MT6359P_TOP_TMA_KEY			0x3a8
+#define MT6359P_BUCK_VCORE_ELR0			0x152c
+#define MT6359P_BUCK_VGPU11_SSHUB_CON0		0x15aa
+#define MT6359P_BUCK_VGPU11_ELR0		0x15b4
+#define MT6359P_LDO_VSRAM_PROC1_ELR		0x1b44
+#define MT6359P_LDO_VSRAM_PROC2_ELR		0x1b46
+#define MT6359P_LDO_VSRAM_OTHERS_ELR		0x1b48
+#define MT6359P_LDO_VSRAM_MD_ELR		0x1b4a
+#define MT6359P_LDO_VEMC_ELR_0			0x1b4c
+#define MT6359P_LDO_VFE28_CON0			0x1b88
+#define MT6359P_LDO_VFE28_MON			0x1b8c
+#define MT6359P_LDO_VXO22_CON0			0x1b9a
+#define MT6359P_LDO_VXO22_MON			0x1b9e
+#define MT6359P_LDO_VRF18_CON0			0x1bac
+#define MT6359P_LDO_VRF18_MON			0x1bb0
+#define MT6359P_LDO_VRF12_CON0			0x1bbe
+#define MT6359P_LDO_VRF12_MON			0x1bc2
+#define MT6359P_LDO_VEFUSE_CON0			0x1bd0
+#define MT6359P_LDO_VEFUSE_MON			0x1bd4
+#define MT6359P_LDO_VCN33_1_CON0		0x1be2
+#define MT6359P_LDO_VCN33_1_MON			0x1be6
+#define MT6359P_LDO_VCN33_1_MULTI_SW		0x1bf4
+#define MT6359P_LDO_VCN33_2_CON0		0x1c08
+#define MT6359P_LDO_VCN33_2_MON			0x1c0c
+#define MT6359P_LDO_VCN33_2_MULTI_SW		0x1c1a
+#define MT6359P_LDO_VCN13_CON0			0x1c1c
+#define MT6359P_LDO_VCN13_MON			0x1c20
+#define MT6359P_LDO_VCN18_CON0			0x1c2e
+#define MT6359P_LDO_VCN18_MON			0x1c32
+#define MT6359P_LDO_VA09_CON0			0x1c40
+#define MT6359P_LDO_VA09_MON			0x1c44
+#define MT6359P_LDO_VCAMIO_CON0			0x1c52
+#define MT6359P_LDO_VCAMIO_MON			0x1c56
+#define MT6359P_LDO_VA12_CON0			0x1c64
+#define MT6359P_LDO_VA12_MON			0x1c68
+#define MT6359P_LDO_VAUX18_CON0			0x1c88
+#define MT6359P_LDO_VAUX18_MON			0x1c8c
+#define MT6359P_LDO_VAUD18_CON0			0x1c9a
+#define MT6359P_LDO_VAUD18_MON			0x1c9e
+#define MT6359P_LDO_VIO18_CON0			0x1cac
+#define MT6359P_LDO_VIO18_MON			0x1cb0
+#define MT6359P_LDO_VEMC_CON0			0x1cbe
+#define MT6359P_LDO_VEMC_MON			0x1cc2
+#define MT6359P_LDO_VSIM1_CON0			0x1cd0
+#define MT6359P_LDO_VSIM1_MON			0x1cd4
+#define MT6359P_LDO_VSIM2_CON0			0x1ce2
+#define MT6359P_LDO_VSIM2_MON			0x1ce6
+#define MT6359P_LDO_VUSB_CON0			0x1d08
+#define MT6359P_LDO_VUSB_MON			0x1d0c
+#define MT6359P_LDO_VRFCK_CON0			0x1d1c
+#define MT6359P_LDO_VRFCK_MON			0x1d20
+#define MT6359P_LDO_VBBCK_CON0			0x1d2e
+#define MT6359P_LDO_VBBCK_MON			0x1d32
+#define MT6359P_LDO_VBIF28_CON0			0x1d40
+#define MT6359P_LDO_VBIF28_MON			0x1d44
+#define MT6359P_LDO_VIBR_CON0			0x1d52
+#define MT6359P_LDO_VIBR_MON			0x1d56
+#define MT6359P_LDO_VIO28_CON0			0x1d64
+#define MT6359P_LDO_VIO28_MON			0x1d68
+#define MT6359P_LDO_VM18_CON0			0x1d88
+#define MT6359P_LDO_VM18_MON			0x1d8c
+#define MT6359P_LDO_VUFS_CON0			0x1d9a
+#define MT6359P_LDO_VUFS_MON			0x1d9e
+#define MT6359P_LDO_VSRAM_PROC1_CON0		0x1e88
+#define MT6359P_LDO_VSRAM_PROC1_MON		0x1e8c
+#define MT6359P_LDO_VSRAM_PROC2_CON0		0x1ea8
+#define MT6359P_LDO_VSRAM_PROC2_MON		0x1eac
+#define MT6359P_LDO_VSRAM_OTHERS_CON0		0x1f08
+#define MT6359P_LDO_VSRAM_OTHERS_MON		0x1f0c
+#define MT6359P_LDO_VSRAM_OTHERS_SSHUB		0x1f28
+#define MT6359P_LDO_VSRAM_MD_CON0		0x1f2e
+#define MT6359P_LDO_VSRAM_MD_MON		0x1f32
+#define MT6359P_VCN33_1_ANA_CON0		0x1f98
+#define MT6359P_VCN33_2_ANA_CON0		0x1f9c
+#define MT6359P_VSIM1_ANA_CON0			0x1fa2
+#define MT6359P_VSIM2_ANA_CON0			0x1fa6
+#define MT6359P_VIO28_ANA_CON0			0x1faa
+#define MT6359P_VIBR_ANA_CON0			0x1fae
+#define MT6359P_VFE28_ELR_4			0x1fc0
+#define MT6359P_VRF18_ANA_CON0			0x2008
+#define MT6359P_VEFUSE_ANA_CON0			0x200c
+#define MT6359P_VCAMIO_ANA_CON0			0x2014
+#define MT6359P_VIO18_ANA_CON0			0x201c
+#define MT6359P_VM18_ANA_CON0			0x2020
+#define MT6359P_VUFS_ANA_CON0			0x2024
+#define MT6359P_VRF12_ANA_CON0			0x202a
+#define MT6359P_VCN13_ANA_CON0			0x202e
+#define MT6359P_VRF18_ELR_3			0x204e
+#define MT6359P_VXO22_ANA_CON0			0x2088
+#define MT6359P_VRFCK_ANA_CON0			0x208c
+#define MT6359P_VBBCK_ANA_CON0			0x2096
+
+#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR		MT6359P_BUCK_VCORE_ELR0
+#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR		MT6359P_BUCK_VGPU11_SSHUB_CON0
+#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR		MT6359P_BUCK_VGPU11_ELR0
+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR		MT6359P_BUCK_VGPU11_SSHUB_CON0
+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK		0x7F
+#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT	4
+#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR		MT6359P_LDO_VSRAM_PROC1_ELR
+#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR		MT6359P_LDO_VSRAM_PROC2_ELR
+#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR		MT6359P_LDO_VSRAM_OTHERS_ELR
+#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR		MT6359P_LDO_VSRAM_MD_ELR
+#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR		MT6359P_LDO_VEMC_ELR_0
+#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK		0xF
+#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT		0
+#define MT6359P_RG_LDO_VFE28_EN_ADDR			MT6359P_LDO_VFE28_CON0
+#define MT6359P_DA_VFE28_B_EN_ADDR			MT6359P_LDO_VFE28_MON
+#define MT6359P_RG_LDO_VXO22_EN_ADDR			MT6359P_LDO_VXO22_CON0
+#define MT6359P_RG_LDO_VXO22_EN_SHIFT			0
+#define MT6359P_DA_VXO22_B_EN_ADDR			MT6359P_LDO_VXO22_MON
+#define MT6359P_RG_LDO_VRF18_EN_ADDR			MT6359P_LDO_VRF18_CON0
+#define MT6359P_RG_LDO_VRF18_EN_SHIFT			0
+#define MT6359P_DA_VRF18_B_EN_ADDR			MT6359P_LDO_VRF18_MON
+#define MT6359P_RG_LDO_VRF12_EN_ADDR			MT6359P_LDO_VRF12_CON0
+#define MT6359P_RG_LDO_VRF12_EN_SHIFT			0
+#define MT6359P_DA_VRF12_B_EN_ADDR			MT6359P_LDO_VRF12_MON
+#define MT6359P_RG_LDO_VEFUSE_EN_ADDR			MT6359P_LDO_VEFUSE_CON0
+#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT			0
+#define MT6359P_DA_VEFUSE_B_EN_ADDR			MT6359P_LDO_VEFUSE_MON
+#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR		MT6359P_LDO_VCN33_1_CON0
+#define MT6359P_DA_VCN33_1_B_EN_ADDR			MT6359P_LDO_VCN33_1_MON
+#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR		MT6359P_LDO_VCN33_1_MULTI_SW
+#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT		15
+#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR		MT6359P_LDO_VCN33_2_CON0
+#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT		0
+#define MT6359P_DA_VCN33_2_B_EN_ADDR			MT6359P_LDO_VCN33_2_MON
+#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR		MT6359P_LDO_VCN33_2_MULTI_SW
+#define MT6359P_RG_LDO_VCN13_EN_ADDR			MT6359P_LDO_VCN13_CON0
+#define MT6359P_RG_LDO_VCN13_EN_SHIFT			0
+#define MT6359P_DA_VCN13_B_EN_ADDR			MT6359P_LDO_VCN13_MON
+#define MT6359P_RG_LDO_VCN18_EN_ADDR			MT6359P_LDO_VCN18_CON0
+#define MT6359P_DA_VCN18_B_EN_ADDR			MT6359P_LDO_VCN18_MON
+#define MT6359P_RG_LDO_VA09_EN_ADDR			MT6359P_LDO_VA09_CON0
+#define MT6359P_RG_LDO_VA09_EN_SHIFT			0
+#define MT6359P_DA_VA09_B_EN_ADDR			MT6359P_LDO_VA09_MON
+#define MT6359P_RG_LDO_VCAMIO_EN_ADDR			MT6359P_LDO_VCAMIO_CON0
+#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT			0
+#define MT6359P_DA_VCAMIO_B_EN_ADDR			MT6359P_LDO_VCAMIO_MON
+#define MT6359P_RG_LDO_VA12_EN_ADDR			MT6359P_LDO_VA12_CON0
+#define MT6359P_RG_LDO_VA12_EN_SHIFT			0
+#define MT6359P_DA_VA12_B_EN_ADDR			MT6359P_LDO_VA12_MON
+#define MT6359P_RG_LDO_VAUX18_EN_ADDR			MT6359P_LDO_VAUX18_CON0
+#define MT6359P_DA_VAUX18_B_EN_ADDR			MT6359P_LDO_VAUX18_MON
+#define MT6359P_RG_LDO_VAUD18_EN_ADDR			MT6359P_LDO_VAUD18_CON0
+#define MT6359P_DA_VAUD18_B_EN_ADDR			MT6359P_LDO_VAUD18_MON
+#define MT6359P_RG_LDO_VIO18_EN_ADDR			MT6359P_LDO_VIO18_CON0
+#define MT6359P_RG_LDO_VIO18_EN_SHIFT			0
+#define MT6359P_DA_VIO18_B_EN_ADDR			MT6359P_LDO_VIO18_MON
+#define MT6359P_RG_LDO_VEMC_EN_ADDR			MT6359P_LDO_VEMC_CON0
+#define MT6359P_RG_LDO_VEMC_EN_SHIFT			0
+#define MT6359P_DA_VEMC_B_EN_ADDR			MT6359P_LDO_VEMC_MON
+#define MT6359P_RG_LDO_VSIM1_EN_ADDR			MT6359P_LDO_VSIM1_CON0
+#define MT6359P_RG_LDO_VSIM1_EN_SHIFT			0
+#define MT6359P_DA_VSIM1_B_EN_ADDR			MT6359P_LDO_VSIM1_MON
+#define MT6359P_RG_LDO_VSIM2_EN_ADDR			MT6359P_LDO_VSIM2_CON0
+#define MT6359P_RG_LDO_VSIM2_EN_SHIFT			0
+#define MT6359P_DA_VSIM2_B_EN_ADDR			MT6359P_LDO_VSIM2_MON
+#define MT6359P_RG_LDO_VUSB_EN_0_ADDR			MT6359P_LDO_VUSB_CON0
+#define MT6359P_DA_VUSB_B_EN_ADDR			MT6359P_LDO_VUSB_MON
+#define MT6359P_RG_LDO_VRFCK_EN_ADDR			MT6359P_LDO_VRFCK_CON0
+#define MT6359P_RG_LDO_VRFCK_EN_SHIFT			0
+#define MT6359P_DA_VRFCK_B_EN_ADDR			MT6359P_LDO_VRFCK_MON
+#define MT6359P_RG_LDO_VBBCK_EN_ADDR			MT6359P_LDO_VBBCK_CON0
+#define MT6359P_RG_LDO_VBBCK_EN_SHIFT			0
+#define MT6359P_DA_VBBCK_B_EN_ADDR			MT6359P_LDO_VBBCK_MON
+#define MT6359P_RG_LDO_VBIF28_EN_ADDR			MT6359P_LDO_VBIF28_CON0
+#define MT6359P_DA_VBIF28_B_EN_ADDR			MT6359P_LDO_VBIF28_MON
+#define MT6359P_RG_LDO_VIBR_EN_ADDR			MT6359P_LDO_VIBR_CON0
+#define MT6359P_RG_LDO_VIBR_EN_SHIFT			0
+#define MT6359P_DA_VIBR_B_EN_ADDR			MT6359P_LDO_VIBR_MON
+#define MT6359P_RG_LDO_VIO28_EN_ADDR			MT6359P_LDO_VIO28_CON0
+#define MT6359P_RG_LDO_VIO28_EN_SHIFT			0
+#define MT6359P_DA_VIO28_B_EN_ADDR			MT6359P_LDO_VIO28_MON
+#define MT6359P_RG_LDO_VM18_EN_ADDR			MT6359P_LDO_VM18_CON0
+#define MT6359P_RG_LDO_VM18_EN_SHIFT			0
+#define MT6359P_DA_VM18_B_EN_ADDR			MT6359P_LDO_VM18_MON
+#define MT6359P_RG_LDO_VUFS_EN_ADDR			MT6359P_LDO_VUFS_CON0
+#define MT6359P_RG_LDO_VUFS_EN_SHIFT			0
+#define MT6359P_DA_VUFS_B_EN_ADDR			MT6359P_LDO_VUFS_MON
+#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR		MT6359P_LDO_VSRAM_PROC1_CON0
+#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR		MT6359P_LDO_VSRAM_PROC1_MON
+#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR		MT6359P_LDO_VSRAM_PROC2_CON0
+#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR		MT6359P_LDO_VSRAM_PROC2_MON
+#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR		MT6359P_LDO_VSRAM_OTHERS_CON0
+#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR		MT6359P_LDO_VSRAM_OTHERS_MON
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR	MT6359P_LDO_VSRAM_OTHERS_SSHUB
+#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR	MT6359P_LDO_VSRAM_OTHERS_SSHUB
+#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR			MT6359P_LDO_VSRAM_MD_CON0
+#define MT6359P_DA_VSRAM_MD_B_EN_ADDR			MT6359P_LDO_VSRAM_MD_MON
+#define MT6359P_RG_VCN33_1_VOSEL_ADDR			MT6359P_VCN33_1_ANA_CON0
+#define MT6359P_RG_VCN33_2_VOSEL_ADDR			MT6359P_VCN33_2_ANA_CON0
+#define MT6359P_RG_VSIM1_VOSEL_ADDR			MT6359P_VSIM1_ANA_CON0
+#define MT6359P_RG_VSIM2_VOSEL_ADDR			MT6359P_VSIM2_ANA_CON0
+#define MT6359P_RG_VIO28_VOSEL_ADDR			MT6359P_VIO28_ANA_CON0
+#define MT6359P_RG_VIBR_VOSEL_ADDR			MT6359P_VIBR_ANA_CON0
+#define MT6359P_RG_VRF18_VOSEL_ADDR			MT6359P_VRF18_ANA_CON0
+#define MT6359P_RG_VEFUSE_VOSEL_ADDR			MT6359P_VEFUSE_ANA_CON0
+#define MT6359P_RG_VCAMIO_VOSEL_ADDR			MT6359P_VCAMIO_ANA_CON0
+#define MT6359P_RG_VIO18_VOSEL_ADDR			MT6359P_VIO18_ANA_CON0
+#define MT6359P_RG_VM18_VOSEL_ADDR			MT6359P_VM18_ANA_CON0
+#define MT6359P_RG_VUFS_VOSEL_ADDR			MT6359P_VUFS_ANA_CON0
+#define MT6359P_RG_VRF12_VOSEL_ADDR			MT6359P_VRF12_ANA_CON0
+#define MT6359P_RG_VCN13_VOSEL_ADDR			MT6359P_VCN13_ANA_CON0
+#define MT6359P_RG_VA09_VOSEL_ADDR			MT6359P_VRF18_ELR_3
+#define MT6359P_RG_VA12_VOSEL_ADDR			MT6359P_VFE28_ELR_4
+#define MT6359P_RG_VXO22_VOSEL_ADDR			MT6359P_VXO22_ANA_CON0
+#define MT6359P_RG_VRFCK_VOSEL_ADDR			MT6359P_VRFCK_ANA_CON0
+#define MT6359P_RG_VBBCK_VOSEL_ADDR			MT6359P_VBBCK_ANA_CON0
+#define MT6359P_RG_VBBCK_VOSEL_MASK			0xF
+#define MT6359P_RG_VBBCK_VOSEL_SHIFT			4
+#define MT6359P_VM_MODE_ADDR				MT6359P_TOP_TRAP
+#define MT6359P_TMA_KEY_ADDR				MT6359P_TOP_TMA_KEY
+
+#define MT6359P_TMA_KEY 0x9CA6
+
+#endif