Merge branch '2020-10-08-misc-board-improvements'

- Move ASPEED ram driver, update.
- Exhance pinctrl/gpio support, update Kendryte K210 support
- Enhance qemu_arm64 support for a single binary to work with and
  without TF-A

4 files changed, 636 insertions, 164 deletions

diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h
index bc8b7c5c123..273fa1a7d7b 100644
--- a/include/configs/qemu-arm.h
+++ b/include/configs/qemu-arm.h
@@ -45,13 +45,7 @@
 #define CONFIG_SYS_CBSIZE 512
 
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#ifdef CONFIG_TFABOOT
-#define CONFIG_SYS_FLASH_BASE		0x4000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#else
-#define CONFIG_SYS_FLASH_BASE		0x0
-#define CONFIG_SYS_MAX_FLASH_BANKS	2
-#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* Sector: 256K, Bank: 64M */
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 692e5fc8cbf..1bdc8d3cbd7 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2015  Masahiro Yamada <[email protected]>
+ * Copyright (C) 2015  Masahiro Yamada <yamada.masahiro@com>
  */
 
 #ifndef __PINCTRL_H
@@ -11,11 +11,10 @@
 
 /**
  * struct pinconf_param - pin config parameters
- *
- * @property: property name in DT nodes
- * @param: ID for this config parameter
- * @default_value: default value for this config parameter used in case
- *	no value is specified in DT nodes
+ * @property:		Property name in DT nodes
+ * @param:		ID for this config parameter
+ * @default_value:	default value for this config parameter used in case
+ *			no value is specified in DT nodes
  */
 struct pinconf_param {
 	const char * const property;
@@ -27,106 +26,274 @@ struct pinconf_param {
  * struct pinctrl_ops - pin control operations, to be implemented by
  * pin controller drivers.
  *
- * The @set_state is the only mandatory operation.  You can implement your
- * pinctrl driver with its own @set_state.  In this case, the other callbacks
- * are not required.  Otherwise, generic pinctrl framework is also available;
- * use pinctrl_generic_set_state for @set_state, and implement other operations
+ * set_state() is the only mandatory operation. You can implement your pinctrl
+ * driver with its own @set_state. In this case, the other callbacks are not
+ * required. Otherwise, generic pinctrl framework is also available; use
+ * pinctrl_generic_set_state for @set_state, and implement other operations
  * depending on your necessity.
- *
- * @get_pins_count: return number of selectable named pins available
- *	in this driver.  (necessary to parse "pins" property in DTS)
- * @get_pin_name: return the pin name of the pin selector,
- *	called by the core to figure out which pin it shall do
- *	operations to.  (necessary to parse "pins" property in DTS)
- * @get_groups_count: return number of selectable named groups available
- *	in this driver.  (necessary to parse "groups" property in DTS)
- * @get_group_name: return the group name of the group selector,
- *	called by the core to figure out which pin group it shall do
- *	operations to.  (necessary to parse "groups" property in DTS)
- * @get_functions_count: return number of selectable named functions available
- *	in this driver.  (necessary for pin-muxing)
- * @get_function_name: return the function name of the muxing selector,
- *	called by the core to figure out which mux setting it shall map a
- *	certain device to.  (necessary for pin-muxing)
- * @pinmux_set: enable a certain muxing function with a certain pin.
- *	The @func_selector selects a certain function whereas @pin_selector
- *	selects a certain pin to be used. On simple controllers one of them
- *	may be ignored.  (necessary for pin-muxing against a single pin)
- * @pinmux_group_set: enable a certain muxing function with a certain pin
- *	group.  The @func_selector selects a certain function whereas
- *	@group_selector selects a certain set of pins to be used. On simple
- *	controllers one of them may be ignored.
- *	(necessary for pin-muxing against a pin group)
- * @pinconf_num_params: number of driver-specific parameters to be parsed
- *	from device trees  (necessary for pin-configuration)
- * @pinconf_params: list of driver_specific parameters to be parsed from
- *	device trees  (necessary for pin-configuration)
- * @pinconf_set: configure an individual pin with a given parameter.
- *	(necessary for pin-configuration against a single pin)
- * @pinconf_group_set: configure all pins in a group with a given parameter.
- *	(necessary for pin-configuration against a pin group)
- * @set_state: do pinctrl operations specified by @config, a pseudo device
- *	pointing a config node. (necessary for pinctrl_full)
- * @set_state_simple: do needed pinctrl operations for a peripherl @periph.
- *	(necessary for pinctrl_simple)
- * @get_pin_muxing: display the muxing of a given pin.
- * @gpio_request_enable: requests and enables GPIO on a certain pin.
- *	Implement this only if you can mux every pin individually as GPIO. The
- *	affected GPIO range is passed along with an offset(pin number) into that
- *	specific GPIO range - function selectors and pin groups are orthogonal
- *	to this, the core will however make sure the pins do not collide.
- * @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
- *	@gpio_request_enable
  */
 struct pinctrl_ops {
+	/**
+	 * @get_pins_count: Get the number of selectable pins
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * This function is necessary to parse the "pins" property in DTS.
+	 *
+	 * @Return:
+	 *	number of selectable named pins available in this driver
+	 */
 	int (*get_pins_count)(struct udevice *dev);
+
+	/**
+	 * @get_pin_name: Get the name of a pin
+	 *
+	 * @dev: Pinctrl device of the pin
+	 *
+	 * @selector: The pin selector
+	 *
+	 * This function is called by the core to figure out which pin it will
+	 * do operations to. This function is necessary to parse the "pins"
+	 * property in DTS.
+	 *
+	 * @Return: const pointer to the name of the pin
+	 */
 	const char *(*get_pin_name)(struct udevice *dev, unsigned selector);
+
+	/**
+	 * @get_groups_count: Get the number of selectable groups
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * This function is necessary to parse the "groups" property in DTS.
+	 *
+	 * @Return:
+	 *	number of selectable named groups available in the driver
+	 */
 	int (*get_groups_count)(struct udevice *dev);
+
+	/**
+	 * @get_group_name: Get the name of a group
+	 *
+	 * @dev: Pinctrl device of the group
+	 *
+	 * @selector: The group selector
+	 *
+	 * This function is called by the core to figure out which group it
+	 * will do operations to. This function is necessary to parse the
+	 * "groups" property in DTS.
+	 *
+	 * @Return: Pointer to the name of the group
+	 */
 	const char *(*get_group_name)(struct udevice *dev, unsigned selector);
+
+	/**
+	 * @get_functions_count: Get the number of selectable functions
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * This function is necessary for pin-muxing.
+	 *
+	 * @Return:
+	 *	number of selectable named functions available in this driver
+	 */
 	int (*get_functions_count)(struct udevice *dev);
+
+	/**
+	 * @get_function_name: Get the name of a function
+	 *
+	 * @dev: Pinmux device of the function
+	 *
+	 * @selector: The function selector
+	 *
+	 * This function is called by the core to figure out which mux setting
+	 * it will map a certain device to. This function is necessary for
+	 * pin-muxing.
+	 *
+	 * @Return:
+	 *	Pointer to the function name of the muxing selector
+	 */
 	const char *(*get_function_name)(struct udevice *dev,
 					 unsigned selector);
+
+	/**
+	 * @pinmux_set: Mux a pin to a function
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @pin_selector: The pin selector
+	 *
+	 * @func_selector: The func selector
+	 *
+	 * On simple controllers one of @pin_selector or @func_selector may be
+	 * ignored. This function is necessary for pin-muxing against a single
+	 * pin.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*pinmux_set)(struct udevice *dev, unsigned pin_selector,
 			  unsigned func_selector);
+
+	/**
+	 * @pinmux_group_set: Mux a group of pins to a function
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @group_selector: The group selector
+	 *
+	 * @func_selector: The func selector
+	 *
+	 * On simple controllers one of @group_selector or @func_selector may be
+	 * ignored. This function is necessary for pin-muxing against a group of
+	 * pins.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*pinmux_group_set)(struct udevice *dev, unsigned group_selector,
 				unsigned func_selector);
+
+	/**
+	 * @pinmux_property_set: Enable a pinmux group
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @pinmux_group: A u32 representing the pin identifier and mux
+	 *                settings. The exact format of a pinmux group is left
+	 *                up to the driver.
+	 *
+	 * Mux a single pin to a single function based on a driver-specific
+	 * pinmux group. This function is necessary for parsing the "pinmux"
+	 * property in DTS, and for pin-muxing against a pinmux group.
+	 *
+	 * @Return:
+	 *	Pin selector for the muxed pin if OK, or negative error code on
+	 *	failure
+	 */
+	int (*pinmux_property_set)(struct udevice *dev, u32 pinmux_group);
+
+	/**
+	 * @pinconf_num_params:
+	 *	Number of driver-specific parameters to be parsed from device
+	 *	trees. This member is necessary for pin configuration.
+	 */
 	unsigned int pinconf_num_params;
+
+	/**
+	 * @pinconf_params:
+	 *	List of driver-specific parameters to be parsed from the device
+	 *	tree. This member is necessary for pin configuration.
+	 */
 	const struct pinconf_param *pinconf_params;
+
+	/**
+	 * @pinconf_set: Configure an individual pin with a parameter
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @pin_selector: The pin selector
+	 *
+	 * @param: An &enum pin_config_param from @pinconf_params
+	 *
+	 * @argument: The argument to this param from the device tree, or
+	 *            @pinconf_params.default_value
+	 *
+	 * This function is necessary for pin configuration against a single
+	 * pin.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*pinconf_set)(struct udevice *dev, unsigned pin_selector,
 			   unsigned param, unsigned argument);
+
+	/**
+	 * @pinconf_group_set: Configure all pins in a group with a parameter
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @pin_selector: The group selector
+	 *
+	 * @param: A &enum pin_config_param from
+	 *         @pinconf_params
+	 *
+	 * @argument: The argument to this param from the device tree, or
+	 *            @pinconf_params.default_value
+	 *
+	 * This function is necessary for pin configuration against a group of
+	 * pins.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*pinconf_group_set)(struct udevice *dev, unsigned group_selector,
 				 unsigned param, unsigned argument);
+
+	/**
+	 * @set_state: Configure a pinctrl device
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @config: Pseudo device pointing a config node
+	 *
+	 * This function is required to be implemented by all pinctrl drivers.
+	 * Drivers may set this member to pinctrl_generic_set_state(), which
+	 * will call other functions in &struct pinctrl_ops to parse
+	 * @config.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*set_state)(struct udevice *dev, struct udevice *config);
 
-	/* for pinctrl-simple */
+	/**
+	 * @set_state_simple: Configure a pinctrl device
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @config: Pseudo-device pointing a config node
+	 *
+	 * This function is usually a simpler version of set_state(). Only the
+	 * first pinctrl device on the system is supported by this function.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
+	 */
 	int (*set_state_simple)(struct udevice *dev, struct udevice *periph);
+
 	/**
-	 * request() - Request a particular pinctrl function
+	 * @request: Request a particular pinctrl function
+	 *
+	 * @dev: Device to adjust (%UCLASS_PINCTRL)
+	 *
+	 * @func: Function number (driver-specific)
 	 *
 	 * This activates the selected function.
 	 *
-	 * @dev:	Device to adjust (UCLASS_PINCTRL)
-	 * @func:	Function number (driver-specific)
-	 * @return 0 if OK, -ve on error
+	 * @Return: 0 if OK, or negative error code on failure
 	 */
 	int (*request)(struct udevice *dev, int func, int flags);
 
 	/**
-	* get_periph_id() - get the peripheral ID for a device
+	* @get_periph_id: Get the peripheral ID for a device
+	*
+	* @dev: Pinctrl device to use for decoding
+	*
+	* @periph: Device to check
 	*
 	* This generally looks at the peripheral's device tree node to work
 	* out the peripheral ID. The return value is normally interpreted as
-	* enum periph_id. so long as this is defined by the platform (which it
+	* &enum periph_id. so long as this is defined by the platform (which it
 	* should be).
 	*
-	* @dev:		Pinctrl device to use for decoding
-	* @periph:	Device to check
-	* @return peripheral ID of @periph, or -ENOENT on error
+	* @Return:
+	*	Peripheral ID of @periph, or %-ENOENT on error
 	*/
 	int (*get_periph_id)(struct udevice *dev, struct udevice *periph);
 
 	/**
-	 * get_gpio_mux() - get the mux value for a particular GPIO
+	 * @get_gpio_mux: Get the mux value for a particular GPIO
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @banknum: GPIO bank number
+	 *
+	 * @index: GPIO index within the bank
 	 *
 	 * This allows the raw mux value for a GPIO to be obtained. It is
 	 * useful for displaying the function being used by that GPIO, such
@@ -134,46 +301,60 @@ struct pinctrl_ops {
 	 * subsystem and should not be used by generic code. Typically it is
 	 * used by a GPIO driver with knowledge of the SoC pinctrl setup.
 	 *
-	* @dev:		Pinctrl device to use
-	* @banknum:	GPIO bank number
-	* @index:	GPIO index within the bank
-	* @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+	 * @Return:
+	 *	Mux value (SoC-specific, e.g. 0 for input, 1 for output)
 	 */
 	int (*get_gpio_mux)(struct udevice *dev, int banknum, int index);
 
 	/**
-	 * get_pin_muxing() - show pin muxing
+	 * @get_pin_muxing: Show pin muxing
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @selector: Pin selector
+	 *
+	 * @buf: Buffer to fill with pin muxing description
+	 *
+	 * @size: Size of @buf
 	 *
 	 * This allows to display the muxing of a given pin. It's useful for
-	 * debug purpose to know if a pin is configured as GPIO or as an
-	 * alternate function and which one.
-	 * Typically it is used by a PINCTRL driver with knowledge of the SoC
-	 * pinctrl setup.
+	 * debug purposes to know if a pin is configured as GPIO or as an
+	 * alternate function and which one. Typically it is used by a PINCTRL
+	 * driver with knowledge of the SoC pinctrl setup.
 	 *
-	 * @dev:	Pinctrl device to use
-	 * @selector:	Pin selector
-	 * @buf		Pin's muxing description
-	 * @size	Pin's muxing description length
-	 * return 0 if OK, -ve on error
+	 * @Return: 0 if OK, or negative error code on failure
 	 */
 	 int (*get_pin_muxing)(struct udevice *dev, unsigned int selector,
 			       char *buf, int size);
 
 	/**
-	 * gpio_request_enable: requests and enables GPIO on a certain pin.
+	 * @gpio_request_enable: Request and enable GPIO on a certain pin.
+	 *
+	 * @dev: Pinctrl device to use
+	 *
+	 * @selector: Pin selector
+	 *
+	 * Implement this only if you can mux every pin individually as GPIO.
+	 * The affected GPIO range is passed along with an offset(pin number)
+	 * into that specific GPIO range - function selectors and pin groups are
+	 * orthogonal to this, the core will however make sure the pins do not
+	 * collide.
 	 *
-	 * @dev:	Pinctrl device to use
-	 * @selector:	Pin selector
-	 * return 0 if OK, -ve on error
+	 * @Return:
+	 *	0 if OK, or negative error code on failure
 	 */
 	int (*gpio_request_enable)(struct udevice *dev, unsigned int selector);
 
 	/**
-	 * gpio_disable_free: free up GPIO muxing on a certain pin.
+	 * @gpio_disable_free: Free up GPIO muxing on a certain pin.
 	 *
-	 * @dev:	Pinctrl device to use
-	 * @selector:	Pin selector
-	 * return 0 if OK, -ve on error
+	 * @dev: Pinctrl device to use
+	 *
+	 * @selector: Pin selector
+	 *
+	 * This function is the reverse of @gpio_request_enable.
+	 *
+	 * @Return: 0 if OK, or negative error code on failure
 	 */
 	int (*gpio_disable_free)(struct udevice *dev, unsigned int selector);
 };
@@ -181,27 +362,26 @@ struct pinctrl_ops {
 #define pinctrl_get_ops(dev)	((struct pinctrl_ops *)(dev)->driver->ops)
 
 /**
- * Generic pin configuration paramters
+ * enum pin_config_param - Generic pin configuration parameters
  *
- * enum pin_config_param - possible pin configuration parameters
- * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
+ * @PIN_CONFIG_BIAS_BUS_HOLD: The pin will be set to weakly latch so that it
  *	weakly drives the last value on a tristate bus, also known as a "bus
  *	holder", "bus keeper" or "repeater". This allows another device on the
  *	bus to change the value by driving the bus high or low and switching to
  *	tristate. The argument is ignored.
- * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
+ * @PIN_CONFIG_BIAS_DISABLE: Disable any pin bias on the pin, a
  *	transition from say pull-up to pull-down implies that you disable
  *	pull-up in the process, this setting disables all biasing.
- * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: the pin will be set to a high impedance
+ * @PIN_CONFIG_BIAS_HIGH_IMPEDANCE: The pin will be set to a high impedance
  *	mode, also know as "third-state" (tristate) or "high-Z" or "floating".
  *	On output pins this effectively disconnects the pin, which is useful
  *	if for example some other pin is going to drive the signal connected
  *	to it for a while. Pins used for input are usually always high
  *	impedance.
- * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
+ * @PIN_CONFIG_BIAS_PULL_DOWN: The pin will be pulled down (usually with high
  *	impedance to GROUND). If the argument is != 0 pull-down is enabled,
  *	if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
- * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: the pin will be pulled up or down based
+ * @PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: The pin will be pulled up or down based
  *	on embedded knowledge of the controller hardware, like current mux
  *	function. The pull direction and possibly strength too will normally
  *	be decided completely inside the hardware block and not be readable
@@ -209,67 +389,67 @@ struct pinctrl_ops {
  *	If the argument is != 0 pull up/down is enabled, if it is 0, the
  *	configuration is ignored. The proper way to disable it is to use
  *	@PIN_CONFIG_BIAS_DISABLE.
- * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
+ * @PIN_CONFIG_BIAS_PULL_UP: The pin will be pulled up (usually with high
  *	impedance to VDD). If the argument is != 0 pull-up is enabled,
  *	if it is 0, pull-up is total, i.e. the pin is connected to VDD.
- * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
+ * @PIN_CONFIG_DRIVE_OPEN_DRAIN: The pin will be driven with open drain (open
  *	collector) which means it is usually wired with other output ports
  *	which are then pulled up with an external resistor. Setting this
  *	config will enable open drain mode, the argument is ignored.
- * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
+ * @PIN_CONFIG_DRIVE_OPEN_SOURCE: The pin will be driven with open source
  *	(open emitter). Setting this config will enable open source mode, the
  *	argument is ignored.
- * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
+ * @PIN_CONFIG_DRIVE_PUSH_PULL: The pin will be driven actively high and
  *	low, this is the most typical case and is typically achieved with two
  *	active transistors on the output. Setting this config will enable
  *	push-pull mode, the argument is ignored.
- * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
+ * @PIN_CONFIG_DRIVE_STRENGTH: The pin will sink or source at most the current
  *	passed as argument. The argument is in mA.
- * @PIN_CONFIG_DRIVE_STRENGTH_UA: the pin will sink or source at most the current
- *	passed as argument. The argument is in uA.
- * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
+ * @PIN_CONFIG_DRIVE_STRENGTH_UA: The pin will sink or source at most the
+ *	current passed as argument. The argument is in uA.
+ * @PIN_CONFIG_INPUT_DEBOUNCE: This will configure the pin to debounce mode,
  *	which means it will wait for signals to settle when reading inputs. The
  *	argument gives the debounce time in usecs. Setting the
  *	argument to zero turns debouncing off.
- * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input.  Note that this does not
+ * @PIN_CONFIG_INPUT_ENABLE: Enable the pin's input.  Note that this does not
  *	affect the pin's ability to drive output.  1 enables input, 0 disables
  *	input.
- * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
+ * @PIN_CONFIG_INPUT_SCHMITT: This will configure an input pin to run in
  *	schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
  *	the threshold value is given on a custom format as argument when
  *	setting pins to this mode.
- * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
+ * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: Control schmitt-trigger mode on the pin.
  *      If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
  *      schmitt-trigger mode is disabled.
- * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
+ * @PIN_CONFIG_LOW_POWER_MODE: This will configure the pin for low power
  *	operation, if several modes of operation are supported these can be
  *	passed in the argument on a custom form, else just use argument 1
  *	to indicate low power mode, argument 0 turns low power mode off.
- * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode
+ * @PIN_CONFIG_OUTPUT_ENABLE: This will enable the pin's output mode
  *	without driving a value there. For most platforms this reduces to
  *	enable the output buffers and then let the pin controller current
  *	configuration (eg. the currently selected mux function) drive values on
  *	the line. Use argument 1 to enable output mode, argument 0 to disable
  *	it.
- * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a
+ * @PIN_CONFIG_OUTPUT: This will configure the pin as an output and drive a
  *	value on the line. Use argument 1 to indicate high level, argument 0 to
  *	indicate low level. (Please see Documentation/driver-api/pinctl.rst,
  *	section "GPIO mode pitfalls" for a discussion around this parameter.)
- * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
+ * @PIN_CONFIG_POWER_SOURCE: If the pin can select between different power
  *	supplies, the argument to this parameter (on a custom format) tells
  *	the driver which alternative power source to use.
- * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state.
- * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
+ * @PIN_CONFIG_SLEEP_HARDWARE_STATE: Indicate this is sleep related state.
+ * @PIN_CONFIG_SLEW_RATE: If the pin can select slew rate, the argument to
  *	this parameter (on a custom format) tells the driver which alternative
  *	slew rate to use.
- * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
+ * @PIN_CONFIG_SKEW_DELAY: If the pin has programmable skew rate (on inputs)
  *	or latch delay (on outputs) this parameter (in a custom format)
  *	specifies the clock skew or latch delay. It typically controls how
  *	many double inverters are put in front of the line.
- * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
+ * @PIN_CONFIG_END: This is the last enumerator for pin configurations, if
  *	you need to pass in custom configurations to the pin controller, use
  *	PIN_CONFIG_END+1 as the base offset.
- * @PIN_CONFIG_MAX: this is the maximum configuration value that can be
+ * @PIN_CONFIG_MAX: This is the maximum configuration value that can be
  *	presented using the packed format.
  */
 enum pin_config_param {
@@ -301,13 +481,14 @@ enum pin_config_param {
 
 #if CONFIG_IS_ENABLED(PINCTRL_GENERIC)
 /**
- * pinctrl_generic_set_state() - generic set_state operation
+ * pinctrl_generic_set_state() - Generic set_state operation
+ * @pctldev:	Pinctrl device to use
+ * @config:	Config device (pseudo device), pointing a config node in DTS
+ *
  * Parse the DT node of @config and its children and handle generic properties
  * such as "pins", "groups", "functions", and pin configuration parameters.
  *
- * @pctldev: pinctrl device
- * @config: config device (pseudo device), pointing a config node in DTS
- * @return: 0 on success, or negative error code on failure
+ * Return: 0 on success, or negative error code on failure
  */
 int pinctrl_generic_set_state(struct udevice *pctldev, struct udevice *config);
 #else
@@ -320,11 +501,11 @@ static inline int pinctrl_generic_set_state(struct udevice *pctldev,
 
 #if CONFIG_IS_ENABLED(PINCTRL)
 /**
- * pinctrl_select_state() - set a device to a given state
+ * pinctrl_select_state() - Set a device to a given state
+ * @dev:	Peripheral device
+ * @statename:	State name, like "default"
  *
- * @dev: peripheral device
- * @statename: state name, like "default"
- * @return: 0 on success, or negative error code on failure
+ * Return: 0 on success, or negative error code on failure
  */
 int pinctrl_select_state(struct udevice *dev, const char *statename);
 #else
@@ -337,40 +518,43 @@ static inline int pinctrl_select_state(struct udevice *dev,
 
 /**
  * pinctrl_request() - Request a particular pinctrl function
- *
- * @dev:	Device to check (UCLASS_PINCTRL)
+ * @dev:	Pinctrl device to use
  * @func:	Function number (driver-specific)
  * @flags:	Flags (driver-specific)
- * @return 0 if OK, -ve on error
+ *
+ * Return: 0 if OK, or negative error code on failure
  */
 int pinctrl_request(struct udevice *dev, int func, int flags);
 
 /**
  * pinctrl_request_noflags() - Request a particular pinctrl function
+ * @dev:	Pinctrl device to use
+ * @func:	Function number (driver-specific)
  *
  * This is similar to pinctrl_request() but uses 0 for @flags.
  *
- * @dev:	Device to check (UCLASS_PINCTRL)
- * @func:	Function number (driver-specific)
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, or negative error code on failure
  */
 int pinctrl_request_noflags(struct udevice *dev, int func);
 
 /**
- * pinctrl_get_periph_id() - get the peripheral ID for a device
+ * pinctrl_get_periph_id() - Get the peripheral ID for a device
+ * @dev:	Pinctrl device to use for decoding
+ * @periph:	Device to check
  *
  * This generally looks at the peripheral's device tree node to work out the
  * peripheral ID. The return value is normally interpreted as enum periph_id.
  * so long as this is defined by the platform (which it should be).
  *
- * @dev:	Pinctrl device to use for decoding
- * @periph:	Device to check
- * @return peripheral ID of @periph, or -ENOENT on error
+ * Return: Peripheral ID of @periph, or -ENOENT on error
  */
 int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
 
 /**
  * pinctrl_get_gpio_mux() - get the mux value for a particular GPIO
+ * @dev:	Pinctrl device to use
+ * @banknum:	GPIO bank number
+ * @index:	GPIO index within the bank
  *
  * This allows the raw mux value for a GPIO to be obtained. It is
  * useful for displaying the function being used by that GPIO, such
@@ -378,66 +562,64 @@ int pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph);
  * subsystem and should not be used by generic code. Typically it is
  * used by a GPIO driver with knowledge of the SoC pinctrl setup.
  *
- * @dev:	Pinctrl device to use
- * @banknum:	GPIO bank number
- * @index:	GPIO index within the bank
- * @return mux value (SoC-specific, e.g. 0 for input, 1 for output)
+ * Return: Mux value (SoC-specific, e.g. 0 for input, 1 for output)
 */
 int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index);
 
 /**
  * pinctrl_get_pin_muxing() - Returns the muxing description
+ * @dev:	Pinctrl device to use
+ * @selector:	Pin index within pin-controller
+ * @buf:	Pin's muxing description
+ * @size:	Pin's muxing description length
  *
  * This allows to display the muxing description of the given pin for
  * debug purpose
  *
- * @dev:	Pinctrl device to use
- * @selector	Pin index within pin-controller
- * @buf		Pin's muxing description
- * @size	Pin's muxing description length
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, or negative error code on failure
  */
 int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
 			   int size);
 
 /**
- * pinctrl_get_pins_count() - display pin-controller pins number
+ * pinctrl_get_pins_count() - Display pin-controller pins number
+ * @dev:	Pinctrl device to use
  *
  * This allows to know the number of pins owned by a given pin-controller
  *
- * @dev:	Pinctrl device to use
- * @return pins number if OK, -ve on error
+ * Return: Number of pins if OK, or negative error code on failure
  */
 int pinctrl_get_pins_count(struct udevice *dev);
 
 /**
  * pinctrl_get_pin_name() - Returns the pin's name
+ * @dev:	Pinctrl device to use
+ * @selector:	Pin index within pin-controller
+ * @buf:	Buffer to fill with the name of the pin
+ * @size:	Size of @buf
  *
  * This allows to display the pin's name for debug purpose
  *
- * @dev:	Pinctrl device to use
- * @selector	Pin index within pin-controller
- * @buf		Pin's name
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, or negative error code on failure
  */
 int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
 			 int size);
 
 /**
- * pinctrl_gpio_request() - request a single pin to be used as GPIO
+ * pinctrl_gpio_request() - Request a single pin to be used as GPIO
+ * @dev:	GPIO peripheral device
+ * @offset:	GPIO pin offset from the GPIO controller
  *
- * @dev: GPIO peripheral device
- * @offset: the GPIO pin offset from the GPIO controller
- * @return: 0 on success, or negative error code on failure
+ * Return: 0 on success, or negative error code on failure
  */
 int pinctrl_gpio_request(struct udevice *dev, unsigned offset);
 
 /**
- * pinctrl_gpio_free() - free a single pin used as GPIO
+ * pinctrl_gpio_free() - Free a single pin used as GPIO
+ * @dev:	GPIO peripheral device
+ * @offset:	GPIO pin offset from the GPIO controller
  *
- * @dev: GPIO peripheral device
- * @offset: the GPIO pin offset from the GPIO controller
- * @return: 0 on success, or negative error code on failure
+ * Return: 0 on success, or negative error code on failure
  */
 int pinctrl_gpio_free(struct udevice *dev, unsigned offset);
 
diff --git a/include/dt-bindings/pinctrl/k210-pinctrl.h b/include/dt-bindings/pinctrl/k210-pinctrl.h
new file mode 100644
index 00000000000..26c1f23b0fe
--- /dev/null
+++ b/include/dt-bindings/pinctrl/k210-pinctrl.h
@@ -0,0 +1,277 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <[email protected]>
+ */
+
+#ifndef DT_K210_PINCTRL_H
+#define DT_K210_PINCTRL_H
+
+/*
+ * Full list of FPIOA functions from
+ * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
+ */
+#define K210_PCF_MASK GENMASK(7, 0)
+#define K210_PCF_JTAG_TCLK      0   /* JTAG Test Clock */
+#define K210_PCF_JTAG_TDI       1   /* JTAG Test Data In */
+#define K210_PCF_JTAG_TMS       2   /* JTAG Test Mode Select */
+#define K210_PCF_JTAG_TDO       3   /* JTAG Test Data Out */
+#define K210_PCF_SPI0_D0        4   /* SPI0 Data 0 */
+#define K210_PCF_SPI0_D1        5   /* SPI0 Data 1 */
+#define K210_PCF_SPI0_D2        6   /* SPI0 Data 2 */
+#define K210_PCF_SPI0_D3        7   /* SPI0 Data 3 */
+#define K210_PCF_SPI0_D4        8   /* SPI0 Data 4 */
+#define K210_PCF_SPI0_D5        9   /* SPI0 Data 5 */
+#define K210_PCF_SPI0_D6        10  /* SPI0 Data 6 */
+#define K210_PCF_SPI0_D7        11  /* SPI0 Data 7 */
+#define K210_PCF_SPI0_SS0       12  /* SPI0 Chip Select 0 */
+#define K210_PCF_SPI0_SS1       13  /* SPI0 Chip Select 1 */
+#define K210_PCF_SPI0_SS2       14  /* SPI0 Chip Select 2 */
+#define K210_PCF_SPI0_SS3       15  /* SPI0 Chip Select 3 */
+#define K210_PCF_SPI0_ARB       16  /* SPI0 Arbitration */
+#define K210_PCF_SPI0_SCLK      17  /* SPI0 Serial Clock */
+#define K210_PCF_UARTHS_RX      18  /* UART High speed Receiver */
+#define K210_PCF_UARTHS_TX      19  /* UART High speed Transmitter */
+#define K210_PCF_RESV6          20  /* Reserved function */
+#define K210_PCF_RESV7          21  /* Reserved function */
+#define K210_PCF_CLK_SPI1       22  /* Clock SPI1 */
+#define K210_PCF_CLK_I2C1       23  /* Clock I2C1 */
+#define K210_PCF_GPIOHS0        24  /* GPIO High speed 0 */
+#define K210_PCF_GPIOHS1        25  /* GPIO High speed 1 */
+#define K210_PCF_GPIOHS2        26  /* GPIO High speed 2 */
+#define K210_PCF_GPIOHS3        27  /* GPIO High speed 3 */
+#define K210_PCF_GPIOHS4        28  /* GPIO High speed 4 */
+#define K210_PCF_GPIOHS5        29  /* GPIO High speed 5 */
+#define K210_PCF_GPIOHS6        30  /* GPIO High speed 6 */
+#define K210_PCF_GPIOHS7        31  /* GPIO High speed 7 */
+#define K210_PCF_GPIOHS8        32  /* GPIO High speed 8 */
+#define K210_PCF_GPIOHS9        33  /* GPIO High speed 9 */
+#define K210_PCF_GPIOHS10       34  /* GPIO High speed 10 */
+#define K210_PCF_GPIOHS11       35  /* GPIO High speed 11 */
+#define K210_PCF_GPIOHS12       36  /* GPIO High speed 12 */
+#define K210_PCF_GPIOHS13       37  /* GPIO High speed 13 */
+#define K210_PCF_GPIOHS14       38  /* GPIO High speed 14 */
+#define K210_PCF_GPIOHS15       39  /* GPIO High speed 15 */
+#define K210_PCF_GPIOHS16       40  /* GPIO High speed 16 */
+#define K210_PCF_GPIOHS17       41  /* GPIO High speed 17 */
+#define K210_PCF_GPIOHS18       42  /* GPIO High speed 18 */
+#define K210_PCF_GPIOHS19       43  /* GPIO High speed 19 */
+#define K210_PCF_GPIOHS20       44  /* GPIO High speed 20 */
+#define K210_PCF_GPIOHS21       45  /* GPIO High speed 21 */
+#define K210_PCF_GPIOHS22       46  /* GPIO High speed 22 */
+#define K210_PCF_GPIOHS23       47  /* GPIO High speed 23 */
+#define K210_PCF_GPIOHS24       48  /* GPIO High speed 24 */
+#define K210_PCF_GPIOHS25       49  /* GPIO High speed 25 */
+#define K210_PCF_GPIOHS26       50  /* GPIO High speed 26 */
+#define K210_PCF_GPIOHS27       51  /* GPIO High speed 27 */
+#define K210_PCF_GPIOHS28       52  /* GPIO High speed 28 */
+#define K210_PCF_GPIOHS29       53  /* GPIO High speed 29 */
+#define K210_PCF_GPIOHS30       54  /* GPIO High speed 30 */
+#define K210_PCF_GPIOHS31       55  /* GPIO High speed 31 */
+#define K210_PCF_GPIO0          56  /* GPIO pin 0 */
+#define K210_PCF_GPIO1          57  /* GPIO pin 1 */
+#define K210_PCF_GPIO2          58  /* GPIO pin 2 */
+#define K210_PCF_GPIO3          59  /* GPIO pin 3 */
+#define K210_PCF_GPIO4          60  /* GPIO pin 4 */
+#define K210_PCF_GPIO5          61  /* GPIO pin 5 */
+#define K210_PCF_GPIO6          62  /* GPIO pin 6 */
+#define K210_PCF_GPIO7          63  /* GPIO pin 7 */
+#define K210_PCF_UART1_RX       64  /* UART1 Receiver */
+#define K210_PCF_UART1_TX       65  /* UART1 Transmitter */
+#define K210_PCF_UART2_RX       66  /* UART2 Receiver */
+#define K210_PCF_UART2_TX       67  /* UART2 Transmitter */
+#define K210_PCF_UART3_RX       68  /* UART3 Receiver */
+#define K210_PCF_UART3_TX       69  /* UART3 Transmitter */
+#define K210_PCF_SPI1_D0        70  /* SPI1 Data 0 */
+#define K210_PCF_SPI1_D1        71  /* SPI1 Data 1 */
+#define K210_PCF_SPI1_D2        72  /* SPI1 Data 2 */
+#define K210_PCF_SPI1_D3        73  /* SPI1 Data 3 */
+#define K210_PCF_SPI1_D4        74  /* SPI1 Data 4 */
+#define K210_PCF_SPI1_D5        75  /* SPI1 Data 5 */
+#define K210_PCF_SPI1_D6        76  /* SPI1 Data 6 */
+#define K210_PCF_SPI1_D7        77  /* SPI1 Data 7 */
+#define K210_PCF_SPI1_SS0       78  /* SPI1 Chip Select 0 */
+#define K210_PCF_SPI1_SS1       79  /* SPI1 Chip Select 1 */
+#define K210_PCF_SPI1_SS2       80  /* SPI1 Chip Select 2 */
+#define K210_PCF_SPI1_SS3       81  /* SPI1 Chip Select 3 */
+#define K210_PCF_SPI1_ARB       82  /* SPI1 Arbitration */
+#define K210_PCF_SPI1_SCLK      83  /* SPI1 Serial Clock */
+#define K210_PCF_SPI2_D0        84  /* SPI2 Data 0 */
+#define K210_PCF_SPI2_SS        85  /* SPI2 Select */
+#define K210_PCF_SPI2_SCLK      86  /* SPI2 Serial Clock */
+#define K210_PCF_I2S0_MCLK      87  /* I2S0 Master Clock */
+#define K210_PCF_I2S0_SCLK      88  /* I2S0 Serial Clock(BCLK) */
+#define K210_PCF_I2S0_WS        89  /* I2S0 Word Select(LRCLK) */
+#define K210_PCF_I2S0_IN_D0     90  /* I2S0 Serial Data Input 0 */
+#define K210_PCF_I2S0_IN_D1     91  /* I2S0 Serial Data Input 1 */
+#define K210_PCF_I2S0_IN_D2     92  /* I2S0 Serial Data Input 2 */
+#define K210_PCF_I2S0_IN_D3     93  /* I2S0 Serial Data Input 3 */
+#define K210_PCF_I2S0_OUT_D0    94  /* I2S0 Serial Data Output 0 */
+#define K210_PCF_I2S0_OUT_D1    95  /* I2S0 Serial Data Output 1 */
+#define K210_PCF_I2S0_OUT_D2    96  /* I2S0 Serial Data Output 2 */
+#define K210_PCF_I2S0_OUT_D3    97  /* I2S0 Serial Data Output 3 */
+#define K210_PCF_I2S1_MCLK      98  /* I2S1 Master Clock */
+#define K210_PCF_I2S1_SCLK      99  /* I2S1 Serial Clock(BCLK) */
+#define K210_PCF_I2S1_WS        100 /* I2S1 Word Select(LRCLK) */
+#define K210_PCF_I2S1_IN_D0     101 /* I2S1 Serial Data Input 0 */
+#define K210_PCF_I2S1_IN_D1     102 /* I2S1 Serial Data Input 1 */
+#define K210_PCF_I2S1_IN_D2     103 /* I2S1 Serial Data Input 2 */
+#define K210_PCF_I2S1_IN_D3     104 /* I2S1 Serial Data Input 3 */
+#define K210_PCF_I2S1_OUT_D0    105 /* I2S1 Serial Data Output 0 */
+#define K210_PCF_I2S1_OUT_D1    106 /* I2S1 Serial Data Output 1 */
+#define K210_PCF_I2S1_OUT_D2    107 /* I2S1 Serial Data Output 2 */
+#define K210_PCF_I2S1_OUT_D3    108 /* I2S1 Serial Data Output 3 */
+#define K210_PCF_I2S2_MCLK      109 /* I2S2 Master Clock */
+#define K210_PCF_I2S2_SCLK      110 /* I2S2 Serial Clock(BCLK) */
+#define K210_PCF_I2S2_WS        111 /* I2S2 Word Select(LRCLK) */
+#define K210_PCF_I2S2_IN_D0     112 /* I2S2 Serial Data Input 0 */
+#define K210_PCF_I2S2_IN_D1     113 /* I2S2 Serial Data Input 1 */
+#define K210_PCF_I2S2_IN_D2     114 /* I2S2 Serial Data Input 2 */
+#define K210_PCF_I2S2_IN_D3     115 /* I2S2 Serial Data Input 3 */
+#define K210_PCF_I2S2_OUT_D0    116 /* I2S2 Serial Data Output 0 */
+#define K210_PCF_I2S2_OUT_D1    117 /* I2S2 Serial Data Output 1 */
+#define K210_PCF_I2S2_OUT_D2    118 /* I2S2 Serial Data Output 2 */
+#define K210_PCF_I2S2_OUT_D3    119 /* I2S2 Serial Data Output 3 */
+#define K210_PCF_RESV0          120 /* Reserved function */
+#define K210_PCF_RESV1          121 /* Reserved function */
+#define K210_PCF_RESV2          122 /* Reserved function */
+#define K210_PCF_RESV3          123 /* Reserved function */
+#define K210_PCF_RESV4          124 /* Reserved function */
+#define K210_PCF_RESV5          125 /* Reserved function */
+#define K210_PCF_I2C0_SCLK      126 /* I2C0 Serial Clock */
+#define K210_PCF_I2C0_SDA       127 /* I2C0 Serial Data */
+#define K210_PCF_I2C1_SCLK      128 /* I2C1 Serial Clock */
+#define K210_PCF_I2C1_SDA       129 /* I2C1 Serial Data */
+#define K210_PCF_I2C2_SCLK      130 /* I2C2 Serial Clock */
+#define K210_PCF_I2C2_SDA       131 /* I2C2 Serial Data */
+#define K210_PCF_DVP_XCLK       132 /* DVP System Clock */
+#define K210_PCF_DVP_RST        133 /* DVP System Reset */
+#define K210_PCF_DVP_PWDN       134 /* DVP Power Down Mode */
+#define K210_PCF_DVP_VSYNC      135 /* DVP Vertical Sync */
+#define K210_PCF_DVP_HSYNC      136 /* DVP Horizontal Sync */
+#define K210_PCF_DVP_PCLK       137 /* Pixel Clock */
+#define K210_PCF_DVP_D0         138 /* Data Bit 0 */
+#define K210_PCF_DVP_D1         139 /* Data Bit 1 */
+#define K210_PCF_DVP_D2         140 /* Data Bit 2 */
+#define K210_PCF_DVP_D3         141 /* Data Bit 3 */
+#define K210_PCF_DVP_D4         142 /* Data Bit 4 */
+#define K210_PCF_DVP_D5         143 /* Data Bit 5 */
+#define K210_PCF_DVP_D6         144 /* Data Bit 6 */
+#define K210_PCF_DVP_D7         145 /* Data Bit 7 */
+#define K210_PCF_SCCB_SCLK      146 /* Serial Camera Control Bus Clock */
+#define K210_PCF_SCCB_SDA       147 /* Serial Camera Control Bus Data */
+#define K210_PCF_UART1_CTS      148 /* UART1 Clear To Send */
+#define K210_PCF_UART1_DSR      149 /* UART1 Data Set Ready */
+#define K210_PCF_UART1_DCD      150 /* UART1 Data Carrier Detect */
+#define K210_PCF_UART1_RI       151 /* UART1 Ring Indicator */
+#define K210_PCF_UART1_SIR_IN   152 /* UART1 Serial Infrared Input */
+#define K210_PCF_UART1_DTR      153 /* UART1 Data Terminal Ready */
+#define K210_PCF_UART1_RTS      154 /* UART1 Request To Send */
+#define K210_PCF_UART1_OUT2     155 /* UART1 User-designated Output 2 */
+#define K210_PCF_UART1_OUT1     156 /* UART1 User-designated Output 1 */
+#define K210_PCF_UART1_SIR_OUT  157 /* UART1 Serial Infrared Output */
+#define K210_PCF_UART1_BAUD     158 /* UART1 Transmit Clock Output */
+#define K210_PCF_UART1_RE       159 /* UART1 Receiver Output Enable */
+#define K210_PCF_UART1_DE       160 /* UART1 Driver Output Enable */
+#define K210_PCF_UART1_RS485_EN 161 /* UART1 RS485 Enable */
+#define K210_PCF_UART2_CTS      162 /* UART2 Clear To Send */
+#define K210_PCF_UART2_DSR      163 /* UART2 Data Set Ready */
+#define K210_PCF_UART2_DCD      164 /* UART2 Data Carrier Detect */
+#define K210_PCF_UART2_RI       165 /* UART2 Ring Indicator */
+#define K210_PCF_UART2_SIR_IN   166 /* UART2 Serial Infrared Input */
+#define K210_PCF_UART2_DTR      167 /* UART2 Data Terminal Ready */
+#define K210_PCF_UART2_RTS      168 /* UART2 Request To Send */
+#define K210_PCF_UART2_OUT2     169 /* UART2 User-designated Output 2 */
+#define K210_PCF_UART2_OUT1     170 /* UART2 User-designated Output 1 */
+#define K210_PCF_UART2_SIR_OUT  171 /* UART2 Serial Infrared Output */
+#define K210_PCF_UART2_BAUD     172 /* UART2 Transmit Clock Output */
+#define K210_PCF_UART2_RE       173 /* UART2 Receiver Output Enable */
+#define K210_PCF_UART2_DE       174 /* UART2 Driver Output Enable */
+#define K210_PCF_UART2_RS485_EN 175 /* UART2 RS485 Enable */
+#define K210_PCF_UART3_CTS      176 /* UART3 Clear To Send */
+#define K210_PCF_UART3_DSR      177 /* UART3 Data Set Ready */
+#define K210_PCF_UART3_DCD      178 /* UART3 Data Carrier Detect */
+#define K210_PCF_UART3_RI       179 /* UART3 Ring Indicator */
+#define K210_PCF_UART3_SIR_IN   180 /* UART3 Serial Infrared Input */
+#define K210_PCF_UART3_DTR      181 /* UART3 Data Terminal Ready */
+#define K210_PCF_UART3_RTS      182 /* UART3 Request To Send */
+#define K210_PCF_UART3_OUT2     183 /* UART3 User-designated Output 2 */
+#define K210_PCF_UART3_OUT1     184 /* UART3 User-designated Output 1 */
+#define K210_PCF_UART3_SIR_OUT  185 /* UART3 Serial Infrared Output */
+#define K210_PCF_UART3_BAUD     186 /* UART3 Transmit Clock Output */
+#define K210_PCF_UART3_RE       187 /* UART3 Receiver Output Enable */
+#define K210_PCF_UART3_DE       188 /* UART3 Driver Output Enable */
+#define K210_PCF_UART3_RS485_EN 189 /* UART3 RS485 Enable */
+#define K210_PCF_TIMER0_TOGGLE1 190 /* TIMER0 Toggle Output 1 */
+#define K210_PCF_TIMER0_TOGGLE2 191 /* TIMER0 Toggle Output 2 */
+#define K210_PCF_TIMER0_TOGGLE3 192 /* TIMER0 Toggle Output 3 */
+#define K210_PCF_TIMER0_TOGGLE4 193 /* TIMER0 Toggle Output 4 */
+#define K210_PCF_TIMER1_TOGGLE1 194 /* TIMER1 Toggle Output 1 */
+#define K210_PCF_TIMER1_TOGGLE2 195 /* TIMER1 Toggle Output 2 */
+#define K210_PCF_TIMER1_TOGGLE3 196 /* TIMER1 Toggle Output 3 */
+#define K210_PCF_TIMER1_TOGGLE4 197 /* TIMER1 Toggle Output 4 */
+#define K210_PCF_TIMER2_TOGGLE1 198 /* TIMER2 Toggle Output 1 */
+#define K210_PCF_TIMER2_TOGGLE2 199 /* TIMER2 Toggle Output 2 */
+#define K210_PCF_TIMER2_TOGGLE3 200 /* TIMER2 Toggle Output 3 */
+#define K210_PCF_TIMER2_TOGGLE4 201 /* TIMER2 Toggle Output 4 */
+#define K210_PCF_CLK_SPI2       202 /* Clock SPI2 */
+#define K210_PCF_CLK_I2C2       203 /* Clock I2C2 */
+#define K210_PCF_INTERNAL0      204 /* Internal function signal 0 */
+#define K210_PCF_INTERNAL1      205 /* Internal function signal 1 */
+#define K210_PCF_INTERNAL2      206 /* Internal function signal 2 */
+#define K210_PCF_INTERNAL3      207 /* Internal function signal 3 */
+#define K210_PCF_INTERNAL4      208 /* Internal function signal 4 */
+#define K210_PCF_INTERNAL5      209 /* Internal function signal 5 */
+#define K210_PCF_INTERNAL6      210 /* Internal function signal 6 */
+#define K210_PCF_INTERNAL7      211 /* Internal function signal 7 */
+#define K210_PCF_INTERNAL8      212 /* Internal function signal 8 */
+#define K210_PCF_INTERNAL9      213 /* Internal function signal 9 */
+#define K210_PCF_INTERNAL10     214 /* Internal function signal 10 */
+#define K210_PCF_INTERNAL11     215 /* Internal function signal 11 */
+#define K210_PCF_INTERNAL12     216 /* Internal function signal 12 */
+#define K210_PCF_INTERNAL13     217 /* Internal function signal 13 */
+#define K210_PCF_INTERNAL14     218 /* Internal function signal 14 */
+#define K210_PCF_INTERNAL15     219 /* Internal function signal 15 */
+#define K210_PCF_INTERNAL16     220 /* Internal function signal 16 */
+#define K210_PCF_INTERNAL17     221 /* Internal function signal 17 */
+#define K210_PCF_CONSTANT       222 /* Constant function */
+#define K210_PCF_INTERNAL18     223 /* Internal function signal 18 */
+#define K210_PCF_DEBUG0         224 /* Debug function 0 */
+#define K210_PCF_DEBUG1         225 /* Debug function 1 */
+#define K210_PCF_DEBUG2         226 /* Debug function 2 */
+#define K210_PCF_DEBUG3         227 /* Debug function 3 */
+#define K210_PCF_DEBUG4         228 /* Debug function 4 */
+#define K210_PCF_DEBUG5         229 /* Debug function 5 */
+#define K210_PCF_DEBUG6         230 /* Debug function 6 */
+#define K210_PCF_DEBUG7         231 /* Debug function 7 */
+#define K210_PCF_DEBUG8         232 /* Debug function 8 */
+#define K210_PCF_DEBUG9         233 /* Debug function 9 */
+#define K210_PCF_DEBUG10        234 /* Debug function 10 */
+#define K210_PCF_DEBUG11        235 /* Debug function 11 */
+#define K210_PCF_DEBUG12        236 /* Debug function 12 */
+#define K210_PCF_DEBUG13        237 /* Debug function 13 */
+#define K210_PCF_DEBUG14        238 /* Debug function 14 */
+#define K210_PCF_DEBUG15        239 /* Debug function 15 */
+#define K210_PCF_DEBUG16        240 /* Debug function 16 */
+#define K210_PCF_DEBUG17        241 /* Debug function 17 */
+#define K210_PCF_DEBUG18        242 /* Debug function 18 */
+#define K210_PCF_DEBUG19        243 /* Debug function 19 */
+#define K210_PCF_DEBUG20        244 /* Debug function 20 */
+#define K210_PCF_DEBUG21        245 /* Debug function 21 */
+#define K210_PCF_DEBUG22        246 /* Debug function 22 */
+#define K210_PCF_DEBUG23        247 /* Debug function 23 */
+#define K210_PCF_DEBUG24        248 /* Debug function 24 */
+#define K210_PCF_DEBUG25        249 /* Debug function 25 */
+#define K210_PCF_DEBUG26        250 /* Debug function 26 */
+#define K210_PCF_DEBUG27        251 /* Debug function 27 */
+#define K210_PCF_DEBUG28        252 /* Debug function 28 */
+#define K210_PCF_DEBUG29        253 /* Debug function 29 */
+#define K210_PCF_DEBUG30        254 /* Debug function 30 */
+#define K210_PCF_DEBUG31        255 /* Debug function 31 */
+
+#define K210_FPIOA(pin, func) (((pin) << 16) | (func))
+#define K210_FPIOA_DO(pin, func) (((pin) << 16) | (1 << 8) | (func))
+
+#define K210_PC_POWER_3V3 0
+#define K210_PC_POWER_1V8 1
+
+#endif /* DT_K210_PINCTRL_H */
diff --git a/include/dt-bindings/pinctrl/sandbox-pinmux.h b/include/dt-bindings/pinctrl/sandbox-pinmux.h
new file mode 100644
index 00000000000..891af072e52
--- /dev/null
+++ b/include/dt-bindings/pinctrl/sandbox-pinmux.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Sean Anderson <[email protected]>
+ */
+
+#ifndef SANDBOX_PINMUX_H
+#define SANDBOX_PINMUX_H
+
+#define SANDBOX_PINMUX_UART 0
+#define SANDBOX_PINMUX_I2C  1
+#define SANDBOX_PINMUX_SPI  2
+#define SANDBOX_PINMUX_I2S  3
+#define SANDBOX_PINMUX_GPIO 4
+#define SANDBOX_PINMUX_CS   5
+#define SANDBOX_PINMUX_PWM  6
+
+#define SANDBOX_PINMUX(pin, func) ((func) << 16 | (pin))
+
+#endif /* SANDBOX_PINMUX_H */