diff options
| author | Dave Liu <[email protected]> | 2009-12-16 10:24:36 -0600 |
|---|---|---|
| committer | Kumar Gala <[email protected]> | 2010-01-05 13:49:10 -0600 |
| commit | 0a71c92c7e1e565111cb34cd389a21ec500ca5c1 (patch) | |
| tree | abee130bc9075de43eb494b30e102a907ffda992 /include | |
| parent | c4ca10f1db36c3ce649c656dec14f7aab644dd86 (diff) | |
fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions