Merge tag 'xilinx-for-v2026.10-rc3' of https://git.u-boot-project.org/u-boot/custodians/u-boot-amd

AMD/Xilinx changes for v2026.10-rc3

Versal Gen 2:
- Add support for 2VM3654 device
- Add missing MAINTAINERS fragment

AMD:
- Fix fwu dfu_string generation not to alter with generic DFU

Firmware/ufs:
- UFS interface cleanup
- Remove ZynqMP firmware dependency from UFS

zynqmp_gqspi:
- Fix quad mode bus conflict

MB-V:
- shrink SPL size and enforce size limits
- remake ELF from BIN

2 files changed, 17 insertions, 5 deletions

diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h
index a07e12bd146..00627dcd943 100644
--- a/include/configs/amd_versal2.h
+++ b/include/configs/amd_versal2.h
@@ -19,6 +19,15 @@
 #define GICD_BASE	0xe2000000
 #define GICR_BASE	0xe2060000
 
+/*
+ * The 2VM3654 part has 4 APU cores and 3 GIC ITS blocks (vs 8 cores and a
+ * single ITS on the base part), which moves the redistributor region up by
+ * the two extra ITS blocks. The right base is selected at runtime in
+ * lowlevel_init() based on the PMC TAP IDCODE.
+ */
+#define GICR_BASE_2VM3654	0xe20a0000
+#define GICR_IDCODE_2VM3654	0x04d98093
+
 /* Serial setup */
 #define CFG_SYS_BAUDRATE_TABLE \
 	{ 4800, 9600, 19200, 38400, 57600, 115200 }
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 0e545e3db1b..f753a67ac27 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -465,10 +465,6 @@ int zynqmp_mmio_read(const u32 address, u32 *value);
 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
 int zynqmp_pm_feature(const u32 api_id);
 u32 zynqmp_pm_get_bootmode_reg(void);
-int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value);
-int zynqmp_pm_ufs_sram_csr_read(u32 *value);
-int zynqmp_pm_ufs_sram_csr_write(u32 *value);
-int zynqmp_pm_ufs_cal_reg(u32 *value);
 u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
 u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr);
 
@@ -535,7 +531,14 @@ extern smc_call_handler_t __data smc_call_handler;
 
 #define PM_DEV_OSPI		(0x1822402aU)
 
-#define PM_REG_PGGS3	0x30004003
+#define PM_REGNODE_PMC_IOU_SLCR		0x30000002
+#define PM_REGNODE_EFUSE_CACHE		0x30000003
+#define PM_REG_PGGS3			0x30004003
+
+#define SRAM_CSR_OFFSET			0x104C
+#define TXRX_CFGRDY_OFFSET		0x1054
+#define UFS_CAL_1_OFFSET		0xBE8
+
 #define PMC_GLOBAL_PGGS3_REG_NODE	0x1824C005
 
 #endif /* _ZYNQMP_FIRMWARE_H_ */