Merge tag 'mmc-for-2026.10-rc2' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mmc

CI: https://git.u-boot-project.org/u-boot/custodians/u-boot-mmc/-/pipelines/781

- Enable MMC CMD23 for multi-block transfers
- Various fixes to mmc core
- Add PF9453 pmic/regulator driver
- Support SCP 4.36 map for renesas-r8a78000

3 files changed, 74 insertions, 2 deletions

diff --git a/include/mmc.h b/include/mmc.h
index 9509c9e9543..4bda44ea220 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -67,6 +67,7 @@ struct bd_info;
 #define MMC_CAP_NONREMOVABLE	BIT(14)
 #define MMC_CAP_NEEDS_POLL	BIT(15)
 #define MMC_CAP_CD_ACTIVE_HIGH  BIT(16)
+#define MMC_CAP_CMD23		BIT(17)
 
 #define MMC_MODE_8BIT		BIT(30)
 #define MMC_MODE_4BIT		BIT(29)
@@ -141,6 +142,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define SD_HIGHSPEED_BUSY	0x00020000
 #define SD_HIGHSPEED_SUPPORTED	0x00020000
 
+#define SD_SCR_CMD23_SUPPORT	BIT(1)
+
 #define UHS_SDR12_BUS_SPEED	0
 #define HIGH_SPEED_BUS_SPEED	1
 #define UHS_SDR25_BUS_SPEED	1
diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h
index 0f6f5c23dee..258623d5c67 100644
--- a/include/mvebu_mmc.h
+++ b/include/mvebu_mmc.h
@@ -253,8 +253,6 @@
 #define MMC_CAP_DRIVER_TYPE_C			(1 << 24)
 /* Host supports Driver Type D */
 #define MMC_CAP_DRIVER_TYPE_D			(1 << 25)
-/* CMD23 supported. */
-#define MMC_CAP_CMD23				(1 << 30)
 /* Hardware reset */
 #define MMC_CAP_HW_RESET			(1 << 31)
 
diff --git a/include/power/pf9453.h b/include/power/pf9453.h
new file mode 100644
index 00000000000..f33b839cde0
--- /dev/null
+++ b/include/power/pf9453.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2024 NXP
+ */
+
+#ifndef PF9453_H_
+#define PF9453_H_
+
+#define PF9453_REGULATOR_DRIVER "pf9453_regulator"
+
+enum {
+	PF9453_REG_DEV_ID          = 0x00,
+	PF9453_OTP_VER             = 0x01,
+	PF9453_INT1                = 0x02,
+	PF9453_INT1_MSK            = 0x03,
+	PF9453_INT1_STATUS         = 0x04,
+	PF9453_VRFLT1_INT          = 0x05,
+	PF9453_VRFLT1_MASK         = 0x06,
+	PF9453_PWRON_STAT          = 0x07,
+	PF9453_RESET_CTRL          = 0x08,
+	PF9453_SW_RST              = 0x09,
+	PF9453_PWR_CTRL            = 0x0a,
+	PF9453_CONFIG1             = 0x0b,
+	PF9453_CONFIG2             = 0x0c,
+	PF9453_32K_CONFIG          = 0x0d,
+	PF9453_BUCK1CTRL           = 0x10,
+	PF9453_BUCK1OUT            = 0x11,
+	PF9453_BUCK2CTRL           = 0x14,
+	PF9453_BUCK2OUT            = 0x15,
+	PF9453_BUCK2OUT_STBY       = 0x1D,
+	PF9453_BUCK2OUT_MAX_LIMIT  = 0x1F,
+	PF9453_BUCK2OUT_MIN_LIMIT  = 0x20,
+	PF9453_BUCK3CTRL           = 0x21,
+	PF9453_BUCK3OUT            = 0x22,
+	PF9453_BUCK4CTRL           = 0x2e,
+	PF9453_BUCK4OUT            = 0x2f,
+	PF9453_LDO1OUT_L          = 0x36,
+	PF9453_LDO1CFG            = 0x37,
+	PF9453_LDO1OUT_H          = 0x38,
+	PF9453_LDOSNVS_CFG1        = 0x39,
+	PF9453_LDOSNVS_CFG2        = 0x3a,
+	PF9453_LDO2CFG            = 0x3b,
+	PF9453_LDO2OUT            = 0x3c,
+	PF9453_BUCK_POK            = 0x3d,
+	PF9453_LSW_CTRL1           = 0x40,
+	PF9453_LSW_CTRL2           = 0x41,
+	PF9453_REG_LOCK            = 0x4e,
+	PF9453_REG_NUM,
+};
+
+int power_pf9453_init(unsigned char bus, unsigned char addr);
+
+enum {
+	NXP_CHIP_TYPE_PF9453 = 0,
+	NXP_CHIP_TYPE_AMOUNT
+};
+
+#define PF9453_UNLOCK_KEY		0x5c
+#define PF9453_LOCK_KEY			0x0
+
+#define PF9453_EN_MODE_MASK		0x3
+#define PF9453_BUCK_RUN_MASK		0x7f
+#define PF9453_LDO1_MASK		0x7f
+#define PF9453_LDO2_MASK		0x3f
+#define PF9453_LDOSNVS_MASK		0x7f
+
+#define PF9453_PMIC_RESET_WDOG_B_CFG_MASK		0xc0
+#define PF9453_PMIC_RESET_WDOG_B_CFG_WARM		0x40
+#define PF9453_PMIC_RESET_WDOG_B_CFG_COLD		0x80
+
+#endif