Merge branch 'master' into next

author: Tom Rini <[email protected]> 2023-05-08 14:31:04 -0400
committer: Tom Rini <[email protected]> 2023-05-08 14:31:04 -0400
commit: 11910550b65e6072b9542d462c0aa93f4ca81836 (patch)
tree: 8308c98ffad76d9693654a28090b03f270a7d250 /include
parent: 9876c8c147144db2c120fcc9ffa6de27f6894441 (diff)
parent: f1d33a44ca04fdca241c1d89fd79e2e56c930c7e (diff)
113 files changed, 2734 insertions, 544 deletions
diff --git a/include/android_image.h b/include/android_image.h
index 54d25af0684..d503c980b23 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -3,7 +3,7 @@
  * This is from the Android Project,
  * Repository: https://android.googlesource.com/platform/system/tools/mkbootimg
  * File: include/bootimg/bootimg.h
- * Commit: e55998a0f2b61b685d5eb4a486ca3a0c680b1a2f
+ * Commit: cce5b1923e3cd2fcb765b512610bdc5c42bc501d
  *
  * Copyright (C) 2007 The Android Open Source Project
  */
@@ -14,15 +14,70 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 
+#define ANDR_GKI_PAGE_SIZE 4096
 #define ANDR_BOOT_MAGIC "ANDROID!"
 #define ANDR_BOOT_MAGIC_SIZE 8
 #define ANDR_BOOT_NAME_SIZE 16
 #define ANDR_BOOT_ARGS_SIZE 512
 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
+#define VENDOR_BOOT_MAGIC "VNDRBOOT"
+#define ANDR_VENDOR_BOOT_MAGIC_SIZE 8
+#define ANDR_VENDOR_BOOT_ARGS_SIZE 2048
+#define ANDR_VENDOR_BOOT_NAME_SIZE 16
 
-/* The bootloader expects the structure of andr_img_hdr with header
+#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
+#define BOOTCONFIG_MAGIC_SIZE 12
+#define BOOTCONFIG_SIZE_SIZE 4
+#define BOOTCONFIG_CHECKSUM_SIZE 4
+#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
+				BOOTCONFIG_SIZE_SIZE + \
+				BOOTCONFIG_CHECKSUM_SIZE
+
+struct andr_boot_img_hdr_v3 {
+	u8 magic[ANDR_BOOT_MAGIC_SIZE];
+
+	u32 kernel_size;    /* size in bytes */
+	u32 ramdisk_size;   /* size in bytes */
+
+	u32 os_version;
+
+	u32 header_size;    /* size of boot image header in bytes */
+	u32 reserved[4];
+	u32 header_version; /* offset remains constant for version check */
+
+	u8 cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE];
+	/* for boot image header v4 only */
+	u32 signature_size; /* size in bytes */
+};
+
+struct andr_vnd_boot_img_hdr {
+	u8 magic[ANDR_VENDOR_BOOT_MAGIC_SIZE];
+	u32 header_version;
+	u32 page_size;           /* flash page size we assume */
+
+	u32 kernel_addr;         /* physical load addr */
+	u32 ramdisk_addr;        /* physical load addr */
+
+	u32 vendor_ramdisk_size; /* size in bytes */
+
+	u8 cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE];
+
+	u32 tags_addr;           /* physical addr for kernel tags */
+
+	u8 name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */
+	u32 header_size;         /* size of vendor boot image header in bytes */
+	u32 dtb_size;            /* size of dtb image */
+	u64 dtb_addr;            /* physical load address */
+	/* for boot image header v4 only */
+	u32 vendor_ramdisk_table_size; /* size in bytes for the vendor ramdisk table */
+	u32 vendor_ramdisk_table_entry_num; /* number of entries in the vendor ramdisk table */
+	u32 vendor_ramdisk_table_entry_size; /* size in bytes for a vendor ramdisk table entry */
+	u32 bootconfig_size; /* size in bytes for the bootconfig section */
+};
+
+/* The bootloader expects the structure of andr_boot_img_hdr_v0 with header
  * version 0 to be as follows: */
-struct andr_img_hdr {
+struct andr_boot_img_hdr_v0 {
     /* Must be ANDR_BOOT_MAGIC. */
     char magic[ANDR_BOOT_MAGIC_SIZE];
 
@@ -136,4 +191,171 @@ struct andr_img_hdr {
  *    else: jump to kernel_addr
  */
 
+/* When the boot image header has a version of 3, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ *
+ * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes.
+ *
+ * The structure of the vendor boot image (introduced with version 3 and
+ * required to be present when a v3 boot image is used) is as follows:
+ *
+ * +---------------------+
+ * | vendor boot header  | o pages
+ * +---------------------+
+ * | vendor ramdisk      | p pages
+ * +---------------------+
+ * | dtb                 | q pages
+ * +---------------------+
+ * o = (2112 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisk at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. set up registers for kernel entry as required by your architecture
+ * 6. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+
+/* When the boot image header has a version of 4, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ * | boot signature      | g pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ * g = (signature_size + 4096 - 1) / 4096
+ *
+ * Note that in version 4 of the boot image header, page size is fixed at 4096
+ * bytes.
+ *
+ * The structure of the vendor boot image version 4, which is required to be
+ * present when a version 4 boot image is used, is as follows:
+ *
+ * +------------------------+
+ * | vendor boot header     | o pages
+ * +------------------------+
+ * | vendor ramdisk section | p pages
+ * +------------------------+
+ * | dtb                    | q pages
+ * +------------------------+
+ * | vendor ramdisk table   | r pages
+ * +------------------------+
+ * | bootconfig             | s pages
+ * +------------------------+
+ *
+ * o = (2128 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ * r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+ * s = (vendor_bootconfig_size + page_size - 1) / page_size
+ *
+ * Note that in version 4 of the vendor boot image, multiple vendor ramdisks can
+ * be included in the vendor boot image. The bootloader can select a subset of
+ * ramdisks to load at runtime. To help the bootloader select the ramdisks, each
+ * ramdisk is tagged with a type tag and a set of hardware identifiers
+ * describing the board, soc or platform that this ramdisk is intended for.
+ *
+ * The vendor ramdisk section is consist of multiple ramdisk images concatenated
+ * one after another, and vendor_ramdisk_size is the size of the section, which
+ * is the total size of all the ramdisks included in the vendor boot image.
+ *
+ * The vendor ramdisk table holds the size, offset, type, name and hardware
+ * identifiers of each ramdisk. The type field denotes the type of its content.
+ * The vendor ramdisk names are unique. The hardware identifiers are specified
+ * in the board_id field in each table entry. The board_id field is consist of a
+ * vector of unsigned integer words, and the encoding scheme is defined by the
+ * hardware vendor.
+ *
+ * For the different type of ramdisks, there are:
+ *    - VENDOR_RAMDISK_TYPE_NONE indicates the value is unspecified.
+ *    - VENDOR_RAMDISK_TYPE_PLATFORM ramdisks contain platform specific bits, so
+ *      the bootloader should always load these into memory.
+ *    - VENDOR_RAMDISK_TYPE_RECOVERY ramdisks contain recovery resources, so
+ *      the bootloader should load these when booting into recovery.
+ *    - VENDOR_RAMDISK_TYPE_DLKM ramdisks contain dynamic loadable kernel
+ *      modules.
+ *
+ * Version 4 of the vendor boot image also adds a bootconfig section to the end
+ * of the image. This section contains Boot Configuration parameters known at
+ * build time. The bootloader is responsible for placing this section directly
+ * after the generic ramdisk, followed by the bootconfig trailer, before
+ * entering the kernel.
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisks at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. load the bootconfig immediately following the generic ramdisk. Add
+ *    additional bootconfig parameters followed by the bootconfig trailer.
+ * 6. set up registers for kernel entry as required by your architecture
+ * 7. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+
+/* Private struct */
+struct andr_image_data {
+	ulong kernel_ptr;  /* kernel address */
+	u32 kernel_size;  /* size in bytes */
+	u32 ramdisk_size;  /* size in bytes */
+	ulong vendor_ramdisk_ptr;  /* vendor ramdisk address */
+	u32 vendor_ramdisk_size;  /* vendor ramdisk size*/
+	u32 boot_ramdisk_size;  /* size in bytes */
+	ulong second_ptr;  /* secondary bootloader address */
+	u32 second_size;  /* secondary bootloader size */
+	ulong dtb_ptr;  /* address of dtb image */
+	u32 dtb_size;  /* size of dtb image */
+	ulong recovery_dtbo_ptr;  /* size in bytes for recovery DTBO/ACPIO image */
+	u32 recovery_dtbo_size;  /* offset to recovery dtbo/acpio in boot image */
+
+	const char *kcmdline;  /* boot kernel cmdline */
+	const char *kcmdline_extra;  /* vendor-boot extra kernel cmdline */
+	const char *image_name;  /* asciiz product name */
+
+	ulong bootconfig_addr;  /* bootconfig image address */
+	ulong bootconfig_size;  /* bootconfig image size */
+
+	u32 kernel_addr;  /* physical load addr */
+	ulong ramdisk_addr;  /* physical load addr */
+	ulong ramdisk_ptr;  /* ramdisk address */
+	ulong dtb_load_addr;  /* physical load address for DTB image */
+	ulong tags_addr;  /* physical addr for kernel tags */
+	u32 header_version;  /* version of the boot image header */
+	u32 boot_img_total_size;  /* boot image size */
+	u32 vendor_boot_img_total_size;  /* vendor boot image size */
+};
+
 #endif
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 987fb66c17a..65bf8df1e56 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -68,7 +68,7 @@ struct global_data {
 	 * @mem_clk: memory clock rate in Hz
 	 */
 	unsigned long mem_clk;
-#if defined(CONFIG_VIDEO)
+#if CONFIG_IS_ENABLED(VIDEO)
 	/**
 	 * @fb_base: base address of frame buffer memory
 	 */
@@ -359,7 +359,7 @@ struct global_data {
 	 */
 	struct membuff console_in;
 #endif
-#ifdef CONFIG_VIDEO
+#if CONFIG_IS_ENABLED(VIDEO)
 	/**
 	 * @video_top: top of video frame buffer area
 	 */
diff --git a/include/axp209.h b/include/axp209.h
index 414f88a32c6..d8bf44f1fa6 100644
--- a/include/axp209.h
+++ b/include/axp209.h
@@ -77,7 +77,6 @@ enum axp209_reg {
 #ifdef CONFIG_AXP209_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_GPIO0_CTRL			0x90
 #define AXP_GPIO1_CTRL			0x92
 #define AXP_GPIO2_CTRL			0x93
diff --git a/include/axp221.h b/include/axp221.h
index 8dfcc5b5a23..32b988f3a9c 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -53,7 +53,6 @@
 #ifdef CONFIG_AXP221_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/axp809.h b/include/axp809.h
index 8082e402e2a..71a7cb2aaa1 100644
--- a/include/axp809.h
+++ b/include/axp809.h
@@ -47,7 +47,6 @@
 #ifdef CONFIG_AXP809_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/axp818.h b/include/axp818.h
index 8ac517a2bf2..08ac35d15fa 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -61,7 +61,6 @@
 #ifdef CONFIG_AXP818_POWER
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_ALDO_IN		BIT(0)
-#define AXP_POWER_STATUS_VBUS_PRESENT		BIT(5)
 #define AXP_VBUS_IPSOUT			0x30
 #define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
 #define AXP_MISC_CTRL			0x8f
diff --git a/include/binman_sym.h b/include/binman_sym.h
index 528d7e4e90e..49a95eafade 100644
--- a/include/binman_sym.h
+++ b/include/binman_sym.h
@@ -71,7 +71,7 @@
  * value #defined above. This is used to check at runtime if the
  * symbol values were filled in and are OK to use.
  */
-extern ulong _binman_sym_magic;
+extern unsigned long _binman_sym_magic;
 
 /**
  * DECLARE_BINMAN_MAGIC_SYM - Declare the internal magic symbol
@@ -81,7 +81,7 @@ extern ulong _binman_sym_magic;
  * definitions of the symbol.
  */
 #define DECLARE_BINMAN_MAGIC_SYM \
-	ulong _binman_sym_magic \
+	unsigned long _binman_sym_magic \
 		__attribute__((aligned(4), section(".binman_sym")))
 
 /**
@@ -93,14 +93,14 @@ extern ulong _binman_sym_magic;
  * Return: 1 if binman symbol values are usable, 0 if not
  */
 #define BINMAN_SYMS_OK \
-	(*(ulong *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
+	(*(unsigned long *)&_binman_sym_magic == BINMAN_SYM_MAGIC_VALUE)
 
 /**
  * binman_sym() - Access a previously declared symbol
  *
  * This is used to get the value of a symbol. E.g.:
  *
- *    ulong address = binman_sym(ulong, u_boot_spl, pos);
+ *    unsigned long address = binman_sym(unsigned long, u_boot_spl, pos);
  *
  * @_type: Type f the symbol (e.g. unsigned long)
  * @entry_name: Name of the entry to look for (e.g. 'u_boot_spl')
diff --git a/include/blk.h b/include/blk.h
index 1db203c1bab..2c9c7985a88 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -62,10 +62,9 @@ struct blk_desc {
 	unsigned char	hwpart;		/* HW partition, e.g. for eMMC */
 	unsigned char	type;		/* device type */
 	unsigned char	removable;	/* removable device */
-#ifdef CONFIG_LBA48
 	/* device can use 48bit addr (ATA/ATAPI v7) */
-	unsigned char	lba48;
-#endif
+	bool	lba48;
+	unsigned char	atapi;		/* Use ATAPI protocol */
 	lbaint_t	lba;		/* number of blocks */
 	unsigned long	blksz;		/* block size */
 	int		log2blksz;	/* for convenience: log2(blksz) */
diff --git a/include/blkmap.h b/include/blkmap.h
new file mode 100644
index 00000000000..af54583c7dd
--- /dev/null
+++ b/include/blkmap.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Addiva Elektronik
+ * Author: Tobias Waldekranz <[email protected]>
+ */
+
+#ifndef _BLKMAP_H
+#define _BLKMAP_H
+
+/**
+ * blkmap_map_linear() - Map region of other block device
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @lblk: The target block device of the mapping
+ * @lblknr: The start block number of the target device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_linear(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		      struct udevice *lblk, lbaint_t lblknr);
+
+/**
+ * blkmap_map_mem() - Map region of memory
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @addr: The target memory address of the mapping
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_mem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		   void *addr);
+
+/**
+ * blkmap_map_pmem() - Map region of physical memory
+ *
+ * Ensures that a valid physical to virtual memory mapping for the
+ * requested region is valid for the lifetime of the mapping, on
+ * architectures that require it (sandbox).
+ *
+ * @dev: Blkmap to create the mapping on
+ * @blknr: Start block number of the mapping
+ * @blkcnt: Number of blocks to map
+ * @paddr: The target physical memory address of the mapping
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_map_pmem(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
+		    phys_addr_t paddr);
+
+
+/**
+ * blkmap_from_label() - Find blkmap from label
+ *
+ * @label: Label of the requested blkmap
+ * Returns: A pointer to the blkmap on success, NULL on failure
+ */
+struct udevice *blkmap_from_label(const char *label);
+
+/**
+ * blkmap_create() - Create new blkmap
+ *
+ * @label: Label of the new blkmap
+ * @devp: If not NULL, updated with the address of the resulting device
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_create(const char *label, struct udevice **devp);
+
+/**
+ * blkmap_destroy() - Destroy blkmap
+ *
+ * @dev: The blkmap to be destroyed
+ * Returns: 0 on success, negative error code on failure
+ */
+int blkmap_destroy(struct udevice *dev);
+
+#endif	/* _BLKMAP_H */
diff --git a/include/bootdev.h b/include/bootdev.h
index b92ff4d4f15..e72ef3650f7 100644
--- a/include/bootdev.h
+++ b/include/bootdev.h
@@ -258,7 +258,7 @@ int bootdev_find_by_label(const char *label, struct udevice **devp,
  * @devp: returns the device found, on success
  * @method_flagsp: If non-NULL, returns any flags implied by the label
  * (enum bootflow_meth_flags_t), 0 if none. Unset if function fails
- * Return: 0 if OK, -EINVAL if the uclass is not supported by this board,
+ * Return: 0 if OK, -EPFNOSUPPORT if the uclass is not supported by this board,
  * -ENOENT if there is no device with that number
  */
 int bootdev_find_by_any(const char *name, struct udevice **devp,
diff --git a/include/cli.h b/include/cli.h
index c777c90313f..094a6602d70 100644
--- a/include/cli.h
+++ b/include/cli.h
@@ -98,8 +98,8 @@ int cli_readline(const char *const prompt);
  *
  * @prompt:	Prompt to display
  * @buffer:	Place to put the line that is entered
- * @timeout:	Timeout in milliseconds, 0 if none
- * Return: command line length excluding terminator, or -ve on error: of the
+ * @timeout:	Timeout in seconds, 0 if none
+ * Return: command line length excluding terminator, or -ve on error: if the
  * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
  * parameter), then -2 is returned. If a break is detected (Ctrl-C) then
  * -1 is returned.
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 4b89f31209a..d4c1e066884 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -111,6 +111,5 @@
 #define CFG_SYS_CS0_MASK		0x007F0001
 #define CFG_SYS_CS0_CTRL		0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif				/* _M5208EVBE_H */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 14d46178116..e5428183400 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -130,6 +130,5 @@
 #	define CFG_SYS_CS0_CTRL	0x00001D80
 #endif
 
-#define CFG_MCFTMR
 
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index b24042328d3..2f4743ce50c 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -120,6 +120,5 @@
 #define	CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED		0x00400000	/* user led                     */
 
-#define CFG_MCFTMR
 
 #endif	/* M5249 */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 008c7257c43..0ff0bfce90b 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -132,6 +132,5 @@
 #define CFG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED		0x00400000	/* user led */
 
-#define CFG_MCFTMR
 
 #endif				/* _M5253DEMO_H */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 49cf3e878ea..98a17181a41 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -107,6 +107,5 @@
 #define CFG_SYS_PBDAT		0x0000
 #define CFG_SYS_PDCNT		0x00000000
 
-#define CFG_MCFTMR
 
 #endif				/* _M5272C3_H */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 965327d759d..77ddf717643 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -116,6 +116,5 @@
 #define CFG_SYS_CS1_CTRL		0x00001900
 #define CFG_SYS_CS1_MASK		0x00070001
 
-#define CFG_MCFTMR
 
 #endif	/* _M5275EVB_H */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index f04d9b1b2ab..e289a23b800 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -127,6 +127,5 @@
 #define CFG_SYS_DDRUA		0x05
 #define CFG_SYS_PJPAR		0xFF
 
-#define CFG_MCFTMR
 
 #endif				/* _CONFIG_M5282EVB_H */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 04c456ff9f1..dcc5701ee0b 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -132,6 +132,5 @@
 #define CFG_SYS_CS1_MASK		0x00070001
 #define CFG_SYS_CS1_CTRL		0x00001FA0
 
-#define CFG_MCFTMR
 
 #endif				/* _M53017EVB_H */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 0aa1ffd4d4f..dd5d4c98023 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -138,6 +138,5 @@
 #define CFG_SYS_CS2_CTRL		0x00001f60
 #endif
 
-#define CFG_MCFTMR
 
 #endif				/* _M5329EVB_H */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 8b9e65de98c..4bb99487509 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -136,6 +136,5 @@
 #define CFG_SYS_CS2_MASK		(16 << 20)
 #define CFG_SYS_CS2_CTRL		0x00001f60
 
-#define CFG_MCFTMR
 
 #endif				/* _M5373EVB_H */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 70b1c399241..3967cc28363 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -140,7 +140,9 @@
 /*
  * Serial Port
  */
+#if !CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(DM_CLK)
 #define CFG_SYS_NS16550_CLK		get_bus_freq(0)
+#endif
 
 #define CFG_SYS_BAUDRATE_TABLE \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 26a7f2521ec..1e37ab47b9a 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -18,91 +18,6 @@
 /* DDR Configuration */
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
-#define PARTS_DEFAULT \
-	/* Linux partitions */ \
-	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
-
-/* U-Boot general configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS					\
-	"findfdt="							\
-		"if test $board_name = am64x_gpevm; then " \
-			"setenv fdtfile k3-am642-evm.dtb; fi; " \
-		"if test $board_name = am64x_skevm; then " \
-			"setenv fdtfile k3-am642-sk.dtb; fi;" \
-		"if test $fdtfile = undefined; then " \
-			"echo WARNING: Could not determine device tree to use; fi; \0" \
-	"name_kern=Image\0"						\
-	"console=ttyS2,115200n8\0"					\
-	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "	\
-		"${mtdparts}\0"						\
-	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
-
-/* U-Boot MMC-specific configuration */
-#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
-	"boot=mmc\0"							\
-	"mmcdev=1\0"							\
-	"bootpart=1:2\0"						\
-	"bootdir=/boot\0"						\
-	"rd_spec=-\0"							\
-	"init_mmc=run args_all args_mmc\0"				\
-	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-	"get_overlay_mmc="						\
-		"fdt address ${fdtaddr};"				\
-		"fdt resize 0x100000;"					\
-		"for overlay in $name_overlays;"			\
-		"do;"							\
-		"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
-		"fdt apply ${dtboaddr};"				\
-		"done;\0"						\
-	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
-		"${bootdir}/${name_fit}\0"				\
-	"partitions=" PARTS_DEFAULT
-
-#define EXTRA_ENV_AM642_BOARD_SETTING_USBMSC				\
-	"args_usb=run finduuid;setenv bootargs console=${console} "	\
-		"${optargs} "						\
-		"root=PARTUUID=${uuid} rw "				\
-		"rootfstype=${mmcrootfstype}\0"				\
-	"init_usb=run args_all args_usb\0"				\
-	"get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
-	"get_overlay_usb="						\
-		"fdt address ${fdtaddr};"				\
-		"fdt resize 0x100000;"					\
-		"for overlay in $name_overlays;"			\
-		"do;"							\
-		"load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
-		"fdt apply ${dtboaddr};"				\
-		"done;\0"						\
-	"get_kern_usb=load usb ${bootpart} ${loadaddr} "		\
-		"${bootdir}/${name_kern}\0"				\
-	"get_fit_usb=load usb ${bootpart} ${addr_fit} "			\
-		"${bootdir}/${name_fit}\0"				\
-	"usbboot=setenv boot usb;"					\
-		"setenv bootpart 0:2;"					\
-		"usb start;"						\
-		"run findfdt;"						\
-		"run init_usb;"						\
-		"run get_kern_usb;"					\
-		"run get_fdt_usb;"					\
-		"run run_kern\0"
-
-#define EXTRA_ENV_DFUARGS \
-	DFU_ALT_INFO_MMC \
-	DFU_ALT_INFO_EMMC \
-	DFU_ALT_INFO_RAM \
-	DFU_ALT_INFO_OSPI
-
-/* Incorporate settings into the U-Boot environment */
-#define CFG_EXTRA_ENV_SETTINGS					\
-	DEFAULT_LINUX_BOOT_ENV						\
-	DEFAULT_MMC_TI_ARGS						\
-	EXTRA_ENV_AM642_BOARD_SETTINGS					\
-	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
-	EXTRA_ENV_DFUARGS						\
-	EXTRA_ENV_AM642_BOARD_SETTING_USBMSC
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index ca8d17bfd2c..4c695fb9df9 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -10,7 +10,6 @@
 
 #define CFG_SYS_UART_PORT		0
 
-#define CFG_MCFTMR
 #define CFG_SYS_UART_PORT		0
 #define CFG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }
 
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 80f8c4129f5..f3bfefa835e 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -184,6 +184,5 @@
 #define CFG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
 					 CF_CACR_DCM_P)
 
-#define CFG_MCFTMR
 
 #endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/bcmns.h b/include/configs/bcmns.h
new file mode 100644
index 00000000000..6f5f2b7ccf2
--- /dev/null
+++ b/include/configs/bcmns.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BCM_NS_H
+#define __BCM_NS_H
+
+#include <linux/sizes.h>
+
+/* Physical Memory Map */
+#define V2M_BASE			0x00000000
+#define PHYS_SDRAM_1			V2M_BASE
+
+#define CFG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Called "periph_clk" in Linux, used by the global timer */
+#define CFG_SYS_HZ_CLOCK		500000000
+
+/* Called "iprocslow" in Linux */
+#define CFG_SYS_NS16550_CLK		125000000
+
+/* console configuration */
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=2\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}"	\
+		  " ${max_cpus}  ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0"
+
+#define KERNEL_LOADADDR_CFG \
+	"loadaddr=0x01000000\0" \
+	"dtb_loadaddr=0x02000000\0"
+
+/*
+ * Hardcoded for the only boards we support, if you add more
+ * boards, add a more clever bootcmd!
+ */
+#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000"
+
+#define ARCH_ENV_SETTINGS \
+	CONSOLE_ARGS \
+	MAX_CPUS \
+	EXTRA_ARGS \
+	KERNEL_LOADADDR_CFG \
+	NS_BOOTCMD
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	ARCH_ENV_SETTINGS
+
+#endif /* __BCM_NS_H */
diff --git a/include/configs/cmpc885.h b/include/configs/cmpc885.h
index 4ce580cd142..545365e1128 100644
--- a/include/configs/cmpc885.h
+++ b/include/configs/cmpc885.h
@@ -9,6 +9,7 @@
 /* Definitions for initial stack pointer and data area (in DPRAM) */
 #define CFG_SYS_INIT_RAM_ADDR		(CONFIG_SYS_IMMR + 0x2800)
 #define CFG_SYS_INIT_RAM_SIZE		(0x2e00 - 0x2800)
+#define CFG_SYS_INIT_SP			(CONFIG_SYS_IMMR + 0x3c00)
 
 /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
 #define CFG_SYS_SDRAM_BASE		0x00000000
@@ -26,4 +27,10 @@
 /* NAND configuration part */
 #define CFG_SYS_NAND_BASE		0xC0000000
 
+/* Board names */
+#define CFG_BOARD_CMPCXXX		"cmpc885"
+#define CFG_BOARD_MCR3000_2G		"mcr3k_2g"
+#define CFG_BOARD_VGOIP			"vgoip"
+#define CFG_BOARD_MIAE			"miae"
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/cmpcpro.h b/include/configs/cmpcpro.h
new file mode 100644
index 00000000000..24e62dfcf0c
--- /dev/null
+++ b/include/configs/cmpcpro.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2006-2023  CS GROUP France
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/*
+ * System IO Config
+ */
+#define CFG_SYS_SICRL		0x00000000
+
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000
+
+#define CFG_SYS_DDRCDR		0x73000002	/* DDR II voltage is 1.8V */
+
+/*
+ * Manually set up DDR parameters
+ */
+
+/* DDR 512 M */
+#define CFG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ODT_WR_CFG | CSCONFIG_BANK_BIT_3 | \
+				 CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10)
+/* 0x80840102 */
+#define CFG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+/* 0x00220802 */
+#define CFG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) | \
+				 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (5 << TIMING_CFG1_CASLAT_SHIFT) | \
+				 (27 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (2 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT))
+/* 0x3935D322 */
+#define CFG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (31 << TIMING_CFG2_CPO_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+/* 0x0F9048CA */
+#define CFG_SYS_DDR_TIMING_3	0x00000000
+#define CFG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+/* 0x02000000 */
+#define CFG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) | (0x0232 << SDRAM_MODE_SD_SHIFT))
+/* 0x44400232 */
+#define CFG_SYS_DDR_MODE2	0x8000c000
+#define CFG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) | \
+				 (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+#define CFG_SYS_DDR_CS0_BNDS	(CFG_SYS_DDR_SDRAM_BASE >> 8 | 0x0000001F)
+
+#define CFG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_32_BE)
+/* 0x43080000 */
+#define CFG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CFG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x110000)
+#define CFG_SYS_INIT_RAM_SIZE	0x4000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_SYS_FLASH_BASE	0x40000000	/* FLASH base address */
+#define CFG_SYS_FLASH_SIZE	64		/* FLASH size is 64M */
+
+/*
+ * NAND
+ */
+#define CFG_SYS_NAND_BASE	0xa0000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CFG_SYS_BOOTMAPSZ	SZ_256M
+
+/* Board names */
+#define CFG_BOARD_CMPCXXX	"cmpcpro"
+#define CFG_BOARD_MCR3000_2G	"mcrpro"
+#define CFG_BOARD_VGOIP		"vgoippro"
+#define CFG_BOARD_MIAE		"miaepro"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 276ecc30ccc..556705fb09f 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -184,6 +184,5 @@ configuration */
 #define CFG_SYS_PBDAT		0x0000			/* PortB value reg. */
 #define CFG_SYS_PDCNT		0x00000000		/* PortD control reg. */
 
-#define CFG_MCFTMR
 
 #endif	/* _CONFIG_COBRA5272_H */
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index ba45ee4efd3..561a61ebc03 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -99,7 +99,7 @@
 		"${board}/flash_blk.img && source ${loadaddr}\0" \
 	"setup=setenv setupargs " \
 		"console=tty1 console=${console}" \
-		",${baudrate}n8 ${memargs} consoleblank=0\0" \
+		",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \
 	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
 	"setusbupdate=usb start && setenv interface usb && " \
 		"fatload ${interface} 0:1 ${loadaddr} " \
diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h
index c568643977c..03f8ed14787 100644
--- a/include/configs/colibri_imx7.h
+++ b/include/configs/colibri_imx7.h
@@ -141,7 +141,7 @@
 		"${board}/flash_blk.img && source ${loadaddr}\0" \
 	"setup=setenv setupargs " \
 		"console=tty1 console=${console}" \
-		",${baudrate}n8 ${memargs} consoleblank=0\0" \
+		",${baudrate}n8 ${memargs} ${mtdparts} consoleblank=0\0" \
 	"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
 	"setusbupdate=usb start && setenv interface usb && " \
 		"fatload ${interface} 0:1 ${loadaddr} " \
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index e9b382a3b77..4b5ef4ad510 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -31,7 +31,6 @@
 #define CFG_MXC_UART_BASE		UART1_BASE
 
 /* USB Configs */
-#ifdef CONFIG_CMD_USB
 #define CFG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CFG_MXC_USB_FLAGS		0
 
@@ -39,7 +38,6 @@
 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 #define DFU_DEFAULT_POLL_TIMEOUT	300
 #endif
-#endif
 
 #define CFG_EXTRA_ENV_SETTINGS	\
 	"console=ttymxc0,115200\0"	\
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 9503ab66f0f..e2c9d9c43ce 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -138,7 +138,6 @@
 #define CFG_SYS_DDRUA		0x05
 #define CFG_SYS_PJPAR		0xFF
 
-#define CFG_MCFTMR
 
 #endif	/* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/
diff --git a/include/configs/evb_rk3588.h b/include/configs/evb_rk3588.h
new file mode 100644
index 00000000000..4568e2cace6
--- /dev/null
+++ b/include/configs/evb_rk3588.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __EVB_RK3588_H
+#define __EVB_RK3588_H
+
+#include <configs/rk3588_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
+
+#endif
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index 446261cedc7..0b62ff9fbe1 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -9,17 +9,7 @@
 #ifndef __FALCON_H
 #define __FALCON_H
 
-#include "rcar-gen3-common.h"
-
-/*
- * Generic Interrupt Controller Definitions.  Undefine v2 locations and define
- * v3 locations.
- */
-#undef GICD_BASE
-#undef GICC_BASE
-#undef GICR_BASE
-#define GICD_BASE	0xF1000000
-#define GICR_BASE	0xF1060000
+#include "rcar-gen4-common.h"
 
 /* Board Clock */
 /* XTAL_CLK : 16.66MHz */
diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h
new file mode 100644
index 00000000000..3db9a474ec7
--- /dev/null
+++ b/include/configs/hc2910-2aghd05.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __HC2910_2AGHD05_CONFIG_H__
+#define __HC2910_2AGHD05_CONFIG_H__
+
+#endif
diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h
index e97b8e871d2..deeed9c2f58 100644
--- a/include/configs/imx8mn_bsh_smm_s2.h
+++ b/include/configs/imx8mn_bsh_smm_s2.h
@@ -14,7 +14,7 @@
 #include <config_distro_bootcmd.h>
 
 #define NANDARGS \
-	"nandargs=setenv bootargs console=${console} " \
+	"nandargs=setenv bootargs " \
 		"${optargs} " \
 		"mtdparts=${mtdparts} " \
 		"root=${nandroot} " \
diff --git a/include/configs/imx8mp_beacon.h b/include/configs/imx8mp_beacon.h
new file mode 100644
index 00000000000..ee0fd07e650
--- /dev/null
+++ b/include/configs/imx8mp_beacon.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Logic PD, Inc dba Beacon EmbeddedWorks
+ */
+
+#ifndef __IMX8MP_BEACON_H
+#define __IMX8MP_BEACON_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#if defined(CONFIG_CMD_NET)
+#define PHY_ANEG_TIMEOUT 20000
+#endif
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR	0x40000000
+#define CFG_SYS_INIT_RAM_SIZE	0x80000
+
+/* Totally 6GB DDR */
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
+#define PHYS_SDRAM_2			0x100000000
+#define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
+
+#endif
diff --git a/include/configs/imx8mp_data_modul_edm_sbc.h b/include/configs/imx8mp_data_modul_edm_sbc.h
new file mode 100644
index 00000000000..11ac3c00f7e
--- /dev/null
+++ b/include/configs/imx8mp_data_modul_edm_sbc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Marek Vasut <[email protected]>
+ */
+
+#ifndef __IMX8MP_DATA_MODUL_EDM_SBC_H
+#define __IMX8MP_DATA_MODUL_EDM_SBC_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+/* Link Definitions */
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x200000
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x40000000 /* Minimum 1 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART3_BASE_ADDR
+
+/* PHY needs a longer autonegotiation timeout after reset */
+#define PHY_ANEG_TIMEOUT		20000
+#define FEC_QUIRK_ENET_MAC
+
+#define CFG_EXTRA_ENV_SETTINGS						\
+	"altbootcmd=setenv devpart 2 && run bootcmd ; reset\0"		\
+	"bootlimit=3\0"							\
+	"devtype=mmc\0"							\
+	"devpart=1\0"							\
+	/* Give slow devices beyond USB HUB chance to come up. */	\
+	"usb_pgood_delay=2000\0"					\
+	"dmo_update_env="						\
+		"setenv dmo_update_env true ; saveenv ; saveenv\0"	\
+	"dmo_update_sf_write_data="					\
+		"sf probe && sf update ${loadaddr} 0 ${filesize}\0"	\
+	"dmo_update_emmc_to_sf="					\
+		"load mmc 0:1 ${loadaddr} boot/flash.bin && "		\
+		"run dmo_update_sf_write_data\0"			\
+	"dmo_update_sd_to_sf="						\
+		"load mmc 1:1 ${loadaddr} boot/flash.bin && "		\
+		"run dmo_update_sf_write_data\0"
+
+#endif
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 00000000000..3148e8622e1
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif
diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h
new file mode 100644
index 00000000000..f9cda5eec7d
--- /dev/null
+++ b/include/configs/imx8qm_dmsse20.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2019 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#ifndef __IMX8QM_DMSSE20_H
+#define __IMX8QM_DMSSE20_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+/* Flat Device Tree Definitions */
+
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+#define USDHC1_BASE_ADDR		0x5B010000
+#define USDHC2_BASE_ADDR		0x5B020000
+#define USDHC3_BASE_ADDR		0x5B030000
+
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x5B040000
+/* FEC1 */
+#define IMX_FEC1_BASE			0x5B040000
+/* FEC2 */
+#define IMX_FEC2_BASE			0x5B050000
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+
+#define CFG_SYS_SDRAM_BASE		0x080000000
+#define PHYS_SDRAM_1			0x080000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x080000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x180000000	/* 6 GB */
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#endif /* __IMX8QM_DMSSE20_H */
diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h
index 2fa93b79614..1e0da9f96c5 100644
--- a/include/configs/j721s2_evm.h
+++ b/include/configs/j721s2_evm.h
@@ -16,7 +16,7 @@
 #define CFG_SYS_SDRAM_BASE1		0x880000000
 
 /* SPL Loader Configuration */
-#if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J721S2_A72_EVM)
 #define CFG_SYS_UBOOT_BASE		0x50280000
 /* Image load address in RAM for DFU boot*/
 #else
diff --git a/include/configs/mcr3000.h b/include/configs/mcr3000.h
index 6b16b050ff3..a07761fdbb2 100644
--- a/include/configs/mcr3000.h
+++ b/include/configs/mcr3000.h
@@ -14,6 +14,7 @@
 /* Definitions for initial stack pointer and data area (in DPRAM) */
 #define CFG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x2800)
 #define	CFG_SYS_INIT_RAM_SIZE	(0x2e00 - 0x2800)
+#define CFG_SYS_INIT_SP		(CONFIG_SYS_IMMR + 0x3c00)
 
 /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
 #define	CFG_SYS_SDRAM_BASE		0x00000000
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
deleted file mode 100644
index 39d0b403139..00000000000
--- a/include/configs/omap5_uevm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Sricharan R	  <[email protected]>
- *
- * Configuration settings for the TI EVM5430 board.
- * See ti_omap5_common.h for omap5 common settings.
- */
-
-#ifndef __CONFIG_OMAP5_EVM_H
-#define __CONFIG_OMAP5_EVM_H
-
-#include <environment/ti/dfu.h>
-
-#ifndef CONFIG_SPL_BUILD
-/* Define the default GPT table for eMMC */
-#define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
-#endif
-
-#define DFUARGS \
-	"dfu_bufsiz=0x10000\0" \
-	DFU_ALT_INFO_MMC \
-	DFU_ALT_INFO_EMMC \
-	DFU_ALT_INFO_RAM
-
-#include <configs/ti_omap5_common.h>
-
-#define CFG_SYS_NS16550_COM3		UART3_BASE
-
-/* MMC ENV related defines */
-
-/* Required support for the TCA642X GPIO we have on the uEVM */
-#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CFG_SYS_I2C_TCA642X_ADDR 0x22
-
-/* Enabled commands */
-
-/* USB Networking options */
-
-#define CONSOLEDEV		"ttyS2"
-
-#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h
index 8df481b0978..6fbd2679f09 100644
--- a/include/configs/px30_common.h
+++ b/include/configs/px30_common.h
@@ -24,12 +24,11 @@
 	"kernel_addr_c=0x03e80000\0" \
 	"ramdisk_addr_r=0x0a200000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h
new file mode 100644
index 00000000000..c4f506df62d
--- /dev/null
+++ b/include/configs/rcar-gen4-common.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/rcar-gen4-common.h
+ *	This file is R-Car Gen4 common configuration file.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#ifndef __RCAR_GEN4_COMMON_H
+#define __RCAR_GEN4_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+/* Console */
+#define CFG_SYS_BAUDRATE_TABLE	{ 38400, 115200, 921600, 1843200 }
+
+/* Memory */
+#define DRAM_RSV_SIZE			0x08000000
+#define CFG_SYS_SDRAM_BASE		(0x40000000 + DRAM_RSV_SIZE)
+#define CFG_SYS_SDRAM_SIZE		(0x80000000u - DRAM_RSV_SIZE)
+#define CFG_MAX_MEM_MAPPED		(0x80000000u - DRAM_RSV_SIZE)
+
+/* PHY needs a longer autoneg timeout */
+#define PHY_ANEG_TIMEOUT		20000
+
+/* Environment setting */
+#define CFG_EXTRA_ENV_SETTINGS					\
+	"bootm_size=0x10000000\0"
+
+#endif	/* __RCAR_GEN4_COMMON_H */
diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h
index ea6073f2944..c2abd14e114 100644
--- a/include/configs/rk3036_common.h
+++ b/include/configs/rk3036_common.h
@@ -21,8 +21,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -30,6 +28,6 @@
 	"fdt_high=0x7fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h
index 1a6d3678df3..d70c8f77d48 100644
--- a/include/configs/rk3066_common.h
+++ b/include/configs/rk3066_common.h
@@ -22,14 +22,12 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdt_high=0x6fffffff\0" \
 	"initrd_high=0x6fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h
index 8736b14d101..d8269b0ec96 100644
--- a/include/configs/rk3128_common.h
+++ b/include/configs/rk3128_common.h
@@ -22,11 +22,10 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index fcb274565e9..a8cee1e44d4 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -21,8 +21,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -32,6 +30,6 @@
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
index 39a40f4e2d1..15f77df3e17 100644
--- a/include/configs/rk322x_common.h
+++ b/include/configs/rk322x_common.h
@@ -22,8 +22,6 @@
 	"kernel_addr_r=0x62000000\0" \
 	"ramdisk_addr_r=0x64000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
  * so limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -31,6 +29,6 @@
 	"fdt_high=0x7fffffff\0" \
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 71d2426d72a..3063076a97a 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -23,8 +23,6 @@
 	"kernel_addr_r=0x02000000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
-
 /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so
  * limit the fdt reallocation to that */
 #define CFG_EXTRA_ENV_SETTINGS \
@@ -34,6 +32,6 @@
 	"partitions=" PARTS_DEFAULT \
 	ENV_MEM_LAYOUT_SETTINGS \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h
index ba9ee112e2d..7d55fcd975c 100644
--- a/include/configs/rk3308_common.h
+++ b/include/configs/rk3308_common.h
@@ -20,11 +20,10 @@
 	"kernel_addr_r=0x00680000\0" \
 	"ramdisk_addr_r=0x04000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"partitions=" PARTS_DEFAULT \
 	ROCKCHIP_DEVICE_SETTINGS \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h
index e565ccff897..e920ec7e5dd 100644
--- a/include/configs/rk3328_common.h
+++ b/include/configs/rk3328_common.h
@@ -22,11 +22,10 @@
 	"kernel_comp_addr_r=0x08000000\0" \
 	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index 9aa256b5959..ccb5369b901 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,11 +23,9 @@
 	"kernel_addr_r=0x280000\0" \
 	"ramdisk_addr_r=0x5bf0000\0"
 
-#include <config_distro_bootcmd.h>
-
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
-	ENV_MEM_LAYOUT_SETTINGS	\
-	BOOTENV
+	ENV_MEM_LAYOUT_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h
index a5e1dde5088..1b7d3437b1a 100644
--- a/include/configs/rk3568_common.h
+++ b/include/configs/rk3568_common.h
@@ -17,17 +17,21 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS		\
 	"scriptaddr=0x00c00000\0"	\
+	"script_offset_f=0xffe000\0"	\
+	"script_size_f=0x2000\0"	\
 	"pxefile_addr_r=0x00e00000\0"	\
 	"fdt_addr_r=0x0a100000\0"	\
+	"fdtoverlay_addr_r=0x02000000\0"	\
 	"kernel_addr_r=0x02080000\0"	\
-	"ramdisk_addr_r=0x0a200000\0"
+	"ramdisk_addr_r=0x0a200000\0"	\
+	"kernel_comp_addr_r=0x08000000\0"	\
+	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS		\
 	ENV_MEM_LAYOUT_SETTINGS			\
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT		\
-	ROCKCHIP_DEVICE_SETTINGS		\
-	BOOTENV
+	ROCKCHIP_DEVICE_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h
index abd20139aaf..46389d087d2 100644
--- a/include/configs/rk3588_common.h
+++ b/include/configs/rk3588_common.h
@@ -16,17 +16,21 @@
 
 #define ENV_MEM_LAYOUT_SETTINGS		\
 	"scriptaddr=0x00c00000\0"	\
+	"script_offset_f=0xffe000\0"	\
+	"script_size_f=0x2000\0"	\
 	"pxefile_addr_r=0x00e00000\0"	\
 	"fdt_addr_r=0x0a100000\0"	\
+	"fdtoverlay_addr_r=0x02000000\0"	\
 	"kernel_addr_r=0x02080000\0"	\
-	"ramdisk_addr_r=0x0a200000\0"
+	"ramdisk_addr_r=0x0a200000\0"	\
+	"kernel_comp_addr_r=0x08000000\0"	\
+	"kernel_comp_size=0x2000000\0"
 
-#include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT		\
 	ENV_MEM_LAYOUT_SETTINGS			\
-	ROCKCHIP_DEVICE_SETTINGS		\
-	BOOTENV
+	ROCKCHIP_DEVICE_SETTINGS \
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif /* __CONFIG_RK3588_COMMON_H */
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 18544d75acc..9121bba3738 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -13,69 +13,7 @@
 
 #ifndef CONFIG_SPL_BUILD
 
-/* First try to boot from SD (index 1), then eMMC (index 0) */
-#if IS_ENABLED(CONFIG_CMD_MMC)
-	#define BOOT_TARGET_MMC(func) \
-		func(MMC, mmc, 1) \
-		func(MMC, mmc, 0)
-#else
-	#define BOOT_TARGET_MMC(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_NVME)
-	#define BOOT_TARGET_NVME(func) func(NVME, nvme, 0)
-#else
-	#define BOOT_TARGET_NVME(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SCSI)
-	#define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0)
-#else
-	#define BOOT_TARGET_SCSI(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_USB)
-	#define BOOT_TARGET_USB(func) func(USB, usb, 0)
-#else
-	#define BOOT_TARGET_USB(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_PXE)
-	#define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
-#else
-	#define BOOT_TARGET_PXE(func)
-#endif
-
-#if CONFIG_IS_ENABLED(CMD_DHCP)
-	#define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
-#else
-	#define BOOT_TARGET_DHCP(func)
-#endif
-
-#if IS_ENABLED(CONFIG_CMD_SF)
-	#define BOOT_TARGET_SF(func)	func(SF, sf, 0)
-#else
-	#define BOOT_TARGET_SF(func)
-#endif
-
-#ifdef CONFIG_ROCKCHIP_RK3399
-#define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_MMC(func) \
-	BOOT_TARGET_NVME(func) \
-	BOOT_TARGET_SCSI(func) \
-	BOOT_TARGET_USB(func) \
-	BOOT_TARGET_PXE(func) \
-	BOOT_TARGET_DHCP(func) \
-	BOOT_TARGET_SF(func)
 #define BOOT_TARGETS	"mmc1 mmc0 nvme scsi usb pxe dhcp spi"
-#else
-#define BOOT_TARGET_DEVICES(func) \
-	BOOT_TARGET_MMC(func) \
-	BOOT_TARGET_USB(func) \
-	BOOT_TARGET_PXE(func) \
-	BOOT_TARGET_DHCP(func)
-#define BOOT_TARGETS	"mmc1 mmc0 usb pxe dhcp"
-#endif
 
 #ifdef CONFIG_ARM64
 #define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0"
diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h
index 050d37bff0b..3bf70a0e0ae 100644
--- a/include/configs/rv1108_common.h
+++ b/include/configs/rv1108_common.h
@@ -28,6 +28,6 @@
 	ENV_MEM_LAYOUT_SETTINGS \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"partitions=" PARTS_DEFAULT \
-	BOOTENV
+	"boot_targets=" BOOT_TARGETS "\0"
 
 #endif
diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
index 2211751b540..673268dca98 100644
--- a/include/configs/sdm845.h
+++ b/include/configs/sdm845.h
@@ -16,7 +16,7 @@
 #define CFG_EXTRA_ENV_SETTINGS \
 	"bootm_size=0x4000000\0"	\
 	"bootm_low=0x80000000\0"	\
-	"stdin=serial\0"	\
+	"stdin=serial,button-kbd\0"	\
 	"stdout=serial,vidconsole\0"	\
 	"stderr=serial,vidconsole\0"	\
 	"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 11031744bef..0aa25f9e2ea 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -17,23 +17,25 @@
 /* MMC Config*/
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
-#define CFG_EXTRA_ENV_SETTINGS \
-	"image=zImage\0" \
-	"console=ttymxc0\0" \
-	"fdtfile=imx7d-smegw01.dtb\0" \
-	"fdt_addr=0x83000000\0" \
-	"bootm_size=0x10000000\0" \
-	"mmcdev=0\0" \
-	"mmcpart=1\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
-	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"if run loadfdt; then " \
-			"bootz ${loadaddr} - ${fdt_addr}; " \
-		"fi;\0" \
+/* default to no extra bootparams, we need an empty define for stringification*/
+#ifndef EXTRA_BOOTPARAMS
+#define EXTRA_BOOTPARAMS
+#endif
+
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define EXTRA_ENV_FLAGS
+#else
+#define EXTRA_ENV_FLAGS "mmcdev:dw,"
+#endif
+
+#define CFG_ENV_FLAGS_LIST_STATIC \
+	"mmcpart:dw," \
+	"mmcpart_committed:dw," \
+	"ustate:dw," \
+	"bootcount:dw," \
+	"bootlimit:dw," \
+	"upgrade_available:dw," \
+	EXTRA_ENV_FLAGS
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
diff --git a/include/configs/spider.h b/include/configs/spider.h
new file mode 100644
index 00000000000..e9b7d6bad5e
--- /dev/null
+++ b/include/configs/spider.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/spider.h
+ *     This file is Spider board configuration.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __SPIDER_H
+#define __SPIDER_H
+
+#include "rcar-gen4-common.h"
+
+#endif /* __SPIDER_H */
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
new file mode 100644
index 00000000000..93dcc22d366
--- /dev/null
+++ b/include/configs/starfive-visionfive2.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author:	Yanhong Wang<[email protected]>
+ *
+ */
+
+#ifndef _STARFIVE_VISIONFIVE2_H
+#define _STARFIVE_VISIONFIVE2_H
+
+#define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMER_FREQ		4000000
+#define RISCV_SMODE_TIMER_FREQ		4000000
+
+#define __io
+
+/* Environment options */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define TYPE_GUID_SPL		"2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_UBOOT	"BC13C2FF-59E6-4262-A352-B275FD6F7172"
+#define TYPE_GUID_SYSTEM	"EBD0A0A2-B9E5-4433-87C0-68B6B72699C7"
+
+#define PARTS_DEFAULT							\
+		"name=spl,start=2M,size=2M,type=${type_guid_gpt_loader1};" \
+		"name=uboot,size=4MB,type=${type_guid_gpt_loader2};"		\
+		"name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	"kernel_addr_r=0x40200000\0" \
+	"kernel_comp_addr_r=0x88000000\0" \
+	"kernel_comp_size=0x4000000\0" \
+	"fdt_addr_r=0x46000000\0" \
+	"scriptaddr=0x43900000\0" \
+	"pxefile_addr_r=0x45900000\0" \
+	"ramdisk_addr_r=0x46100000\0" \
+	"type_guid_gpt_loader1=" TYPE_GUID_SPL "\0" \
+	"type_guid_gpt_loader2=" TYPE_GUID_UBOOT "\0" \
+	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+	"partitions=" PARTS_DEFAULT "\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	BOOTENV
+
+#endif /* _STARFIVE_VISIONFIVE2_H */
diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h
index ad8126f6103..20ec11477d6 100644
--- a/include/configs/stm32mp13_st_common.h
+++ b/include/configs/stm32mp13_st_common.h
@@ -9,7 +9,7 @@
 #define __CONFIG_STM32MP13_ST_COMMON_H__
 
 #define STM32MP_BOARD_EXTRA_ENV \
-	"usb_pgood_delay=1000\0" \
+	"usb_pgood_delay=2000\0" \
 	"console=ttySTM0\0"
 
 #include <configs/stm32mp13_common.h>
diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h
index d0cd4130cec..866cd7a719f 100644
--- a/include/configs/stm32mp15_st_common.h
+++ b/include/configs/stm32mp15_st_common.h
@@ -9,6 +9,7 @@
 #define __CONFIG_STM32MP15_ST_COMMON_H__
 
 #define STM32MP_BOARD_EXTRA_ENV \
+	"usb_pgood_delay=2000\0" \
 	"console=ttySTM0\0"
 
 #include <configs/stm32mp15_common.h>
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
index 05de376f0e6..af5da096b7d 100644
--- a/include/configs/stmark2.h
+++ b/include/configs/stmark2.h
@@ -95,6 +95,7 @@
 #define CACR_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
 					CFG_SYS_INIT_RAM_SIZE - 12)
 
-#define CFG_MCFTMR
+
+#define CFG_SYS_I2C_0
 
 #endif /* __STMARK2_CONFIG_H */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index d54c208ef66..149a74d98e8 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -55,7 +55,8 @@
 		"do;" \
 		"setenv overlaystring ${overlaystring}'#'${overlay};" \
 		"done;\0" \
-	"run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}\0" \
+	"get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}\0" \
+	"run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}\0" \
 
 /*
  * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
diff --git a/include/configs/whitehawk.h b/include/configs/whitehawk.h
new file mode 100644
index 00000000000..4b4cf635966
--- /dev/null
+++ b/include/configs/whitehawk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * include/configs/whitehawk.h
+ *     This file is White Hawk board configuration.
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __WHITEHAWK_H
+#define __WHITEHAWK_H
+
+#include "rcar-gen4-common.h"
+
+#endif /* __WHITEHAWK_H */
diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h
index 69cd012fc5a..1a20285d92d 100644
--- a/include/dm/platform_data/serial_sh.h
+++ b/include/dm/platform_data/serial_sh.h
@@ -17,6 +17,7 @@ enum sh_serial_type {
 	PORT_SCIF,
 	PORT_SCIFA,
 	PORT_SCIFB,
+	PORT_HSCIF,
 };
 
 /*
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 33e43c20db6..307ad6931ca 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
 	UCLASS_AUDIO_CODEC,	/* Audio codec with control and data path */
 	UCLASS_AXI,		/* AXI bus */
 	UCLASS_BLK,		/* Block device */
+	UCLASS_BLKMAP,		/* Composable virtual block device */
 	UCLASS_BOOTCOUNT,       /* Bootcount backing store */
 	UCLASS_BOOTDEV,		/* Boot device for locating an OS to boot */
 	UCLASS_BOOTMETH,	/* Bootmethod for booting an OS */
@@ -55,6 +56,7 @@ enum uclass_id {
 	UCLASS_EFI_MEDIA,	/* Devices provided by UEFI firmware */
 	UCLASS_ETH,		/* Ethernet device */
 	UCLASS_ETH_PHY,		/* Ethernet PHY device */
+	UCLASS_EXTCON,		/* External Connector Class */
 	UCLASS_FIRMWARE,	/* Firmware */
 	UCLASS_FPGA,		/* FPGA device */
 	UCLASS_FUZZING_ENGINE,	/* Fuzzing engine */
@@ -88,6 +90,7 @@ enum uclass_id {
 	UCLASS_NOP,		/* No-op devices */
 	UCLASS_NORTHBRIDGE,	/* Intel Northbridge / SDRAM controller */
 	UCLASS_NVME,		/* NVM Express device */
+	UCLASS_NVMXIP,		/* NVM XIP devices */
 	UCLASS_P2SB,		/* (x86) Primary-to-Sideband Bus */
 	UCLASS_PANEL,		/* Display panel, such as an LCD */
 	UCLASS_PANEL_BACKLIGHT,	/* Backlight controller for panel */
diff --git a/include/dm/uclass.h b/include/dm/uclass.h
index ee15c920633..456eef7f2f3 100644
--- a/include/dm/uclass.h
+++ b/include/dm/uclass.h
@@ -265,6 +265,23 @@ int uclass_get_device_by_ofnode(enum uclass_id id, ofnode node,
 				struct udevice **devp);
 
 /**
+ * uclass_get_device_by_of_path() - Get a uclass device by device tree path
+ *
+ * This searches the devices in the uclass for one attached to the
+ * device tree node corresponding to the given path (which may also be
+ * an alias).
+ *
+ * The device is probed to activate it ready for use.
+ *
+ * @id: ID to look up
+ * @path: Device tree path to search for (if no such path then -ENODEV is returned)
+ * @devp: Returns pointer to device (there is only one for each node)
+ * Return: 0 if OK, -ve on error
+ */
+int uclass_get_device_by_of_path(enum uclass_id id, const char *path,
+				 struct udevice **devp);
+
+/**
  * uclass_get_device_by_phandle_id() - Get a uclass device by phandle id
  *
  * This searches the devices in the uclass for one with the given phandle id.
diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h
new file mode 100644
index 00000000000..ad5827cde78
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-nsp.h
@@ -0,0 +1,51 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *	* Redistributions of source code must retain the above copyright
+ *	  notice, this list of conditions and the following disclaimer.
+ *	* Redistributions in binary form must reproduce the above copyright
+ *	  notice, this list of conditions and the following disclaimer in
+ *	  the documentation and/or other materials provided with the
+ *	  distribution.
+ *	* Neither the name of Broadcom Corporation nor the names of its
+ *	  contributors may be used to endorse or promote products derived
+ *	  from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL			0
+#define BCM_NSP_GENPLL_PHY_CLK		1
+#define BCM_NSP_GENPLL_ENET_SW_CLK	2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
+#define BCM_NSP_GENPLL_SATA1_CLK	5
+#define BCM_NSP_GENPLL_SATA2_CLK	6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0			0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
+#define BCM_NSP_LCPLL0_SDIO_CLK		2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
+
+#endif /* _CLOCK_BCM_NSP_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 136de24733b..8a05790d1a9 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -70,6 +70,18 @@
 #define HISTB_USB3_UTMI_CLK1		48
 #define HISTB_USB3_PIPE_CLK1		49
 #define HISTB_USB3_SUSPEND_CLK1		50
+#define HISTB_SDIO1_BIU_CLK		51
+#define HISTB_SDIO1_CIU_CLK		52
+#define HISTB_SDIO1_DRV_CLK		53
+#define HISTB_SDIO1_SAMPLE_CLK		54
+
+/* Hi3798MV200 specific clocks */
+
+// reuse clocks of histb
+#define HI3798MV200_GMAC_CLK		HISTB_ETH0_MAC_CLK
+#define HI3798MV200_GMACIF_CLK		HISTB_ETH0_MACIF_CLK
+#define HI3798MV200_FEMAC_CLK		HISTB_ETH1_MAC_CLK
+#define HI3798MV200_FEMACIF_CLK		HISTB_ETH1_MACIF_CLK
 
 /* clocks provided by mcu CRG */
 #define HISTB_MCE_CLK			1
diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
new file mode 100644
index 00000000000..f2ae1c6a82d
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779f0 CPG Core Clocks */
+
+#define R8A779F0_CLK_ZX			0
+#define R8A779F0_CLK_ZS			1
+#define R8A779F0_CLK_ZT			2
+#define R8A779F0_CLK_ZTR		3
+#define R8A779F0_CLK_S0D2		4
+#define R8A779F0_CLK_S0D3		5
+#define R8A779F0_CLK_S0D4		6
+#define R8A779F0_CLK_S0D2_MM		7
+#define R8A779F0_CLK_S0D3_MM		8
+#define R8A779F0_CLK_S0D4_MM		9
+#define R8A779F0_CLK_S0D2_RT		10
+#define R8A779F0_CLK_S0D3_RT		11
+#define R8A779F0_CLK_S0D4_RT		12
+#define R8A779F0_CLK_S0D6_RT		13
+#define R8A779F0_CLK_S0D3_PER		14
+#define R8A779F0_CLK_S0D6_PER		15
+#define R8A779F0_CLK_S0D12_PER		16
+#define R8A779F0_CLK_S0D24_PER		17
+#define R8A779F0_CLK_S0D2_HSC		18
+#define R8A779F0_CLK_S0D3_HSC		19
+#define R8A779F0_CLK_S0D4_HSC		20
+#define R8A779F0_CLK_S0D6_HSC		21
+#define R8A779F0_CLK_S0D12_HSC		22
+#define R8A779F0_CLK_S0D2_CC		23
+#define R8A779F0_CLK_CL			24
+#define R8A779F0_CLK_CL16M		25
+#define R8A779F0_CLK_CL16M_MM		26
+#define R8A779F0_CLK_CL16M_RT		27
+#define R8A779F0_CLK_CL16M_PER		28
+#define R8A779F0_CLK_CL16M_HSC		29
+#define R8A779F0_CLK_Z0			30
+#define R8A779F0_CLK_Z1			31
+#define R8A779F0_CLK_ZB3		32
+#define R8A779F0_CLK_ZB3D2		33
+#define R8A779F0_CLK_ZB3D4		34
+#define R8A779F0_CLK_SD0H		35
+#define R8A779F0_CLK_SD0		36
+#define R8A779F0_CLK_RPC		37
+#define R8A779F0_CLK_RPCD2		38
+#define R8A779F0_CLK_MSO		39
+#define R8A779F0_CLK_SASYNCRT		40
+#define R8A779F0_CLK_SASYNCPERD1	41
+#define R8A779F0_CLK_SASYNCPERD2	42
+#define R8A779F0_CLK_SASYNCPERD4	43
+#define R8A779F0_CLK_DBGSOC_HSC		44
+#define R8A779F0_CLK_RSW2		45
+#define R8A779F0_CLK_OSC		46
+#define R8A779F0_CLK_ZR			47
+#define R8A779F0_CLK_CPEX		48
+#define R8A779F0_CLK_CBFUSA		49
+#define R8A779F0_CLK_R			50
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
new file mode 100644
index 00000000000..754c54a6eb0
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779g0 CPG Core Clocks */
+
+#define R8A779G0_CLK_ZX			0
+#define R8A779G0_CLK_ZS			1
+#define R8A779G0_CLK_ZT			2
+#define R8A779G0_CLK_ZTR		3
+#define R8A779G0_CLK_S0D2		4
+#define R8A779G0_CLK_S0D3		5
+#define R8A779G0_CLK_S0D4		6
+#define R8A779G0_CLK_S0D1_VIO		7
+#define R8A779G0_CLK_S0D2_VIO		8
+#define R8A779G0_CLK_S0D4_VIO		9
+#define R8A779G0_CLK_S0D8_VIO		10
+#define R8A779G0_CLK_S0D1_VC		11
+#define R8A779G0_CLK_S0D2_VC		12
+#define R8A779G0_CLK_S0D4_VC		13
+#define R8A779G0_CLK_S0D2_MM		14
+#define R8A779G0_CLK_S0D4_MM		15
+#define R8A779G0_CLK_S0D2_U3DG		16
+#define R8A779G0_CLK_S0D4_U3DG		17
+#define R8A779G0_CLK_S0D2_RT		18
+#define R8A779G0_CLK_S0D3_RT		19
+#define R8A779G0_CLK_S0D4_RT		20
+#define R8A779G0_CLK_S0D6_RT		21
+#define R8A779G0_CLK_S0D24_RT		22
+#define R8A779G0_CLK_S0D2_PER		23
+#define R8A779G0_CLK_S0D3_PER		24
+#define R8A779G0_CLK_S0D4_PER		25
+#define R8A779G0_CLK_S0D6_PER		26
+#define R8A779G0_CLK_S0D12_PER		27
+#define R8A779G0_CLK_S0D24_PER		28
+#define R8A779G0_CLK_S0D1_HSC		29
+#define R8A779G0_CLK_S0D2_HSC		30
+#define R8A779G0_CLK_S0D4_HSC		31
+#define R8A779G0_CLK_S0D2_CC		32
+#define R8A779G0_CLK_SVD1_IR		33
+#define R8A779G0_CLK_SVD2_IR		34
+#define R8A779G0_CLK_SVD1_VIP		35
+#define R8A779G0_CLK_SVD2_VIP		36
+#define R8A779G0_CLK_CL			37
+#define R8A779G0_CLK_CL16M		38
+#define R8A779G0_CLK_CL16M_MM		39
+#define R8A779G0_CLK_CL16M_RT		40
+#define R8A779G0_CLK_CL16M_PER		41
+#define R8A779G0_CLK_CL16M_HSC		42
+#define R8A779G0_CLK_Z0			43
+#define R8A779G0_CLK_ZB3		44
+#define R8A779G0_CLK_ZB3D2		45
+#define R8A779G0_CLK_ZB3D4		46
+#define R8A779G0_CLK_ZG			47
+#define R8A779G0_CLK_SD0H		48
+#define R8A779G0_CLK_SD0		49
+#define R8A779G0_CLK_RPC		50
+#define R8A779G0_CLK_RPCD2		51
+#define R8A779G0_CLK_MSO		52
+#define R8A779G0_CLK_CANFD		53
+#define R8A779G0_CLK_CSI		54
+#define R8A779G0_CLK_FRAY		55
+#define R8A779G0_CLK_IPC		56
+#define R8A779G0_CLK_SASYNCRT		57
+#define R8A779G0_CLK_SASYNCPERD1	58
+#define R8A779G0_CLK_SASYNCPERD2	59
+#define R8A779G0_CLK_SASYNCPERD4	60
+#define R8A779G0_CLK_VIOBUS		61
+#define R8A779G0_CLK_VIOBUSD2		62
+#define R8A779G0_CLK_VCBUS		63
+#define R8A779G0_CLK_VCBUSD2		64
+#define R8A779G0_CLK_DSIEXT		65
+#define R8A779G0_CLK_DSIREF		66
+#define R8A779G0_CLK_ADGH		67
+#define R8A779G0_CLK_OSC		68
+#define R8A779G0_CLK_ZR0		69
+#define R8A779G0_CLK_ZR1		70
+#define R8A779G0_CLK_ZR2		71
+#define R8A779G0_CLK_IMPA		72
+#define R8A779G0_CLK_IMPAD4		73
+#define R8A779G0_CLK_CPEX		74
+#define R8A779G0_CLK_CBFUSA		75
+#define R8A779G0_CLK_R			76
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
new file mode 100644
index 00000000000..77b70e7a83b
--- /dev/null
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__
+
+#define JH7110_SYSCLK_CPU_ROOT			0
+#define JH7110_SYSCLK_CPU_CORE			1
+#define JH7110_SYSCLK_CPU_BUS			2
+#define JH7110_SYSCLK_GPU_ROOT			3
+#define JH7110_SYSCLK_PERH_ROOT		4
+#define JH7110_SYSCLK_BUS_ROOT			5
+#define JH7110_SYSCLK_NOCSTG_BUS		6
+#define JH7110_SYSCLK_AXI_CFG0			7
+#define JH7110_SYSCLK_STG_AXIAHB		8
+#define JH7110_SYSCLK_AHB0			9
+#define JH7110_SYSCLK_AHB1			10
+#define JH7110_SYSCLK_APB_BUS			11
+#define JH7110_SYSCLK_APB0			12
+#define JH7110_SYSCLK_PLL0_DIV2		13
+#define JH7110_SYSCLK_PLL1_DIV2		14
+#define JH7110_SYSCLK_PLL2_DIV2		15
+#define JH7110_SYSCLK_AUDIO_ROOT		16
+#define JH7110_SYSCLK_MCLK_INNER		17
+#define JH7110_SYSCLK_MCLK			18
+#define JH7110_SYSCLK_MCLK_OUT			19
+#define JH7110_SYSCLK_ISP_2X			20
+#define JH7110_SYSCLK_ISP_AXI			21
+#define JH7110_SYSCLK_GCLK0			22
+#define JH7110_SYSCLK_GCLK1			23
+#define JH7110_SYSCLK_GCLK2			24
+#define JH7110_SYSCLK_CORE			25
+#define JH7110_SYSCLK_CORE1			26
+#define JH7110_SYSCLK_CORE2			27
+#define JH7110_SYSCLK_CORE3			28
+#define JH7110_SYSCLK_CORE4			29
+#define JH7110_SYSCLK_DEBUG			30
+#define JH7110_SYSCLK_RTC_TOGGLE		31
+#define JH7110_SYSCLK_TRACE0			32
+#define JH7110_SYSCLK_TRACE1			33
+#define JH7110_SYSCLK_TRACE2			34
+#define JH7110_SYSCLK_TRACE3			35
+#define JH7110_SYSCLK_TRACE4			36
+#define JH7110_SYSCLK_TRACE_COM		37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI		38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI	39
+#define JH7110_SYSCLK_OSC_DIV2			40
+#define JH7110_SYSCLK_PLL1_DIV4		41
+#define JH7110_SYSCLK_PLL1_DIV8		42
+#define JH7110_SYSCLK_DDR_BUS			43
+#define JH7110_SYSCLK_DDR_AXI			44
+#define JH7110_SYSCLK_GPU_CORE			45
+#define JH7110_SYSCLK_GPU_CORE_CLK		46
+#define JH7110_SYSCLK_GPU_SYS_CLK		47
+#define JH7110_SYSCLK_GPU_APB			48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE		49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI		50
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X	51
+#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI	52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI		53
+#define JH7110_SYSCLK_HIFI4_CORE		54
+#define JH7110_SYSCLK_HIFI4_AXI		55
+#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN	56
+#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB		57
+#define JH7110_SYSCLK_VOUT_SRC			58
+#define JH7110_SYSCLK_VOUT_AXI			59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI		60
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB		61
+#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI		62
+#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK	63
+#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF		64
+#define JH7110_SYSCLK_JPEGC_AXI		65
+#define JH7110_SYSCLK_CODAJ12_AXI		66
+#define JH7110_SYSCLK_CODAJ12_CORE		67
+#define JH7110_SYSCLK_CODAJ12_APB		68
+#define JH7110_SYSCLK_VDEC_AXI			69
+#define JH7110_SYSCLK_WAVE511_AXI		70
+#define JH7110_SYSCLK_WAVE511_BPU		71
+#define JH7110_SYSCLK_WAVE511_VCE		72
+#define JH7110_SYSCLK_WAVE511_APB		73
+#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG		74
+#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN	75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI		76
+#define JH7110_SYSCLK_VENC_AXI			77
+#define JH7110_SYSCLK_WAVE420L_AXI		78
+#define JH7110_SYSCLK_WAVE420L_BPU		79
+#define JH7110_SYSCLK_WAVE420L_VCE		80
+#define JH7110_SYSCLK_WAVE420L_APB		81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI		82
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV	83
+#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN	84
+#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4	85
+#define JH7110_SYSCLK_AXIMEM2_AXI		86
+#define JH7110_SYSCLK_QSPI_AHB			87
+#define JH7110_SYSCLK_QSPI_APB			88
+#define JH7110_SYSCLK_QSPI_REF_SRC		89
+#define JH7110_SYSCLK_QSPI_REF			90
+#define JH7110_SYSCLK_SDIO0_AHB		91
+#define JH7110_SYSCLK_SDIO1_AHB		92
+#define JH7110_SYSCLK_SDIO0_SDCARD		93
+#define JH7110_SYSCLK_SDIO1_SDCARD		94
+#define JH7110_SYSCLK_USB_125M			95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI		96
+#define JH7110_SYSCLK_GMAC1_AHB		97
+#define JH7110_SYSCLK_GMAC1_AXI		98
+#define JH7110_SYSCLK_GMAC_SRC			99
+#define JH7110_SYSCLK_GMAC1_GTXCLK		100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX		101
+#define JH7110_SYSCLK_GMAC1_PTP		102
+#define JH7110_SYSCLK_GMAC1_RX			103
+#define JH7110_SYSCLK_GMAC1_RX_INV		104
+#define JH7110_SYSCLK_GMAC1_TX			105
+#define JH7110_SYSCLK_GMAC1_TX_INV		106
+#define JH7110_SYSCLK_GMAC1_GTXC		107
+#define JH7110_SYSCLK_GMAC0_GTXCLK		108
+#define JH7110_SYSCLK_GMAC0_PTP		109
+#define JH7110_SYSCLK_GMAC_PHY			110
+#define JH7110_SYSCLK_GMAC0_GTXC		111
+#define JH7110_SYSCLK_IOMUX_APB		112
+#define JH7110_SYSCLK_MAILBOX			113
+#define JH7110_SYSCLK_INT_CTRL_APB		114
+#define JH7110_SYSCLK_CAN0_APB			115
+#define JH7110_SYSCLK_CAN0_TIMER		116
+#define JH7110_SYSCLK_CAN0_CAN			117
+#define JH7110_SYSCLK_CAN1_APB			118
+#define JH7110_SYSCLK_CAN1_TIMER		119
+#define JH7110_SYSCLK_CAN1_CAN			120
+#define JH7110_SYSCLK_PWM_APB			121
+#define JH7110_SYSCLK_WDT_APB			122
+#define JH7110_SYSCLK_WDT_CORE			123
+#define JH7110_SYSCLK_TIMER_APB		124
+#define JH7110_SYSCLK_TIMER0			125
+#define JH7110_SYSCLK_TIMER1			126
+#define JH7110_SYSCLK_TIMER2			127
+#define JH7110_SYSCLK_TIMER3			128
+#define JH7110_SYSCLK_TEMP_APB			129
+#define JH7110_SYSCLK_TEMP_CORE		130
+#define JH7110_SYSCLK_SPI0_APB			131
+#define JH7110_SYSCLK_SPI1_APB			132
+#define JH7110_SYSCLK_SPI2_APB			133
+#define JH7110_SYSCLK_SPI3_APB			134
+#define JH7110_SYSCLK_SPI4_APB			135
+#define JH7110_SYSCLK_SPI5_APB			136
+#define JH7110_SYSCLK_SPI6_APB			137
+#define JH7110_SYSCLK_I2C0_APB			138
+#define JH7110_SYSCLK_I2C1_APB			139
+#define JH7110_SYSCLK_I2C2_APB			140
+#define JH7110_SYSCLK_I2C3_APB			141
+#define JH7110_SYSCLK_I2C4_APB			142
+#define JH7110_SYSCLK_I2C5_APB			143
+#define JH7110_SYSCLK_I2C6_APB			144
+#define JH7110_SYSCLK_UART0_APB		145
+#define JH7110_SYSCLK_UART0_CORE		146
+#define JH7110_SYSCLK_UART1_APB		147
+#define JH7110_SYSCLK_UART1_CORE		148
+#define JH7110_SYSCLK_UART2_APB		149
+#define JH7110_SYSCLK_UART2_CORE		150
+#define JH7110_SYSCLK_UART3_APB		151
+#define JH7110_SYSCLK_UART3_CORE		152
+#define JH7110_SYSCLK_UART4_APB		153
+#define JH7110_SYSCLK_UART4_CORE		154
+#define JH7110_SYSCLK_UART5_APB		155
+#define JH7110_SYSCLK_UART5_CORE		156
+#define JH7110_SYSCLK_PWMDAC_APB		157
+#define JH7110_SYSCLK_PWMDAC_CORE		158
+#define JH7110_SYSCLK_SPDIF_APB		159
+#define JH7110_SYSCLK_SPDIF_CORE		160
+#define JH7110_SYSCLK_I2STX0_APB		161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST		162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV	163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST		164
+#define JH7110_SYSCLK_I2STX0_BCLK		165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV		166
+#define JH7110_SYSCLK_I2STX0_LRCK		167
+#define JH7110_SYSCLK_I2STX1_APB		168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST		169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV	170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST		171
+#define JH7110_SYSCLK_I2STX1_BCLK		172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV		173
+#define JH7110_SYSCLK_I2STX1_LRCK		174
+#define JH7110_SYSCLK_I2SRX_APB		175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST		176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV	177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST		178
+#define JH7110_SYSCLK_I2SRX_BCLK		179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV		180
+#define JH7110_SYSCLK_I2SRX_LRCK		181
+#define JH7110_SYSCLK_PDM_DMIC			182
+#define JH7110_SYSCLK_PDM_APB			183
+#define JH7110_SYSCLK_TDM_AHB			184
+#define JH7110_SYSCLK_TDM_APB			185
+#define JH7110_SYSCLK_TDM_INTERNAL		186
+#define JH7110_SYSCLK_TDM_CLK_TDM		187
+#define JH7110_SYSCLK_TDM_CLK_TDM_N		188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG	189
+
+#define JH7110_SYSCLK_PLL0_OUT			190
+#define JH7110_SYSCLK_PLL1_OUT			191
+#define JH7110_SYSCLK_PLL2_OUT			192
+
+#define JH7110_SYSCLK_END			193
+
+#define JH7110_AONCLK_OSC_DIV4		(JH7110_SYSCLK_END + 0)
+#define JH7110_AONCLK_APB_FUNC		(JH7110_SYSCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_AHB	(JH7110_SYSCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_AXI	(JH7110_SYSCLK_END + 3)
+#define JH7110_AONCLK_GMAC0_RMII_RTX	(JH7110_SYSCLK_END + 4)
+#define JH7110_AONCLK_GMAC0_TX		(JH7110_SYSCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_TX_INV	(JH7110_SYSCLK_END + 6)
+#define JH7110_AONCLK_GMAC0_RX		(JH7110_SYSCLK_END + 7)
+#define JH7110_AONCLK_GMAC0_RX_INV	(JH7110_SYSCLK_END + 8)
+#define JH7110_AONCLK_OTPC_APB		(JH7110_SYSCLK_END  + 9)
+#define JH7110_AONCLK_RTC_APB		(JH7110_SYSCLK_END + 10)
+#define JH7110_AONCLK_RTC_INTERNAL	(JH7110_SYSCLK_END + 11)
+#define JH7110_AONCLK_RTC_32K		(JH7110_SYSCLK_END + 12)
+#define JH7110_AONCLK_RTC_CAL		(JH7110_SYSCLK_END + 13)
+
+#define JH7110_AONCLK_END		(JH7110_SYSCLK_END + 14)
+
+#define JH7110_STGCLK_HIFI4_CORE	(JH7110_AONCLK_END + 0)
+#define JH7110_STGCLK_USB_APB		(JH7110_AONCLK_END + 1)
+#define JH7110_STGCLK_USB_UTMI_APB	(JH7110_AONCLK_END + 2)
+#define JH7110_STGCLK_USB_AXI		(JH7110_AONCLK_END + 3)
+#define JH7110_STGCLK_USB_LPM		(JH7110_AONCLK_END + 4)
+#define JH7110_STGCLK_USB_STB		(JH7110_AONCLK_END + 5)
+#define JH7110_STGCLK_USB_APP_125	(JH7110_AONCLK_END + 6)
+#define JH7110_STGCLK_USB_REFCLK	(JH7110_AONCLK_END + 7)
+#define JH7110_STGCLK_PCIE0_AXI	(JH7110_AONCLK_END + 8)
+#define JH7110_STGCLK_PCIE0_APB	(JH7110_AONCLK_END + 9)
+#define JH7110_STGCLK_PCIE0_TL		(JH7110_AONCLK_END + 10)
+#define JH7110_STGCLK_PCIE1_AXI	(JH7110_AONCLK_END + 11)
+#define JH7110_STGCLK_PCIE1_APB	(JH7110_AONCLK_END + 12)
+#define JH7110_STGCLK_PCIE1_TL		(JH7110_AONCLK_END + 13)
+#define JH7110_STGCLK_PCIE01_MAIN	(JH7110_AONCLK_END + 14)
+#define JH7110_STGCLK_SEC_HCLK		(JH7110_AONCLK_END + 15)
+#define JH7110_STGCLK_SEC_MISCAHB	(JH7110_AONCLK_END + 16)
+#define JH7110_STGCLK_MTRX_GRP0_MAIN	(JH7110_AONCLK_END + 17)
+#define JH7110_STGCLK_MTRX_GRP0_BUS	(JH7110_AONCLK_END + 18)
+#define JH7110_STGCLK_MTRX_GRP0_STG	(JH7110_AONCLK_END + 19)
+#define JH7110_STGCLK_MTRX_GRP1_MAIN	(JH7110_AONCLK_END + 20)
+#define JH7110_STGCLK_MTRX_GRP1_BUS	(JH7110_AONCLK_END + 21)
+#define JH7110_STGCLK_MTRX_GRP1_STG	(JH7110_AONCLK_END + 22)
+#define JH7110_STGCLK_MTRX_GRP1_HIFI	(JH7110_AONCLK_END + 23)
+#define JH7110_STGCLK_E2_RTC		(JH7110_AONCLK_END + 24)
+#define JH7110_STGCLK_E2_CORE		(JH7110_AONCLK_END + 25)
+#define JH7110_STGCLK_E2_DBG		(JH7110_AONCLK_END + 26)
+#define JH7110_STGCLK_DMA1P_AXI	(JH7110_AONCLK_END + 27)
+#define JH7110_STGCLK_DMA1P_AHB	(JH7110_AONCLK_END + 28)
+
+#define JH7110_STGCLK_END		(JH7110_AONCLK_END + 29)
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */
diff --git a/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
new file mode 100644
index 00000000000..f273547e7b1
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-starfive-jh7110.h
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_PINCTRL_STARFIVE_JH7110_H__
+
+/*
+ * mux bits:
+ *  | 31 - 24 | 23 - 16 | 15 - 10 |  9 - 8   |  7 - 0  |
+ *  |  din    |  dout   |  doen   | function | gpio nr |
+ *
+ * dout:     output signal
+ * doen:     output enable signal
+ * din:      optional input signal, 0xff = none
+ * function:
+ * gpio nr:  gpio number, 0 - 63
+ */
+#define GPIOMUX(n, dout, doen, din) ( \
+		(((din)  & 0xff) << 24) | \
+		(((dout) & 0xff) << 16) | \
+		(((doen) & 0x3f) << 10) | \
+		((n) & 0x3f))
+
+#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
+
+/* sys_iomux pin */
+#define	PAD_GPIO0	 0
+#define	PAD_GPIO1	 1
+#define	PAD_GPIO2	 2
+#define	PAD_GPIO3	 3
+#define	PAD_GPIO4	 4
+#define	PAD_GPIO5	 5
+#define	PAD_GPIO6	 6
+#define	PAD_GPIO7	 7
+#define	PAD_GPIO8	 8
+#define	PAD_GPIO9	 9
+#define	PAD_GPIO10	10
+#define	PAD_GPIO11	11
+#define	PAD_GPIO12	12
+#define	PAD_GPIO13	13
+#define	PAD_GPIO14	14
+#define	PAD_GPIO15	15
+#define	PAD_GPIO16	16
+#define	PAD_GPIO17	17
+#define	PAD_GPIO18	18
+#define	PAD_GPIO19	19
+#define	PAD_GPIO20	20
+#define	PAD_GPIO21	21
+#define	PAD_GPIO22	22
+#define	PAD_GPIO23	23
+#define	PAD_GPIO24	24
+#define	PAD_GPIO25	25
+#define	PAD_GPIO26	26
+#define	PAD_GPIO27	27
+#define	PAD_GPIO28	28
+#define	PAD_GPIO29	29
+#define	PAD_GPIO30	30
+#define	PAD_GPIO31	31
+#define	PAD_GPIO32	32
+#define	PAD_GPIO33	33
+#define	PAD_GPIO34	34
+#define	PAD_GPIO35	35
+#define	PAD_GPIO36	36
+#define	PAD_GPIO37	37
+#define	PAD_GPIO38	38
+#define	PAD_GPIO39	39
+#define	PAD_GPIO40	40
+#define	PAD_GPIO41	41
+#define	PAD_GPIO42	42
+#define	PAD_GPIO43	43
+#define	PAD_GPIO44	44
+#define	PAD_GPIO45	45
+#define	PAD_GPIO46	46
+#define	PAD_GPIO47	47
+#define	PAD_GPIO48	48
+#define	PAD_GPIO49	49
+#define	PAD_GPIO50	50
+#define	PAD_GPIO51	51
+#define	PAD_GPIO52	52
+#define	PAD_GPIO53	53
+#define	PAD_GPIO54	54
+#define	PAD_GPIO55	55
+#define	PAD_GPIO56	56
+#define	PAD_GPIO57	57
+#define	PAD_GPIO58	58
+#define	PAD_GPIO59	59
+#define	PAD_GPIO60	60
+#define	PAD_GPIO61	61
+#define	PAD_GPIO62	62
+#define	PAD_GPIO63	63
+#define	PAD_SD0_CLK	64
+#define	PAD_SD0_CMD	65
+#define	PAD_SD0_DATA0	66
+#define	PAD_SD0_DATA1	67
+#define	PAD_SD0_DATA2	68
+#define	PAD_SD0_DATA3	69
+#define	PAD_SD0_DATA4	70
+#define	PAD_SD0_DATA5	71
+#define	PAD_SD0_DATA6	72
+#define	PAD_SD0_DATA7	73
+#define	PAD_SD0_STRB	74
+#define	PAD_GMAC1_MDC	75
+#define	PAD_GMAC1_MDIO	76
+#define	PAD_GMAC1_RXD0	77
+#define	PAD_GMAC1_RXD1	78
+#define	PAD_GMAC1_RXD2	79
+#define	PAD_GMAC1_RXD3	80
+#define	PAD_GMAC1_RXDV	81
+#define	PAD_GMAC1_RXC	82
+#define	PAD_GMAC1_TXD0	83
+#define	PAD_GMAC1_TXD1	84
+#define	PAD_GMAC1_TXD2	85
+#define	PAD_GMAC1_TXD3	86
+#define	PAD_GMAC1_TXEN	87
+#define	PAD_GMAC1_TXC	88
+#define	PAD_QSPI_SCLK	89
+#define	PAD_QSPI_CS0	90
+#define	PAD_QSPI_DATA0	91
+#define	PAD_QSPI_DATA1	92
+#define	PAD_QSPI_DATA2	93
+#define	PAD_QSPI_DATA3	94
+
+/* aon_iomux pin */
+#define	PAD_TESTEN	0
+#define	PAD_RGPIO0	1
+#define	PAD_RGPIO1	2
+#define	PAD_RGPIO2	3
+#define	PAD_RGPIO3	4
+#define	PAD_RSTN	5
+#define	PAD_GMAC0_MDC	6
+#define	PAD_GMAC0_MDIO	7
+#define	PAD_GMAC0_RXD0	8
+#define	PAD_GMAC0_RXD1	9
+#define	PAD_GMAC0_RXD2	10
+#define	PAD_GMAC0_RXD3	11
+#define	PAD_GMAC0_RXDV	12
+#define	PAD_GMAC0_RXC	13
+#define	PAD_GMAC0_TXD0	14
+#define	PAD_GMAC0_TXD1	15
+#define	PAD_GMAC0_TXD2	16
+#define	PAD_GMAC0_TXD3	17
+#define	PAD_GMAC0_TXEN	18
+#define	PAD_GMAC0_TXC	19
+
+/* sys_iomux dout */
+#define GPOUT_LOW				  0
+#define GPOUT_HIGH				  1
+#define GPOUT_SYS_WAVE511_UART_TX		  2
+#define GPOUT_SYS_CAN0_STBY			  3
+#define GPOUT_SYS_CAN0_TST_NEXT_BIT		  4
+#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT	  5
+#define GPOUT_SYS_CAN0_TXD			  6
+#define GPOUT_SYS_USB_DRIVE_VBUS		  7
+#define GPOUT_SYS_QSPI_CS1			  8
+#define GPOUT_SYS_SPDIF			 9
+#define GPOUT_SYS_HDMI_CEC_SDA			 10
+#define GPOUT_SYS_HDMI_DDC_SCL			 11
+#define GPOUT_SYS_HDMI_DDC_SDA			 12
+#define GPOUT_SYS_WATCHDOG			 13
+#define GPOUT_SYS_I2C0_CLK			 14
+#define GPOUT_SYS_I2C0_DATA			 15
+#define GPOUT_SYS_SDIO0_BACK_END_POWER		 16
+#define GPOUT_SYS_SDIO0_CARD_POWER_EN		 17
+#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN	 18
+#define GPOUT_SYS_SDIO0_RST			 19
+#define GPOUT_SYS_UART0_TX			 20
+#define GPOUT_SYS_HIFI4_JTAG_TDO		 21
+#define GPOUT_SYS_JTAG_TDO			 22
+#define GPOUT_SYS_PDM_MCLK			 23
+#define GPOUT_SYS_PWM_CHANNEL0			 24
+#define GPOUT_SYS_PWM_CHANNEL1			 25
+#define GPOUT_SYS_PWM_CHANNEL2			 26
+#define GPOUT_SYS_PWM_CHANNEL3			 27
+#define GPOUT_SYS_PWMDAC_LEFT			 28
+#define GPOUT_SYS_PWMDAC_RIGHT			 29
+#define GPOUT_SYS_SPI0_CLK			 30
+#define GPOUT_SYS_SPI0_FSS			 31
+#define GPOUT_SYS_SPI0_TXD			 32
+#define GPOUT_SYS_GMAC_PHYCLK			 33
+#define GPOUT_SYS_I2SRX_BCLK			 34
+#define GPOUT_SYS_I2SRX_LRCK			 35
+#define GPOUT_SYS_I2STX0_BCLK			 36
+#define GPOUT_SYS_I2STX0_LRCK			 37
+#define GPOUT_SYS_MCLK				 38
+#define GPOUT_SYS_TDM_CLK			 39
+#define GPOUT_SYS_TDM_SYNC			 40
+#define GPOUT_SYS_TDM_TXD			 41
+#define GPOUT_SYS_TRACE_DATA0			 42
+#define GPOUT_SYS_TRACE_DATA1			 43
+#define GPOUT_SYS_TRACE_DATA2			 44
+#define GPOUT_SYS_TRACE_DATA3			 45
+#define GPOUT_SYS_TRACE_REF			 46
+#define GPOUT_SYS_CAN1_STBY			 47
+#define GPOUT_SYS_CAN1_TST_NEXT_BIT		 48
+#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT	 49
+#define GPOUT_SYS_CAN1_TXD			 50
+#define GPOUT_SYS_I2C1_CLK			 51
+#define GPOUT_SYS_I2C1_DATA			 52
+#define GPOUT_SYS_SDIO1_BACK_END_POWER		 53
+#define GPOUT_SYS_SDIO1_CARD_POWER_EN		 54
+#define GPOUT_SYS_SDIO1_CLK			 55
+#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN	 56
+#define GPOUT_SYS_SDIO1_CMD			 57
+#define GPOUT_SYS_SDIO1_DATA0			 58
+#define GPOUT_SYS_SDIO1_DATA1			 59
+#define GPOUT_SYS_SDIO1_DATA2			 60
+#define GPOUT_SYS_SDIO1_DATA3			 61
+#define GPOUT_SYS_SDIO1_DATA4			 63
+#define GPOUT_SYS_SDIO1_DATA5			 63
+#define GPOUT_SYS_SDIO1_DATA6			 64
+#define GPOUT_SYS_SDIO1_DATA7			 65
+#define GPOUT_SYS_SDIO1_RST			 66
+#define GPOUT_SYS_UART1_RTS			 67
+#define GPOUT_SYS_UART1_TX			 68
+#define GPOUT_SYS_I2STX1_SDO0			 69
+#define GPOUT_SYS_I2STX1_SDO1			 70
+#define GPOUT_SYS_I2STX1_SDO2			 71
+#define GPOUT_SYS_I2STX1_SDO3			 72
+#define GPOUT_SYS_SPI1_CLK			 73
+#define GPOUT_SYS_SPI1_FSS			 74
+#define GPOUT_SYS_SPI1_TXD			 75
+#define GPOUT_SYS_I2C2_CLK			 76
+#define GPOUT_SYS_I2C2_DATA			 77
+#define GPOUT_SYS_UART2_RTS			 78
+#define GPOUT_SYS_UART2_TX			 79
+#define GPOUT_SYS_SPI2_CLK			 80
+#define GPOUT_SYS_SPI2_FSS			 81
+#define GPOUT_SYS_SPI2_TXD			 82
+#define GPOUT_SYS_I2C3_CLK			 83
+#define GPOUT_SYS_I2C3_DATA			 84
+#define GPOUT_SYS_UART3_TX			 85
+#define GPOUT_SYS_SPI3_CLK			 86
+#define GPOUT_SYS_SPI3_FSS			 87
+#define GPOUT_SYS_SPI3_TXD			 88
+#define GPOUT_SYS_I2C4_CLK			 89
+#define GPOUT_SYS_I2C4_DATA			 90
+#define GPOUT_SYS_UART4_RTS			 91
+#define GPOUT_SYS_UART4_TX			 92
+#define GPOUT_SYS_SPI4_CLK			 93
+#define GPOUT_SYS_SPI4_FSS			 94
+#define GPOUT_SYS_SPI4_TXD			 95
+#define GPOUT_SYS_I2C5_CLK			 96
+#define GPOUT_SYS_I2C5_DATA			 97
+#define GPOUT_SYS_UART5_RTS			 98
+#define GPOUT_SYS_UART5_TX			 99
+#define GPOUT_SYS_SPI5_CLK			100
+#define GPOUT_SYS_SPI5_FSS			101
+#define GPOUT_SYS_SPI5_TXD			102
+#define GPOUT_SYS_I2C6_CLK			103
+#define GPOUT_SYS_I2C6_DATA			104
+#define GPOUT_SYS_SPI6_CLK			105
+#define GPOUT_SYS_SPI6_FSS			106
+#define GPOUT_SYS_SPI6_TXD			107
+
+/* aon_iomux dout */
+#define GPOUT_AON_CLK_32K_OUT			2
+#define GPOUT_AON_PTC0_PWM4			3
+#define GPOUT_AON_PTC0_PWM5			4
+#define GPOUT_AON_PTC0_PWM6			5
+#define GPOUT_AON_PTC0_PWM7			6
+#define GPOUT_AON_CLK_GCLK0			7
+#define GPOUT_AON_CLK_GCLK1			8
+#define GPOUT_AON_CLK_GCLK2			9
+
+/* sys_iomux doen */
+#define GPOEN_ENABLE				 0
+#define GPOEN_DISABLE				 1
+#define GPOEN_SYS_HDMI_CEC_SDA			 2
+#define GPOEN_SYS_HDMI_DDC_SCL			 3
+#define GPOEN_SYS_HDMI_DDC_SDA			 4
+#define GPOEN_SYS_I2C0_CLK			 5
+#define GPOEN_SYS_I2C0_DATA			 6
+#define GPOEN_SYS_HIFI4_JTAG_TDO		 7
+#define GPOEN_SYS_JTAG_TDO			 8
+#define GPOEN_SYS_PWM0_CHANNEL0		9
+#define GPOEN_SYS_PWM0_CHANNEL1		10
+#define GPOEN_SYS_PWM0_CHANNEL2		11
+#define GPOEN_SYS_PWM0_CHANNEL3		12
+#define GPOEN_SYS_SPI0_NSSPCTL			13
+#define GPOEN_SYS_SPI0_NSSP			14
+#define GPOEN_SYS_TDM_SYNC			15
+#define GPOEN_SYS_TDM_TXD			16
+#define GPOEN_SYS_I2C1_CLK			17
+#define GPOEN_SYS_I2C1_DATA			18
+#define GPOEN_SYS_SDIO1_CMD			19
+#define GPOEN_SYS_SDIO1_DATA0			20
+#define GPOEN_SYS_SDIO1_DATA1			21
+#define GPOEN_SYS_SDIO1_DATA2			22
+#define GPOEN_SYS_SDIO1_DATA3			23
+#define GPOEN_SYS_SDIO1_DATA4			24
+#define GPOEN_SYS_SDIO1_DATA5			25
+#define GPOEN_SYS_SDIO1_DATA6			26
+#define GPOEN_SYS_SDIO1_DATA7			27
+#define GPOEN_SYS_SPI1_NSSPCTL			28
+#define GPOEN_SYS_SPI1_NSSP			29
+#define GPOEN_SYS_I2C2_CLK			30
+#define GPOEN_SYS_I2C2_DATA			31
+#define GPOEN_SYS_SPI2_NSSPCTL			32
+#define GPOEN_SYS_SPI2_NSSP			33
+#define GPOEN_SYS_I2C3_CLK			34
+#define GPOEN_SYS_I2C3_DATA			35
+#define GPOEN_SYS_SPI3_NSSPCTL			36
+#define GPOEN_SYS_SPI3_NSSP			37
+#define GPOEN_SYS_I2C4_CLK			38
+#define GPOEN_SYS_I2C4_DATA			39
+#define GPOEN_SYS_SPI4_NSSPCTL			40
+#define GPOEN_SYS_SPI4_NSSP			41
+#define GPOEN_SYS_I2C5_CLK			42
+#define GPOEN_SYS_I2C5_DATA			43
+#define GPOEN_SYS_SPI5_NSSPCTL			44
+#define GPOEN_SYS_SPI5_NSSP			45
+#define GPOEN_SYS_I2C6_CLK			46
+#define GPOEN_SYS_I2C6_DATA			47
+#define GPOEN_SYS_SPI6_NSSPCTL			48
+#define GPOEN_SYS_SPI6_NSSP			49
+
+/* aon_iomux doen */
+#define GPOEN_AON_PTC0_OE_N_4			2
+#define GPOEN_AON_PTC0_OE_N_5			3
+#define GPOEN_AON_PTC0_OE_N_6			4
+#define GPOEN_AON_PTC0_OE_N_7			5
+
+/* sys_iomux gin */
+#define GPI_NONE				255
+
+#define GPI_SYS_WAVE511_UART_RX		 0
+#define GPI_SYS_CAN0_RXD			 1
+#define GPI_SYS_USB_OVERCURRENT		 2
+#define GPI_SYS_SPDIF				 3
+#define GPI_SYS_JTAG_RST			 4
+#define GPI_SYS_HDMI_CEC_SDA			 5
+#define GPI_SYS_HDMI_DDC_SCL			 6
+#define GPI_SYS_HDMI_DDC_SDA			 7
+#define GPI_SYS_HDMI_HPD			 8
+#define GPI_SYS_I2C0_CLK			 9
+#define GPI_SYS_I2C0_DATA			10
+#define GPI_SYS_SDIO0_CD			11
+#define GPI_SYS_SDIO0_INT			12
+#define GPI_SYS_SDIO0_WP			13
+#define GPI_SYS_UART0_RX			14
+#define GPI_SYS_HIFI4_JTAG_TCK			15
+#define GPI_SYS_HIFI4_JTAG_TDI			16
+#define GPI_SYS_HIFI4_JTAG_TMS			17
+#define GPI_SYS_HIFI4_JTAG_RST			18
+#define GPI_SYS_JTAG_TDI			19
+#define GPI_SYS_JTAG_TMS			20
+#define GPI_SYS_PDM_DMIC0			21
+#define GPI_SYS_PDM_DMIC1			22
+#define GPI_SYS_I2SRX_SDIN0			23
+#define GPI_SYS_I2SRX_SDIN1			24
+#define GPI_SYS_I2SRX_SDIN2			25
+#define GPI_SYS_SPI0_CLK			26
+#define GPI_SYS_SPI0_FSS			27
+#define GPI_SYS_SPI0_RXD			28
+#define GPI_SYS_JTAG_TCK			29
+#define GPI_SYS_MCLK_EXT			30
+#define GPI_SYS_I2SRX_BCLK			31
+#define GPI_SYS_I2SRX_LRCK			32
+#define GPI_SYS_I2STX0_BCLK			33
+#define GPI_SYS_I2STX0_LRCK			34
+#define GPI_SYS_TDM_CLK			35
+#define GPI_SYS_TDM_RXD			36
+#define GPI_SYS_TDM_SYNC			37
+#define GPI_SYS_CAN1_RXD			38
+#define GPI_SYS_I2C1_CLK			39
+#define GPI_SYS_I2C1_DATA			40
+#define GPI_SYS_SDIO1_CD			41
+#define GPI_SYS_SDIO1_INT			42
+#define GPI_SYS_SDIO1_WP			43
+#define GPI_SYS_SDIO1_CMD			44
+#define GPI_SYS_SDIO1_DATA0			45
+#define GPI_SYS_SDIO1_DATA1			46
+#define GPI_SYS_SDIO1_DATA2			47
+#define GPI_SYS_SDIO1_DATA3			48
+#define GPI_SYS_SDIO1_DATA4			49
+#define GPI_SYS_SDIO1_DATA5			50
+#define GPI_SYS_SDIO1_DATA6			51
+#define GPI_SYS_SDIO1_DATA7			52
+#define GPI_SYS_SDIO1_STRB			53
+#define GPI_SYS_UART1_CTS			54
+#define GPI_SYS_UART1_RX			55
+#define GPI_SYS_SPI1_CLK			56
+#define GPI_SYS_SPI1_FSS			57
+#define GPI_SYS_SPI1_RXD			58
+#define GPI_SYS_I2C2_CLK			59
+#define GPI_SYS_I2C2_DATA			60
+#define GPI_SYS_UART2_CTS			61
+#define GPI_SYS_UART2_RX			62
+#define GPI_SYS_SPI2_CLK			63
+#define GPI_SYS_SPI2_FSS			64
+#define GPI_SYS_SPI2_RXD			65
+#define GPI_SYS_I2C3_CLK			66
+#define GPI_SYS_I2C3_DATA			67
+#define GPI_SYS_UART3_RX			68
+#define GPI_SYS_SPI3_CLK			69
+#define GPI_SYS_SPI3_FSS			70
+#define GPI_SYS_SPI3_RXD			71
+#define GPI_SYS_I2C4_CLK			72
+#define GPI_SYS_I2C4_DATA			73
+#define GPI_SYS_UART4_CTS			74
+#define GPI_SYS_UART4_RX			75
+#define GPI_SYS_SPI4_CLK			76
+#define GPI_SYS_SPI4_FSS			77
+#define GPI_SYS_SPI4_RXD			78
+#define GPI_SYS_I2C5_CLK			79
+#define GPI_SYS_I2C5_DATA			80
+#define GPI_SYS_UART5_CTS			81
+#define GPI_SYS_UART5_RX			82
+#define GPI_SYS_SPI5_CLK			83
+#define GPI_SYS_SPI5_FSS			84
+#define GPI_SYS_SPI5_RXD			85
+#define GPI_SYS_I2C6_CLK			86
+#define GPI_SYS_I2C6_DATA			87
+#define GPI_SYS_SPI6_CLK			88
+#define GPI_SYS_SPI6_FSS			89
+#define GPI_SYS_SPI6_RXD			90
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0		0
+#define GPI_AON_PMU_GPIO_WAKEUP_1		1
+#define GPI_AON_PMU_GPIO_WAKEUP_2		2
+#define GPI_AON_PMU_GPIO_WAKEUP_3		3
+
+#endif
diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h
new file mode 100644
index 00000000000..0ec8ad727ed
--- /dev/null
+++ b/include/dt-bindings/power/r8a779f0-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/*
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779F0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779F0_PD_A1E0D0C0		0
+#define R8A779F0_PD_A1E0D0C1		1
+#define R8A779F0_PD_A1E0D1C0		2
+#define R8A779F0_PD_A1E0D1C1		3
+#define R8A779F0_PD_A1E1D0C0		4
+#define R8A779F0_PD_A1E1D0C1		5
+#define R8A779F0_PD_A1E1D1C0		6
+#define R8A779F0_PD_A1E1D1C1		7
+#define R8A779F0_PD_A2E0D0		16
+#define R8A779F0_PD_A2E0D1		17
+#define R8A779F0_PD_A2E1D0		18
+#define R8A779F0_PD_A2E1D1		19
+#define R8A779F0_PD_A3E0		20
+#define R8A779F0_PD_A3E1		21
+
+/* Always-on power area */
+#define R8A779F0_PD_ALWAYS_ON		64
+
+#endif /* __DT_BINDINGS_POWER_R8A779A0_SYSC_H__*/
diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h
new file mode 100644
index 00000000000..c7b139fb075
--- /dev/null
+++ b/include/dt-bindings/power/r8a779g0-sysc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
+
+/*
+ * These power domain indices match the Power Domain Register Numbers (PDR)
+ */
+
+#define R8A779G0_PD_A1E0D0C0		0
+#define R8A779G0_PD_A1E0D0C1		1
+#define R8A779G0_PD_A1E0D1C0		2
+#define R8A779G0_PD_A1E0D1C1		3
+#define R8A779G0_PD_A2E0D0		16
+#define R8A779G0_PD_A2E0D1		17
+#define R8A779G0_PD_A3E0		20
+#define R8A779G0_PD_A33DGA		24
+#define R8A779G0_PD_A23DGB		25
+#define R8A779G0_PD_A1DSP0		33
+#define R8A779G0_PD_A2IMP01		34
+#define R8A779G0_PD_A2PSC		35
+#define R8A779G0_PD_A2CV0		36
+#define R8A779G0_PD_A2CV1		37
+#define R8A779G0_PD_A1CNN0		41
+#define R8A779G0_PD_A2CN0		42
+#define R8A779G0_PD_A3IR		43
+#define R8A779G0_PD_A1DSP1		45
+#define R8A779G0_PD_A2IMP23		46
+#define R8A779G0_PD_A2DMA		47
+#define R8A779G0_PD_A2CV2		48
+#define R8A779G0_PD_A2CV3		49
+#define R8A779G0_PD_A1DSP2		53
+#define R8A779G0_PD_A1DSP3		54
+#define R8A779G0_PD_A3VIP0		56
+#define R8A779G0_PD_A3VIP1		57
+#define R8A779G0_PD_A3VIP2		58
+#define R8A779G0_PD_A3ISP0		60
+#define R8A779G0_PD_A3ISP1		61
+#define R8A779G0_PD_A3DUL		62
+
+/* Always-on power area */
+#define R8A779G0_PD_ALWAYS_ON		64
+
+#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
new file mode 100644
index 00000000000..1d596581da7
--- /dev/null
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author: Yanhong Wang <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
+
+/* SYSCRG resets */
+#define JH7110_SYSRST_JTAG2APB			0
+#define JH7110_SYSRST_SYSCON			1
+#define JH7110_SYSRST_IOMUX_APB		2
+#define JH7110_SYSRST_BUS			3
+#define JH7110_SYSRST_DEBUG			4
+#define JH7110_SYSRST_CORE0			5
+#define JH7110_SYSRST_CORE1			6
+#define JH7110_SYSRST_CORE2			7
+#define JH7110_SYSRST_CORE3			8
+#define JH7110_SYSRST_CORE4			9
+#define JH7110_SYSRST_CORE0_ST			10
+#define JH7110_SYSRST_CORE1_ST			11
+#define JH7110_SYSRST_CORE2_ST			12
+#define JH7110_SYSRST_CORE3_ST			13
+#define JH7110_SYSRST_CORE4_ST			14
+#define JH7110_SYSRST_TRACE0			15
+#define JH7110_SYSRST_TRACE1			16
+#define JH7110_SYSRST_TRACE2			17
+#define JH7110_SYSRST_TRACE3			18
+#define JH7110_SYSRST_TRACE4			19
+#define JH7110_SYSRST_TRACE_COM		20
+#define JH7110_SYSRST_GPU_APB			21
+#define JH7110_SYSRST_GPU_DOMA			22
+#define JH7110_SYSRST_NOC_BUS_APB_BUS		23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI	24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI		25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI		26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI		27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI		28
+#define JH7110_SYSRST_NOC_BUS_DDRC		29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI		30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI		31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI		32
+#define JH7110_SYSRST_AXI_CFG1_DEC_AHB		33
+#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN	34
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN	35
+#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV	36
+#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4	37
+#define JH7110_SYSRST_DDR_AXI			38
+#define JH7110_SYSRST_DDR_OSC			39
+#define JH7110_SYSRST_DDR_APB			40
+#define JH7110_SYSRST_DOM_ISP_TOP_N		41
+#define JH7110_SYSRST_DOM_ISP_TOP_AXI		42
+#define JH7110_SYSRST_DOM_VOUT_TOP_SRC		43
+#define JH7110_SYSRST_CODAJ12_AXI		44
+#define JH7110_SYSRST_CODAJ12_CORE		45
+#define JH7110_SYSRST_CODAJ12_APB		46
+#define JH7110_SYSRST_WAVE511_AXI		47
+#define JH7110_SYSRST_WAVE511_BPU		48
+#define JH7110_SYSRST_WAVE511_VCE		49
+#define JH7110_SYSRST_WAVE511_APB		50
+#define JH7110_SYSRST_VDEC_JPG_ARB_JPG		51
+#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN	52
+#define JH7110_SYSRST_AXIMEM0_AXI		53
+#define JH7110_SYSRST_WAVE420L_AXI		54
+#define JH7110_SYSRST_WAVE420L_BPU		55
+#define JH7110_SYSRST_WAVE420L_VCE		56
+#define JH7110_SYSRST_WAVE420L_APB		57
+#define JH7110_SYSRST_AXIMEM1_AXI		58
+#define JH7110_SYSRST_AXIMEM2_AXI		59
+#define JH7110_SYSRST_INTMEM			60
+#define JH7110_SYSRST_QSPI_AHB			61
+#define JH7110_SYSRST_QSPI_APB			62
+#define JH7110_SYSRST_QSPI_REF			63
+
+#define JH7110_SYSRST_SDIO0_AHB		64
+#define JH7110_SYSRST_SDIO1_AHB		65
+#define JH7110_SYSRST_GMAC1_AXI		66
+#define JH7110_SYSRST_GMAC1_AHB		67
+#define JH7110_SYSRST_MAILBOX			68
+#define JH7110_SYSRST_SPI0_APB			69
+#define JH7110_SYSRST_SPI1_APB			70
+#define JH7110_SYSRST_SPI2_APB			71
+#define JH7110_SYSRST_SPI3_APB			72
+#define JH7110_SYSRST_SPI4_APB			73
+#define JH7110_SYSRST_SPI5_APB			74
+#define JH7110_SYSRST_SPI6_APB			75
+#define JH7110_SYSRST_I2C0_APB			76
+#define JH7110_SYSRST_I2C1_APB			77
+#define JH7110_SYSRST_I2C2_APB			78
+#define JH7110_SYSRST_I2C3_APB			79
+#define JH7110_SYSRST_I2C4_APB			80
+#define JH7110_SYSRST_I2C5_APB			81
+#define JH7110_SYSRST_I2C6_APB			82
+#define JH7110_SYSRST_UART0_APB		83
+#define JH7110_SYSRST_UART0_CORE		84
+#define JH7110_SYSRST_UART1_APB		85
+#define JH7110_SYSRST_UART1_CORE		86
+#define JH7110_SYSRST_UART2_APB		87
+#define JH7110_SYSRST_UART2_CORE		88
+#define JH7110_SYSRST_UART3_APB		89
+#define JH7110_SYSRST_UART3_CORE		90
+#define JH7110_SYSRST_UART4_APB		91
+#define JH7110_SYSRST_UART4_CORE		92
+#define JH7110_SYSRST_UART5_APB		93
+#define JH7110_SYSRST_UART5_CORE		94
+#define JH7110_SYSRST_SPDIF_APB		95
+
+#define JH7110_SYSRST_PWMDAC_APB		96
+#define JH7110_SYSRST_PDM_DMIC			97
+#define JH7110_SYSRST_PDM_APB			98
+#define JH7110_SYSRST_I2SRX_APB		99
+#define JH7110_SYSRST_I2SRX_BCLK		100
+#define JH7110_SYSRST_I2STX0_APB		101
+#define JH7110_SYSRST_I2STX0_BCLK		102
+#define JH7110_SYSRST_I2STX1_APB		103
+#define JH7110_SYSRST_I2STX1_BCLK		104
+#define JH7110_SYSRST_TDM_AHB			105
+#define JH7110_SYSRST_TDM_CORE			106
+#define JH7110_SYSRST_TDM_APB			107
+#define JH7110_SYSRST_PWM_APB			108
+#define JH7110_SYSRST_WDT_APB			109
+#define JH7110_SYSRST_WDT_CORE			110
+#define JH7110_SYSRST_CAN0_APB			111
+#define JH7110_SYSRST_CAN0_CORE		112
+#define JH7110_SYSRST_CAN0_TIMER		113
+#define JH7110_SYSRST_CAN1_APB			114
+#define JH7110_SYSRST_CAN1_CORE		115
+#define JH7110_SYSRST_CAN1_TIMER		116
+#define JH7110_SYSRST_TIMER_APB		117
+#define JH7110_SYSRST_TIMER0			118
+#define JH7110_SYSRST_TIMER1			119
+#define JH7110_SYSRST_TIMER2			120
+#define JH7110_SYSRST_TIMER3			121
+#define JH7110_SYSRST_INT_CTRL_APB		122
+#define JH7110_SYSRST_TEMP_APB			123
+#define JH7110_SYSRST_TEMP_CORE		124
+#define JH7110_SYSRST_JTAG_CERTIFICATION	125
+
+#define JH7110_SYSRST_END			126
+
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI		0
+#define JH7110_AONRST_GMAC0_AHB		1
+#define JH7110_AONRST_IOMUX			2
+#define JH7110_AONRST_PMU_APB			3
+#define JH7110_AONRST_PMU_WKUP			4
+#define JH7110_AONRST_RTC_APB			5
+#define JH7110_AONRST_RTC_CAL			6
+#define JH7110_AONRST_RTC_32K			7
+
+#define JH7110_AONRST_END			8
+
+/* STGCRG resets */
+#define JH7110_STGRST_SYSCON_PRESETN		0
+#define JH7110_STGRST_HIFI4_CORE		1
+#define JH7110_STGRST_HIFI4_AXI		2
+#define JH7110_STGRST_SEC_TOP_HRESETN		3
+#define JH7110_STGRST_E24_CORE			4
+#define JH7110_STGRST_DMA1P_AXI		5
+#define JH7110_STGRST_DMA1P_AHB		6
+#define JH7110_STGRST_USB_AXI			7
+#define JH7110_STGRST_USB_APB			8
+#define JH7110_STGRST_USB_UTMI_APB		9
+#define JH7110_STGRST_USB_PWRUP		10
+#define JH7110_STGRST_PCIE0_MST0		11
+#define JH7110_STGRST_PCIE0_SLV0		12
+#define JH7110_STGRST_PCIE0_SLV		13
+#define JH7110_STGRST_PCIE0_BRG		14
+#define JH7110_STGRST_PCIE0_CORE		15
+#define JH7110_STGRST_PCIE0_APB		16
+#define JH7110_STGRST_PCIE1_MST0		17
+#define JH7110_STGRST_PCIE1_SLV0		18
+#define JH7110_STGRST_PCIE1_SLV		19
+#define JH7110_STGRST_PCIE1_BRG		20
+#define JH7110_STGRST_PCIE1_CORE		21
+#define JH7110_STGRST_PCIE1_APB		22
+
+#define JH7110_STGRST_END			23
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
diff --git a/include/efi_api.h b/include/efi_api.h
index c4512eeb862..2fd0221c1c7 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -604,6 +604,7 @@ struct efi_device_path_acpi_path {
 #  define DEVICE_PATH_SUB_TYPE_MSG_MAC_ADDR	0x0b
 #  define DEVICE_PATH_SUB_TYPE_MSG_UART		0x0e
 #  define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS	0x0f
+#  define DEVICE_PATH_SUB_TYPE_MSG_USB_WWI	0x10
 #  define DEVICE_PATH_SUB_TYPE_MSG_SATA		0x12
 #  define DEVICE_PATH_SUB_TYPE_MSG_NVME		0x17
 #  define DEVICE_PATH_SUB_TYPE_MSG_URI		0x18
@@ -1172,7 +1173,7 @@ struct efi_hii_keyboard_layout {
 	efi_guid_t guid;
 	u32 layout_descriptor_string_offset;
 	u8 descriptor_count;
-	struct efi_key_descriptor descriptors[];
+	/* struct efi_key_descriptor descriptors[]; follows here */
 } __packed;
 
 struct efi_hii_keyboard_package {
diff --git a/include/efi_loader.h b/include/efi_loader.h
index cee04cbb9dc..b395eef9e79 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -134,6 +134,10 @@ static inline efi_status_t efi_launch_capsules(void)
 #define U_BOOT_GUID \
 	EFI_GUID(0xe61d73b9, 0xa384, 0x4acc, \
 		 0xae, 0xab, 0x82, 0xe8, 0x28, 0xf3, 0x62, 0x8b)
+/* GUID used as root for blkmap devices */
+#define U_BOOT_BLKMAP_DEV_GUID \
+	EFI_GUID(0x4cad859d, 0xd644, 0x42ff,	\
+		 0x87, 0x0b, 0xc0, 0x2e, 0xac, 0x05, 0x58, 0x63)
 /* GUID used as host device on sandbox */
 #define U_BOOT_HOST_DEV_GUID \
 	EFI_GUID(0xbbe4e671, 0x5773, 0x4ea1, \
@@ -509,9 +513,6 @@ struct efi_register_notify_event {
 	struct list_head handles;
 };
 
-/* List of all events registered by RegisterProtocolNotify() */
-extern struct list_head efi_register_notify_events;
-
 /* called at pre-initialization */
 int efi_init_early(void);
 /* Initialize efi execution environment */
diff --git a/include/env_flags.h b/include/env_flags.h
index 7de58cc57c3..d785f87cdcb 100644
--- a/include/env_flags.h
+++ b/include/env_flags.h
@@ -71,7 +71,7 @@ enum env_flags_varaccess {
 #define NET6_FLAGS \
 	"ip6addr:s," \
 	"serverip6:s," \
-	"gatewayip6:s"
+	"gatewayip6:s,"
 #else
 #define NET6_FLAGS
 #endif
diff --git a/include/environment/ti/ti_armv7_common.env b/include/environment/ti/ti_armv7_common.env
index 4d334648c05..0c0929d8628 100644
--- a/include/environment/ti/ti_armv7_common.env
+++ b/include/environment/ti/ti_armv7_common.env
@@ -20,5 +20,6 @@ get_overlaystring=
 	do;
 	setenv overlaystring ${overlaystring}'#'${overlay};
 	done;
-run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}
+get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile}
+run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring}
 
diff --git a/include/extcon.h b/include/extcon.h
new file mode 100644
index 00000000000..d060f5a3c1f
--- /dev/null
+++ b/include/extcon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <[email protected]>
+ */
+
+#ifndef __EXTCON_H
+#define __EXTCON_H
+
+struct udevice;
+
+/**
+ * struct extcon_uc_plat - Platform data the uclass stores about each device
+ *
+ * To be filled
+ */
+struct extcon_uc_plat {
+};
+
+#endif
diff --git a/include/faraday/ftwdt010_wdt.h b/include/faraday/ftwdt010_wdt.h
index 804907d6455..d4c11e39a05 100644
--- a/include/faraday/ftwdt010_wdt.h
+++ b/include/faraday/ftwdt010_wdt.h
@@ -89,7 +89,4 @@ struct ftwdt010_wdt {
  */
 #define FTWDT010_TIMEOUT_FACTOR		(get_board_sys_clk() / 1000) /* 1 ms */
 
-void ftwdt010_wdt_reset(void);
-void ftwdt010_wdt_disable(void);
-
 #endif /* __FTWDT010_H */
diff --git a/include/fastboot.h b/include/fastboot.h
index 07f4c8fa711..296451f89d4 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -124,6 +124,15 @@ void fastboot_init(void *buf_addr, u32 buf_size);
 void fastboot_boot(void);
 
 /**
+ * fastboot_handle_boot() - Shared implementation of system reaction to
+ * fastboot commands
+ *
+ * Making desceisions about device boot state (stay in fastboot, reboot
+ * to bootloader, reboot to OS, etc).
+ */
+void fastboot_handle_boot(int command, bool success);
+
+/**
  * fastboot_handle_command() - Handle fastboot command
  *
  * @cmd_string: Pointer to command string
diff --git a/include/fdt_simplefb.h b/include/fdt_simplefb.h
index 41cd740ac05..af93e3be631 100644
--- a/include/fdt_simplefb.h
+++ b/include/fdt_simplefb.h
@@ -9,6 +9,5 @@
 #ifndef _FDT_SIMPLEFB_H_
 #define _FDT_SIMPLEFB_H_
 int fdt_simplefb_add_node(void *blob);
-int fdt_simplefb_enable_existing_node(void *blob);
 int fdt_simplefb_enable_and_mem_rsv(void *blob);
 #endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index aa61a0fca1a..6716da9c659 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -187,7 +187,6 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
-	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
 	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
 	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* SoCFPGA pinctrl-single */
 	COMPAT_ALTERA_SOCFPGA_H2F_BRG,          /* SoCFPGA hps2fpga bridge */
diff --git a/include/generic-phy.h b/include/generic-phy.h
index f8eddeff67a..bee4de8a0ba 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -11,6 +11,29 @@
 
 struct ofnode_phandle_args;
 
+enum phy_mode {
+	PHY_MODE_INVALID,
+	PHY_MODE_USB_HOST,
+	PHY_MODE_USB_HOST_LS,
+	PHY_MODE_USB_HOST_FS,
+	PHY_MODE_USB_HOST_HS,
+	PHY_MODE_USB_HOST_SS,
+	PHY_MODE_USB_DEVICE,
+	PHY_MODE_USB_DEVICE_LS,
+	PHY_MODE_USB_DEVICE_FS,
+	PHY_MODE_USB_DEVICE_HS,
+	PHY_MODE_USB_DEVICE_SS,
+	PHY_MODE_USB_OTG,
+	PHY_MODE_UFS_HS_A,
+	PHY_MODE_UFS_HS_B,
+	PHY_MODE_PCIE,
+	PHY_MODE_ETHERNET,
+	PHY_MODE_MIPI_DPHY,
+	PHY_MODE_SATA,
+	PHY_MODE_LVDS,
+	PHY_MODE_DP
+};
+
 /**
  * struct phy - A handle to (allowing control of) a single phy port.
  *
@@ -69,73 +92,99 @@ struct phy_ops {
 	int	(*init)(struct phy *phy);
 
 	/**
-	* exit - de-initialize the PHY device
-	*
-	* Hardware de-intialization should be done here. Every step done in
-	* init() should be undone here.
-	* This could be used to suspend the phy to reduce power consumption or
-	* to put the phy in a known condition before booting the OS (though it
-	* is NOT called automatically before booting the OS)
-	* If power_off() is not implemented, it must power down the phy.
-	*
-	* @phy:	PHY port to be de-initialized
-	* Return: 0 if OK, or a negative error code
-	*/
+	 * exit - de-initialize the PHY device
+	 *
+	 * Hardware de-intialization should be done here. Every step done in
+	 * init() should be undone here.
+	 * This could be used to suspend the phy to reduce power consumption or
+	 * to put the phy in a known condition before booting the OS (though it
+	 * is NOT called automatically before booting the OS)
+	 * If power_off() is not implemented, it must power down the phy.
+	 *
+	 * @phy:	PHY port to be de-initialized
+	 * Return: 0 if OK, or a negative error code
+	 */
 	int	(*exit)(struct phy *phy);
 
 	/**
-	* reset - resets a PHY device without shutting down
-	*
-	* @phy:	PHY port to be reset
-	*
-	* During runtime, the PHY may need to be reset in order to
-	* re-establish connection etc without being shut down or exit.
-	*
-	* Return: 0 if OK, or a negative error code
-	*/
+	 * reset - resets a PHY device without shutting down
+	 *
+	 * @phy:	PHY port to be reset
+	 *
+	 * During runtime, the PHY may need to be reset in order to
+	 * re-establish connection etc without being shut down or exit.
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
 	int	(*reset)(struct phy *phy);
 
 	/**
-	* power_on - power on a PHY device
-	*
-	* @phy:	PHY port to be powered on
-	*
-	* During runtime, the PHY may need to be powered on or off several
-	* times. This function is used to power on the PHY. It relies on the
-	* setup done in init(). If init() is not implemented, it must take care
-	* of setting up the context (PLLs, ...)
-	*
-	* Return: 0 if OK, or a negative error code
-	*/
+	 * power_on - power on a PHY device
+	 *
+	 * @phy:	PHY port to be powered on
+	 *
+	 * During runtime, the PHY may need to be powered on or off several
+	 * times. This function is used to power on the PHY. It relies on the
+	 * setup done in init(). If init() is not implemented, it must take care
+	 * of setting up the context (PLLs, ...)
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
 	int	(*power_on)(struct phy *phy);
 
 	/**
-	* power_off - power off a PHY device
-	*
-	* @phy:	PHY port to be powered off
-	*
-	* During runtime, the PHY may need to be powered on or off several
-	* times. This function is used to power off the PHY. Except if
-	* init()/deinit() are not implemented, it must not de-initialize
-	* everything.
-	*
-	* Return: 0 if OK, or a negative error code
-	*/
+	 * power_off - power off a PHY device
+	 *
+	 * @phy:	PHY port to be powered off
+	 *
+	 * During runtime, the PHY may need to be powered on or off several
+	 * times. This function is used to power off the PHY. Except if
+	 * init()/deinit() are not implemented, it must not de-initialize
+	 * everything.
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
 	int	(*power_off)(struct phy *phy);
 
 	/**
-	* configure - configure a PHY device
-	*
-	* @phy:	PHY port to be configured
-	* @params: PHY Parameters, underlying data is specific to the PHY function
-	*
-	* During runtime, the PHY may need to be configured for it's main function.
-	* This function configures the PHY for it's main function following
-	* power_on/off() after beeing initialized.
-	*
-	* Return: 0 if OK, or a negative error code
-	*/
+	 * configure - configure a PHY device
+	 *
+	 * @phy:	PHY port to be configured
+	 * @params: PHY Parameters, underlying data is specific to the PHY function
+	 *
+	 * During runtime, the PHY may need to be configured for it's main function.
+	 * This function configures the PHY for it's main function following
+	 * power_on/off() after being initialized.
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
 	int	(*configure)(struct phy *phy, void *params);
+
+	/**
+	 * set_mode - set PHY device mode
+	 *
+	 * @phy:	PHY port to be configured
+	 * @mode: PHY mode
+	 * @submode: PHY submode
+	 *
+	 * Configure PHY mode (e.g. USB, Ethernet, ...) and submode
+	 * (e.g. for Ethernet this can be RGMII).
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
+	int	(*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
+
+	/**
+	 * set_speed - set PHY device speed
+	 *
+	 * @phy:	PHY port to be configured
+	 * @speed: PHY speed
+	 *
+	 * Configure PHY speed (e.g. for Ethernet, this could be 10 or 100 ...).
+	 *
+	 * Return: 0 if OK, or a negative error code
+	 */
+	int	(*set_speed)(struct phy *phy, int speed);
 };
 
 /**
@@ -206,6 +255,24 @@ int generic_phy_power_off(struct phy *phy);
  */
 int generic_phy_configure(struct phy *phy, void *params);
 
+/**
+ * generic_phy_set_mode() - set PHY device mode
+ *
+ * @phy:	PHY port to be configured
+ * @mode: PHY mode
+ * @submode: PHY submode
+ * Return: 0 if OK, or a negative error code
+ */
+int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode);
+
+/**
+ * generic_phy_set_speed() - set PHY device speed
+ *
+ * @phy:	PHY port to be configured
+ * @speed: PHY speed
+ * Return: 0 if OK, or a negative error code
+ */
+int generic_phy_set_speed(struct phy *phy, int speed);
 
 /**
  * generic_phy_get_by_index() - Get a PHY device by integer index.
@@ -389,6 +456,21 @@ static inline int generic_phy_power_off(struct phy *phy)
 	return 0;
 }
 
+static inline int generic_phy_configure(struct phy *phy, void *params)
+{
+	return 0;
+}
+
+static inline int generic_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+	return 0;
+}
+
+static inline int generic_phy_set_speed(struct phy *phy, int speed)
+{
+	return 0;
+}
+
 static inline int generic_phy_get_by_index(struct udevice *user, int index,
 			     struct phy *phy)
 {
diff --git a/include/ide.h b/include/ide.h
index 426cef4e39e..2c25e74ede0 100644
--- a/include/ide.h
+++ b/include/ide.h
@@ -11,50 +11,14 @@
 
 #define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
 
-#define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
-extern ulong ide_bus_offset[];
-
-/*
- * Function Prototypes
- */
-
-void ide_init(void);
-struct blk_desc;
-struct udevice;
-#ifdef CONFIG_BLK
-ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer);
-ulong ide_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer);
-#else
-ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-	       void *buffer);
-ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
-		const void *buffer);
-#endif
-
-#if defined(CONFIG_OF_IDE_FIXUP)
-int ide_device_present(int dev);
-#endif
-
-/*
- * I/O function overrides
- */
-unsigned char ide_inb(int dev, int port);
-void ide_outb(int dev, int port, unsigned char val);
-void ide_input_swap_data(int dev, ulong *sect_buf, int words);
-void ide_input_data(int dev, ulong *sect_buf, int words);
-void ide_output_data(int dev, const ulong *sect_buf, int words);
-void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
-void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
-
-void ide_led(uchar led, uchar status);
-
 /**
- * board_start_ide() - Start up the board IDE interfac
+ * ide_set_reset() - Assert or de-assert reset for the IDE device
+ *
+ * This is provided by boards which need to reset the device through another
+ * means, e.g. a GPIO.
  *
- * Return: 0 if ok
+ * @idereset: 1 to assert reset, 0 to de-assert it
  */
-int board_start_ide(void);
+void ide_set_reset(int idereset);
 
 #endif /* _IDE_H */
diff --git a/include/image.h b/include/image.h
index 7717a4c13d3..456197d6fda 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1733,25 +1733,174 @@ struct cipher_algo {
 int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo);
 
 struct cipher_algo *image_get_cipher_algo(const char *full_name);
+struct andr_image_data;
 
-struct andr_img_hdr;
-int android_image_check_header(const struct andr_img_hdr *hdr);
-int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+/**
+ * android_image_get_data() - Parse Android boot images
+ *
+ * This is used to parse boot and vendor-boot header into
+ * andr_image_data generic structure.
+ *
+ * @boot_hdr: Pointer to boot image header
+ * @vendor_boot_hdr: Pointer to vendor boot image header
+ * @data: Pointer to generic boot format structure
+ * Return: true if succeeded, false otherwise
+ */
+bool android_image_get_data(const void *boot_hdr, const void *vendor_boot_hdr,
+			    struct andr_image_data *data);
+
+struct andr_boot_img_hdr_v0;
+
+/**
+ * android_image_get_kernel() - Processes kernel part of Android boot images
+ *
+ * This function returns the os image's start address and length. Also,
+ * it appends the kernel command line to the bootargs env variable.
+ *
+ * @hdr:	Pointer to image header, which is at the start
+ *			of the image.
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * @verify:	Checksum verification flag. Currently unimplemented.
+ * @os_data:	Pointer to a ulong variable, will hold os data start
+ *			address.
+ * @os_len:	Pointer to a ulong variable, will hold os data length.
+ * Return: Zero, os start address and length on success,
+ *		otherwise on failure.
+ */
+int android_image_get_kernel(const void *hdr,
+			     const void *vendor_boot_img, int verify,
 			     ulong *os_data, ulong *os_len);
-int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+
+/**
+ * android_image_get_ramdisk() - Extracts the ramdisk load address and its size
+ *
+ * This extracts the load address of the ramdisk and its size
+ *
+ * @hdr:	Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * @rd_data:	Pointer to a ulong variable, will hold ramdisk address
+ * @rd_len:	Pointer to a ulong variable, will hold ramdisk length
+ * Return: 0 if succeeded, -1 if ramdisk size is 0
+ */
+int android_image_get_ramdisk(const void *hdr, const void *vendor_boot_img,
 			      ulong *rd_data, ulong *rd_len);
-int android_image_get_second(const struct andr_img_hdr *hdr,
-			      ulong *second_data, ulong *second_len);
+
+/**
+ * android_image_get_second() - Extracts the secondary bootloader address
+ * and its size
+ *
+ * This extracts the address of the secondary bootloader and its size
+ *
+ * @hdr:	 Pointer to image header
+ * @second_data: Pointer to a ulong variable, will hold secondary bootloader address
+ * @second_len : Pointer to a ulong variable, will hold secondary bootloader length
+ * Return: 0 if succeeded, -1 if secondary bootloader size is 0
+ */
+int android_image_get_second(const void *hdr, ulong *second_data, ulong *second_len);
 bool android_image_get_dtbo(ulong hdr_addr, ulong *addr, u32 *size);
-bool android_image_get_dtb_by_index(ulong hdr_addr, u32 index, ulong *addr,
-				    u32 *size);
-ulong android_image_get_end(const struct andr_img_hdr *hdr);
-ulong android_image_get_kload(const struct andr_img_hdr *hdr);
-ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
-void android_print_contents(const struct andr_img_hdr *hdr);
+
+/**
+ * android_image_get_dtb_by_index() - Get address and size of blob in DTB area.
+ * @hdr_addr: Boot image header address
+ * @vendor_boot_img: Pointer to vendor boot image header, which is at the start of the image.
+ * @index: Index of desired DTB in DTB area (starting from 0)
+ * @addr: If not NULL, will contain address to specified DTB
+ * @size: If not NULL, will contain size of specified DTB
+ *
+ * Get the address and size of DTB blob by its index in DTB area of Android
+ * Boot Image in RAM.
+ *
+ * Return: true on success or false on error.
+ */
+bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img,
+				    u32 index, ulong *addr, u32 *size);
+
+/**
+ * android_image_get_end() - Get the end of Android boot image
+ *
+ * This returns the end address of Android boot image address
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: The end address of Android boot image
+ */
+ulong android_image_get_end(const struct andr_boot_img_hdr_v0 *hdr,
+			    const void *vendor_boot_img);
+
+/**
+ * android_image_get_kload() - Get the kernel load address
+ *
+ * This returns the kernel load address. The load address is extracted
+ * from the boot image header or the "kernel_addr_r" environment variable
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: The kernel load address
+ */
+ulong android_image_get_kload(const void *hdr,
+			      const void *vendor_boot_img);
+
+/**
+ * android_image_get_kcomp() - Get kernel compression type
+ *
+ * This gets the kernel compression type from the boot image header
+ *
+ * @hdr: Pointer to image header
+ * @vendor_boot_img : Pointer to vendor boot image header
+ * Return: Kernel compression type
+ */
+ulong android_image_get_kcomp(const void *hdr,
+			      const void *vendor_boot_img);
+
+/**
+ * android_print_contents() - Prints out the contents of the Android format image
+ *
+ * This formats a multi line Android image contents description.
+ * The routine prints out Android image properties
+ *
+ * @hdr: Pointer to the Android format image header
+ * Return: no returned results
+ */
+void android_print_contents(const struct andr_boot_img_hdr_v0 *hdr);
 bool android_image_print_dtb_contents(ulong hdr_addr);
 
 /**
+ * is_android_boot_image_header() - Check the magic of boot image
+ *
+ * This checks the header of Android boot image and verifies the
+ * magic is "ANDROID!"
+ *
+ * @hdr: Pointer to boot image
+ * Return: non-zero if the magic is correct, zero otherwise
+ */
+bool is_android_boot_image_header(const void *hdr);
+
+/**
+ * is_android_vendor_boot_image_header() - Check the magic of vendor boot image
+ *
+ * This checks the header of Android vendor boot image and verifies the magic
+ * is "VNDRBOOT"
+ *
+ * @vendor_boot_img: Pointer to boot image
+ * Return: non-zero if the magic is correct, zero otherwise
+ */
+bool is_android_vendor_boot_image_header(const void *vendor_boot_img);
+
+/**
+ * get_abootimg_addr() - Get Android boot image address
+ *
+ * Return: Android boot image address
+ */
+ulong get_abootimg_addr(void);
+
+/**
+ * get_avendor_bootimg_addr() - Get Android vendor boot image address
+ *
+ * Return: Android vendor boot image address
+ */
+ulong get_avendor_bootimg_addr(void);
+
+/**
  * board_fit_config_name_match() - Check for a matching board name
  *
  * This is used when SPL loads a FIT containing multiple device tree files
diff --git a/include/linker_lists.h b/include/linker_lists.h
index d3da9d44e85..f9a2ee0c762 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -127,7 +127,9 @@
 	static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN)	\
 		__attribute__((unused))					\
 		__section("__u_boot_list_2_"#_list"_1");			\
-	(_type *)&start;						\
+	_type * tmp = (_type *)&start;					\
+	asm("":"+r"(tmp));						\
+	tmp;								\
 })
 
 /**
@@ -153,7 +155,9 @@
 ({									\
 	static char end[0] __aligned(4) __attribute__((unused))		\
 		__section("__u_boot_list_2_"#_list"_3");			\
-	(_type *)&end;							\
+	_type * tmp = (_type *)&end;					\
+	asm("":"+r"(tmp));						\
+	tmp;								\
 })
 /**
  * ll_entry_count() - Return the number of elements in linker-generated array
@@ -247,7 +251,9 @@
 ({									\
 	static char start[0] __aligned(4) __attribute__((unused))	\
 		__section("__u_boot_list_1");				\
-	(_type *)&start;						\
+	_type * tmp = (_type *)&start;					\
+	asm("":"+r"(tmp));						\
+	tmp;								\
 })
 
 /**
@@ -270,7 +276,9 @@
 ({									\
 	static char end[0] __aligned(4) __attribute__((unused))		\
 		__section("__u_boot_list_3");				\
-	(_type *)&end;							\
+	_type * tmp = (_type *)&end;					\
+	asm("":"+r"(tmp));						\
+	tmp;								\
 })
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 6e821d906fb..b7c845155e4 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -44,6 +44,7 @@
 #define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
 #define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
 #define MDIO_PCS_EEE_ABLE	20	/* EEE Capability register */
+#define MDIO_PMA_NG_EXTABLE	21	/* 2.5G/5G PMA/PMD extended ability */
 #define MDIO_PCS_EEE_WK_ERR	22	/* EEE wake error counter */
 #define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
 #define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
@@ -91,6 +92,10 @@
 #define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
 /* 10PASS-TS/2BASE-TL */
 #define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
+/* 2.5 Gb/s */
+#define MDIO_CTRL1_SPEED2_5G		(MDIO_CTRL1_SPEEDSELEXT | 0x18)
+/* 5 Gb/s */
+#define MDIO_CTRL1_SPEED5G		(MDIO_CTRL1_SPEEDSELEXT | 0x1c)
 
 /* Status register 1. */
 #define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
@@ -111,6 +116,8 @@
 #define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
 #define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
 #define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
+#define MDIO_PCS_SPEED_2_5G		0x0040	/* 2.5G capable */
+#define MDIO_PCS_SPEED_5G		0x0080	/* 5G capable */
 
 /* Device present registers. */
 #define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
@@ -150,6 +157,8 @@
 #define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
 #define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
 #define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
+#define MDIO_PMA_CTRL2_2_5GBT		0x0030  /* 2.5GBaseT type */
+#define MDIO_PMA_CTRL2_5GBT		0x0031  /* 5GBaseT type */
 #define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
 #define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
 #define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
@@ -203,6 +212,7 @@
 #define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
 #define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
 #define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
+#define MDIO_PMA_EXTABLE_NBT		0x4000  /* 2.5/5GBASE-T ability */
 
 /* PHY XGXS lane state register. */
 #define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
@@ -239,9 +249,13 @@
 #define MDIO_PCS_10GBRT_STAT2_BER	0x3f00
 
 /* AN 10GBASE-T control register. */
+#define MDIO_AN_10GBT_CTRL_ADV2_5G	0x0080	/* Advertise 2.5GBASE-T */
+#define MDIO_AN_10GBT_CTRL_ADV5G	0x0100	/* Advertise 5GBASE-T */
 #define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
 
 /* AN 10GBASE-T status register. */
+#define MDIO_AN_10GBT_STAT_LP2_5G	0x0020  /* LP is 2.5GBT capable */
+#define MDIO_AN_10GBT_STAT_LP5G		0x0040  /* LP is 5GBT capable */
 #define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
 #define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
 #define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
@@ -270,6 +284,10 @@
 #define MDIO_EEE_10GKX4		0x0020	/* 10G KX4 EEE cap */
 #define MDIO_EEE_10GKR		0x0040	/* 10G KR EEE cap */
 
+/* 2.5G/5G Extended abilities register. */
+#define MDIO_PMA_NG_EXTABLE_2_5GBT	0x0001	/* 2.5GBASET ability */
+#define MDIO_PMA_NG_EXTABLE_5GBT	0x0002	/* 5GBASET ability */
+
 /* LASI RX_ALARM control/status registers. */
 #define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
 #define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
diff --git a/include/lmb.h b/include/lmb.h
index 7298c2ccc40..07bf22144ea 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -35,6 +35,24 @@ struct lmb_property {
 	enum lmb_flags flags;
 };
 
+/*
+ * For regions size management, see LMB configuration in KConfig
+ * all the #if test are done with CONFIG_LMB_USE_MAX_REGIONS (boolean)
+ *
+ * case 1. CONFIG_LMB_USE_MAX_REGIONS is defined (legacy mode)
+ *         => CONFIG_LMB_MAX_REGIONS is used to configure the region size,
+ *         directly in the array lmb_region.region[], with the same
+ *         configuration for memory and reserved regions.
+ *
+ * case 2. CONFIG_LMB_USE_MAX_REGIONS is not defined, the size of each
+ *         region is configurated *independently* with
+ *         => CONFIG_LMB_MEMORY_REGIONS: struct lmb.memory_regions
+ *         => CONFIG_LMB_RESERVED_REGIONS: struct lmb.reserved_regions
+ *         lmb_region.region is only a pointer to the correct buffer,
+ *         initialized in lmb_init(). This configuration is useful to manage
+ *         more reserved memory regions with CONFIG_LMB_RESERVED_REGIONS.
+ */
+
 /**
  * struct lmb_region - Description of a set of region.
  *
@@ -68,7 +86,7 @@ struct lmb_region {
 struct lmb {
 	struct lmb_region memory;
 	struct lmb_region reserved;
-#ifdef CONFIG_LMB_MEMORY_REGIONS
+#if !IS_ENABLED(CONFIG_LMB_USE_MAX_REGIONS)
 	struct lmb_property memory_regions[CONFIG_LMB_MEMORY_REGIONS];
 	struct lmb_property reserved_regions[CONFIG_LMB_RESERVED_REGIONS];
 #endif
diff --git a/include/marvell_phy.h b/include/marvell_phy.h
new file mode 100644
index 00000000000..0f06c2287b5
--- /dev/null
+++ b/include/marvell_phy.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _MARVELL_PHY_H
+#define _MARVELL_PHY_H
+
+/* Mask used for ID comparisons */
+#define MARVELL_PHY_ID_MASK		0xfffffff0
+
+/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E1101		0x01410c60
+#define MARVELL_PHY_ID_88E1112		0x01410c90
+#define MARVELL_PHY_ID_88E1111		0x01410cc0
+#define MARVELL_PHY_ID_88E1118		0x01410e10
+#define MARVELL_PHY_ID_88E1121R		0x01410cb0
+#define MARVELL_PHY_ID_88E1145		0x01410cd0
+#define MARVELL_PHY_ID_88E1149R		0x01410e50
+#define MARVELL_PHY_ID_88E1240		0x01410e30
+#define MARVELL_PHY_ID_88E1318S		0x01410e90
+#define MARVELL_PHY_ID_88E1340S		0x01410dc0
+#define MARVELL_PHY_ID_88E1116R		0x01410e40
+#define MARVELL_PHY_ID_88E1510		0x01410dd0
+#define MARVELL_PHY_ID_88E1540		0x01410eb0
+#define MARVELL_PHY_ID_88E1545		0x01410ea0
+#define MARVELL_PHY_ID_88E1548P		0x01410ec0
+#define MARVELL_PHY_ID_88E3016		0x01410e60
+#define MARVELL_PHY_ID_88X3310		0x002b09a0
+#define MARVELL_PHY_ID_88E2110		0x002b09b0
+#define MARVELL_PHY_ID_88X2222		0x01410f10
+
+/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
+#define MARVELL_PHY_ID_88E1111_FINISAR	0x01ff0cc0
+
+/* These Ethernet switch families contain embedded PHYs, but they do
+ * not have a model ID. So the switch driver traps reads to the ID2
+ * register and returns the switch family ID
+ */
+#define MARVELL_PHY_ID_88E6341_FAMILY	0x01410f41
+#define MARVELL_PHY_ID_88E6390_FAMILY	0x01410f90
+#define MARVELL_PHY_ID_88E6393_FAMILY	0x002b0b9b
+
+#define MARVELL_PHY_FAMILY_ID(id)	((id) >> 4)
+
+/* struct phy_device dev_flags definitions */
+#define MARVELL_PHY_M1145_FLAGS_RESISTANCE	0x00000001
+#define MARVELL_PHY_M1118_DNS323_LEDS		0x00000002
+#define MARVELL_PHY_LED0_LINK_LED1_ACTIVE	0x00000004
+
+#endif /* _MARVELL_PHY_H */
diff --git a/include/mmc.h b/include/mmc.h
index 36dd841d5d1..b8fbff150de 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -241,6 +241,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
 #define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
 #define EXT_CSD_BOOT_MULT		226	/* RO */
+#define EXT_CSD_SEC_FEATURE		231	/* RO */
 #define EXT_CSD_GENERIC_CMD6_TIME       248     /* RO */
 #define EXT_CSD_BKOPS_SUPPORT		502	/* RO */
 
@@ -315,6 +316,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define EXT_CSD_WR_DATA_REL_USR		(1 << 0)	/* user data area WR_REL */
 #define EXT_CSD_WR_DATA_REL_GP(x)	(1 << ((x)+1))	/* GP part (x+1) WR_REL */
 
+#define EXT_CSD_SEC_FEATURE_TRIM_EN	(1 << 4) /* Support secure & insecure trim */
+
 #define R1_ILLEGAL_COMMAND		(1 << 22)
 #define R1_APP_CMD			(1 << 5)
 
@@ -687,6 +690,7 @@ struct mmc {
 	uint tran_speed;
 	uint legacy_speed; /* speed for the legacy mode provided by the card */
 	uint read_bl_len;
+	bool can_trim;
 #if CONFIG_IS_ENABLED(MMC_WRITE)
 	uint write_bl_len;
 	uint erase_grp_size;	/* in 512-byte sectors */
diff --git a/include/ndisc.h b/include/ndisc.h
index f6f8eb6507c..d0fe3acca4a 100644
--- a/include/ndisc.h
+++ b/include/ndisc.h
@@ -19,6 +19,20 @@ struct nd_msg {
 	__u8		opt[0];
 };
 
+/* struct rs_msg - ICMPv6 Router Solicitation message format */
+struct rs_msg {
+	struct icmp6hdr	icmph;
+	__u8		opt[0];
+};
+
+/* struct ra_msg - ICMPv6 Router Advertisement message format */
+struct ra_msg {
+	struct icmp6hdr	icmph;
+	__u32	reachable_time;
+	__u32	retransmission_timer;
+	__u8	opt[0];
+};
+
 /* struct echo_msg - ICMPv6 echo request/reply message format */
 struct echo_msg {
 	struct icmp6hdr	icmph;
@@ -57,6 +71,11 @@ extern int net_nd_try;
  */
 void ndisc_init(void);
 
+/*
+ * ip6_send_rs() - Send IPv6 Router Solicitation Message
+ */
+void ip6_send_rs(void);
+
 /**
  * ndisc_receive() - Handle ND packet
  *
@@ -78,6 +97,8 @@ void ndisc_request(void);
  * Return: 0 if no timeout, -1 otherwise
  */
 int ndisc_timeout_check(void);
+bool validate_ra(struct ip6_hdr *ip6);
+int process_ra(struct ip6_hdr *ip6, int len);
 #else
 static inline void ndisc_init(void)
 {
@@ -97,6 +118,20 @@ static inline int ndisc_timeout_check(void)
 {
 	return 0;
 }
+
+static inline void ip6_send_rs(void)
+{
+}
+
+static inline bool validate_ra(struct ip6_hdr *ip6)
+{
+	return true;
+}
+
+static inline int process_ra(struct ip6_hdr *ip6, int len)
+{
+	return 0;
+}
 #endif
 
 #endif /* __NDISC_H__ */
diff --git a/include/net.h b/include/net.h
index 399af5e0645..785cb1059ef 100644
--- a/include/net.h
+++ b/include/net.h
@@ -484,6 +484,8 @@ extern char	net_hostname[32];	/* Our hostname */
 #ifdef CONFIG_NET
 extern char	net_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN];	/* Our root path */
 #endif
+/* Indicates whether the pxe path prefix / config file was specified in dhcp option */
+extern char *pxelinux_configfile;
 /** END OF BOOTP EXTENTIONS **/
 extern u8		net_ethaddr[ARP_HLEN];		/* Our ethernet address */
 extern u8		net_server_ethaddr[ARP_HLEN];	/* Boot server enet address */
@@ -504,8 +506,9 @@ extern ushort		net_native_vlan;	/* Our Native VLAN */
 extern int		net_restart_wrap;	/* Tried all network devices */
 
 enum proto_t {
-	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
-	SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET
+	BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
+	NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT_UDP, FASTBOOT_TCP,
+	WOL, UDP, NCSI, WGET, RS
 };
 
 extern char	net_boot_file_name[1024];/* Boot File name */
diff --git a/include/net/fastboot.h b/include/net/fastboot.h
deleted file mode 100644
index 68602095d2b..00000000000
--- a/include/net/fastboot.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (C) 2016 The Android Open Source Project
- */
-
-#ifndef __NET_FASTBOOT_H__
-#define __NET_FASTBOOT_H__
-
-/**********************************************************************/
-/*
- *	Global functions and variables.
- */
-
-/**
- * Wait for incoming fastboot comands.
- */
-void fastboot_start_server(void);
-
-/**********************************************************************/
-
-#endif /* __NET_FASTBOOT_H__ */
diff --git a/include/net/fastboot_tcp.h b/include/net/fastboot_tcp.h
new file mode 100644
index 00000000000..6cf29d52e93
--- /dev/null
+++ b/include/net/fastboot_tcp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2023 The Android Open Source Project
+ */
+
+#ifndef __NET_FASTBOOT_TCP_H__
+#define __NET_FASTBOOT_TCP_H__
+
+/**
+ * Wait for incoming tcp fastboot comands.
+ */
+void fastboot_tcp_start_server(void);
+
+#endif /* __NET_FASTBOOT_TCP_H__ */
diff --git a/include/net/fastboot_udp.h b/include/net/fastboot_udp.h
new file mode 100644
index 00000000000..d4382c0a0e0
--- /dev/null
+++ b/include/net/fastboot_udp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2016 The Android Open Source Project
+ */
+
+#ifndef __NET_FASTBOOT_H__
+#define __NET_FASTBOOT_H__
+
+/**
+ * Wait for incoming UDP fastboot comands.
+ */
+void fastboot_udp_start_server(void);
+
+#endif /* __NET_FASTBOOT_H__ */
diff --git a/include/net/ldpaa_eth.h b/include/net/ldpaa_eth.h
new file mode 100644
index 00000000000..7474bfaeec3
--- /dev/null
+++ b/include/net/ldpaa_eth.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 NXP
+ */
+
+#define LDPAA_ETH_DRIVER_NAME	"ldpaa_eth"
+
+/**
+ * ldpaa_eth_get_dpmac_id() - Get the dpmac_id of a DPAA2 ethernet device
+ *
+ * @dev:	DPAA2 ethernet udevice pointer
+ * Return: requested dpmac_id
+ */
+
+uint32_t ldpaa_eth_get_dpmac_id(struct udevice *dev);
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 322551694f5..c29d4ce24a7 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -259,6 +259,7 @@ union tcp_build_pkt {
  * enum tcp_state - TCP State machine states for connection
  * @TCP_CLOSED: Need to send SYN to connect
  * @TCP_SYN_SENT: Trying to connect, waiting for SYN ACK
+ * @TCP_SYN_RECEIVED: Initial SYN received, waiting for ACK
  * @TCP_ESTABLISHED: both server & client have a connection
  * @TCP_CLOSE_WAIT: Rec FIN, passed to app for FIN, ACK rsp
  * @TCP_CLOSING: Rec FIN, sent FIN, ACK waiting for ACK
@@ -268,6 +269,7 @@ union tcp_build_pkt {
 enum tcp_state {
 	TCP_CLOSED,
 	TCP_SYN_SENT,
+	TCP_SYN_RECEIVED,
 	TCP_ESTABLISHED,
 	TCP_CLOSE_WAIT,
 	TCP_CLOSING,
@@ -283,14 +285,18 @@ int tcp_set_tcp_header(uchar *pkt, int dport, int sport, int payload_len,
 /**
  * rxhand_tcp() - An incoming packet handler.
  * @pkt: pointer to the application packet
- * @dport: destination UDP port
+ * @dport: destination TCP port
  * @sip: source IP address
- * @sport: source UDP port
+ * @sport: source TCP port
+ * @tcp_seq_num: TCP sequential number
+ * @tcp_ack_num: TCP acknowledgment number
+ * @action: TCP action (SYN, ACK, FIN, etc)
  * @len: packet length
  */
-typedef void rxhand_tcp(uchar *pkt, unsigned int dport,
-			struct in_addr sip, unsigned int sport,
-			unsigned int len);
+typedef void rxhand_tcp(uchar *pkt, u16 dport,
+			struct in_addr sip, u16 sport,
+			u32 tcp_seq_num, u32 tcp_ack_num,
+			u8 action, unsigned int len);
 void tcp_set_tcp_handler(rxhand_tcp *f);
 
 void rxhand_tcp_f(union tcp_build_pkt *b, unsigned int len);
diff --git a/include/net6.h b/include/net6.h
index 2d7c5a09604..beafc053386 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -81,8 +81,17 @@ struct udp_hdr {
 			  0x00, 0x00, 0x00, 0x00, \
 			  0x00, 0x00, 0x00, 0x00, \
 			  0x00, 0x00, 0x00, 0x00 } } }
+/*
+ * All-routers multicast address is the link-local scope address to reach all
+ * routers.
+ */
+#define ALL_ROUTERS_MULT_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \
+				  0x00, 0x00, 0x00, 0x00, \
+				  0x00, 0x00, 0x00, 0x00, \
+				  0x00, 0x00, 0x00, 0x02 } } }
 
 #define IPV6_LINK_LOCAL_PREFIX	0xfe80
+#define IPV6_LINK_LOCAL_MASK	0xffb0 /* The first 10-bit of address mask. */
 
 /* hop limit for neighbour discovery packets */
 #define IPV6_NDISC_HOPLIMIT             255
@@ -166,6 +175,37 @@ struct icmp6hdr {
 #define icmp6_rt_lifetime	icmp6_dataun.u_nd_ra.rt_lifetime
 } __packed;
 
+/*
+ * struct icmp6_ra_prefix_info - Prefix Information option of the ICMPv6 message
+ * The Prefix Information option provides hosts with on-link prefixes and
+ * prefixes for Address Autoconfiguration. Refer to RFC 4861 for more info.
+ */
+struct icmp6_ra_prefix_info {
+	u8	type;		/* Type is 3 for Prefix Information. */
+	u8	len;		/* Len is 4 for Prefix Information. */
+	/* The number of leading bits in the Prefix that are valid. */
+	u8	prefix_len;
+	u8	reserved1:6,	/* MUST be ignored by the receiver. */
+		aac:1,		/* autonomous address-configuration flag */
+	/* Indicates that this prefix can be used for on-link determination. */
+		on_link:1;
+	/*
+	 * The length of time in seconds that the prefix is valid for the
+	 * purpose of on-link determination.
+	 */
+	__be32	valid_lifetime;
+	/* The length of time addresses remain preferred. */
+	__be32	preferred_lifetime;
+	__be32	reserved2;	/* MUST be ignored by the receiver. */
+	/*
+	 * Prefix is an IP address or a prefix of an IP address. The Prefix
+	 * Length field contains the number of valid leading bits in the prefix.
+	 * The bits in the prefix after the prefix length are reserved and MUST
+	 * be initialized to zero by the sender and ignored by the receiver.
+	 */
+	struct in6_addr prefix;
+};
+
 extern struct in6_addr const net_null_addr_ip6;	/* NULL IPv6 address */
 extern struct in6_addr net_gateway6;	/* Our gateways IPv6 address */
 extern struct in6_addr net_ip6;	/* Our IPv6 addr (0 = unknown) */
diff --git a/include/os.h b/include/os.h
index 0415f0f0e7a..968412b0a82 100644
--- a/include/os.h
+++ b/include/os.h
@@ -64,7 +64,7 @@ off_t os_lseek(int fd, off_t offset, int whence);
  * @fd:		File descriptor as returned by os_open()
  * Return:	file size or negative error code
  */
-int os_filesize(int fd);
+off_t os_filesize(int fd);
 
 /**
  * Access to the OS open() system call
diff --git a/include/phy.h b/include/phy.h
index 87aa86c2e78..247223d92be 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -125,8 +125,6 @@ struct phy_driver {
 	int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
 			 u16 val);
 
-	struct list_head list;
-
 	/* driver private data */
 	ulong data;
 };
@@ -173,10 +171,6 @@ struct fixed_link {
 	int asym_pause;
 };
 
-#ifdef CONFIG_PHYLIB_10G
-extern struct phy_driver gen10g_driver;
-#endif
-
 /**
  * phy_init() - Initializes the PHY drivers
  * This function registers all available PHY drivers
@@ -288,6 +282,37 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 		return dev_ofnode(phydev->dev);
 }
 
+/**
+ * phy_read_mmd_poll_timeout - Periodically poll a PHY register until a
+ *                             condition is met or a timeout occurs
+ *
+ * @phydev: The phy_device struct
+ * @devaddr: The MMD to read from
+ * @regnum: The register on the MMD to read
+ * @val: Variable to read the register into
+ * @cond: Break condition (usually involving @val)
+ * @sleep_us: Maximum time to sleep between reads in us (0
+ *            tight-loops).  Should be less than ~20ms since usleep_range
+ *            is used (see Documentation/timers/timers-howto.rst).
+ * @timeout_us: Timeout in us, 0 means never timeout
+ * @sleep_before_read: if it is true, sleep @sleep_us before read.
+ * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
+ * case, the last read value at @args is stored in @val. Must not
+ * be called from atomic context if sleep_us or timeout_us are used.
+ */
+#define phy_read_mmd_poll_timeout(phydev, devaddr, regnum, val, cond, \
+				  sleep_us, timeout_us, sleep_before_read) \
+({ \
+	int __ret = read_poll_timeout(phy_read_mmd, val, (cond) || val < 0, \
+				  sleep_us, timeout_us, \
+				  phydev, devaddr, regnum); \
+	if (val <  0) \
+		__ret = val; \
+	if (__ret) \
+		dev_err(phydev->dev, "%s failed: %d\n", __func__, __ret); \
+	__ret; \
+})
+
 int phy_read(struct phy_device *phydev, int devad, int regnum);
 int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val);
 void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum);
@@ -295,11 +320,14 @@ int phy_read_mmd(struct phy_device *phydev, int devad, int regnum);
 int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val);
 int phy_set_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
 int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val);
+int phy_modify_mmd_changed(struct phy_device *phydev, int devad, u32 regnum,
+			   u16 mask, u16 set);
+int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
+		   u16 mask, u16 set);
 
 int phy_startup(struct phy_device *phydev);
 int phy_config(struct phy_device *phydev);
 int phy_shutdown(struct phy_device *phydev);
-int phy_register(struct phy_driver *drv);
 int phy_set_supported(struct phy_device *phydev, u32 max_speed);
 int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
 	       u16 set);
@@ -315,35 +343,12 @@ int gen10g_startup(struct phy_device *phydev);
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
-int phy_b53_init(void);
-int phy_mv88e61xx_init(void);
-int phy_adin_init(void);
-int phy_aquantia_init(void);
-int phy_atheros_init(void);
-int phy_broadcom_init(void);
-int phy_cortina_init(void);
-int phy_cortina_access_init(void);
-int phy_davicom_init(void);
-int phy_et1011c_init(void);
-int phy_lxt_init(void);
-int phy_marvell_init(void);
-int phy_micrel_ksz8xxx_init(void);
-int phy_micrel_ksz90x1_init(void);
-int phy_meson_gxl_init(void);
-int phy_natsemi_init(void);
-int phy_nxp_c45_tja11xx_init(void);
-int phy_nxp_tja11xx_init(void);
-int phy_realtek_init(void);
-int phy_smsc_init(void);
-int phy_teranetics_init(void);
-int phy_ti_init(void);
-int phy_vitesse_init(void);
-int phy_xilinx_init(void);
-int phy_xway_init(void);
-int phy_mscc_init(void);
-int phy_fixed_init(void);
-int phy_ncsi_init(void);
-int phy_xilinx_gmii2rgmii_init(void);
+/**
+ * U_BOOT_PHY_DRIVER() - Declare a new U-Boot driver
+ * @__name: name of the driver
+ */
+#define U_BOOT_PHY_DRIVER(__name)					\
+	ll_entry_declare(struct phy_driver, __name, phy_driver)
 
 int board_phy_config(struct phy_device *phydev);
 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
@@ -356,20 +361,15 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
  */
 static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
 {
-	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
-		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
-}
-
-/**
- * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
- * is SGMII (all variants)
- * @phydev: the phy_device struct
- * @return: true if MII bus is SGMII or false if it is not
- */
-static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
-{
-	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
-		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+	switch (phydev->interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		return 1;
+	default:
+		return 0;
+	}
 }
 
 bool phy_interface_is_ncsi(void);
diff --git a/include/phy_interface.h b/include/phy_interface.h
index fed3357b9a2..31be3228c7c 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -14,63 +14,95 @@
 
 typedef enum {
 	PHY_INTERFACE_MODE_NA, /* don't touch */
+	PHY_INTERFACE_MODE_INTERNAL,
 	PHY_INTERFACE_MODE_MII,
 	PHY_INTERFACE_MODE_GMII,
 	PHY_INTERFACE_MODE_SGMII,
-	PHY_INTERFACE_MODE_SGMII_2500,
-	PHY_INTERFACE_MODE_QSGMII,
 	PHY_INTERFACE_MODE_TBI,
+	PHY_INTERFACE_MODE_REVMII,
 	PHY_INTERFACE_MODE_RMII,
+	PHY_INTERFACE_MODE_REVRMII,
 	PHY_INTERFACE_MODE_RGMII,
 	PHY_INTERFACE_MODE_RGMII_ID,
 	PHY_INTERFACE_MODE_RGMII_RXID,
 	PHY_INTERFACE_MODE_RGMII_TXID,
 	PHY_INTERFACE_MODE_RTBI,
+	PHY_INTERFACE_MODE_SMII,
+	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_XLGMII,
+	PHY_INTERFACE_MODE_MOCA,
+	PHY_INTERFACE_MODE_QSGMII,
+	PHY_INTERFACE_MODE_TRGMII,
+	PHY_INTERFACE_MODE_100BASEX,
 	PHY_INTERFACE_MODE_1000BASEX,
 	PHY_INTERFACE_MODE_2500BASEX,
-	PHY_INTERFACE_MODE_XGMII,
-	PHY_INTERFACE_MODE_XAUI,
+	PHY_INTERFACE_MODE_5GBASER,
 	PHY_INTERFACE_MODE_RXAUI,
-	PHY_INTERFACE_MODE_SFI,
-	PHY_INTERFACE_MODE_INTERNAL,
+	PHY_INTERFACE_MODE_XAUI,
+	/* 10GBASE-R, XFI, SFI - single lane 10G Serdes */
+	PHY_INTERFACE_MODE_10GBASER,
+	PHY_INTERFACE_MODE_25GBASER,
+	PHY_INTERFACE_MODE_USXGMII,
+	/* 10GBASE-KR - with Clause 73 AN */
+	PHY_INTERFACE_MODE_10GKR,
+	PHY_INTERFACE_MODE_QUSGMII,
+	PHY_INTERFACE_MODE_1000BASEKX,
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
+	/* LX2160A SERDES modes */
 	PHY_INTERFACE_MODE_25G_AUI,
 	PHY_INTERFACE_MODE_XLAUI,
 	PHY_INTERFACE_MODE_CAUI2,
 	PHY_INTERFACE_MODE_CAUI4,
+#endif
+#if defined(CONFIG_PHY_NCSI)
 	PHY_INTERFACE_MODE_NCSI,
-	PHY_INTERFACE_MODE_10GBASER,
-	PHY_INTERFACE_MODE_USXGMII,
+#endif
 	PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
 static const char * const phy_interface_strings[] = {
-	[PHY_INTERFACE_MODE_NA]		= "",
+	[PHY_INTERFACE_MODE_NA]			= "",
+	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
 	[PHY_INTERFACE_MODE_MII]		= "mii",
 	[PHY_INTERFACE_MODE_GMII]		= "gmii",
 	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
-	[PHY_INTERFACE_MODE_SGMII_2500]		= "sgmii-2500",
-	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
 	[PHY_INTERFACE_MODE_TBI]		= "tbi",
+	[PHY_INTERFACE_MODE_REVMII]		= "rev-mii",
 	[PHY_INTERFACE_MODE_RMII]		= "rmii",
+	[PHY_INTERFACE_MODE_REVRMII]		= "rev-rmii",
 	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
 	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
 	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
 	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
 	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
+	[PHY_INTERFACE_MODE_SMII]		= "smii",
+	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
+	[PHY_INTERFACE_MODE_XLGMII]		= "xlgmii",
+	[PHY_INTERFACE_MODE_MOCA]		= "moca",
+	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
+	[PHY_INTERFACE_MODE_TRGMII]		= "trgmii",
 	[PHY_INTERFACE_MODE_1000BASEX]		= "1000base-x",
+	[PHY_INTERFACE_MODE_1000BASEKX]		= "1000base-kx",
 	[PHY_INTERFACE_MODE_2500BASEX]		= "2500base-x",
-	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
-	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
+	[PHY_INTERFACE_MODE_5GBASER]		= "5gbase-r",
 	[PHY_INTERFACE_MODE_RXAUI]		= "rxaui",
-	[PHY_INTERFACE_MODE_SFI]		= "sfi",
-	[PHY_INTERFACE_MODE_INTERNAL]		= "internal",
+	[PHY_INTERFACE_MODE_XAUI]		= "xaui",
+	[PHY_INTERFACE_MODE_10GBASER]		= "10gbase-r",
+	[PHY_INTERFACE_MODE_25GBASER]		= "25gbase-r",
+	[PHY_INTERFACE_MODE_USXGMII]		= "usxgmii",
+	[PHY_INTERFACE_MODE_10GKR]		= "10gbase-kr",
+	[PHY_INTERFACE_MODE_100BASEX]		= "100base-x",
+	[PHY_INTERFACE_MODE_QUSGMII]		= "qusgmii",
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
+	/* LX2160A SERDES modes */
 	[PHY_INTERFACE_MODE_25G_AUI]		= "25g-aui",
 	[PHY_INTERFACE_MODE_XLAUI]		= "xlaui4",
 	[PHY_INTERFACE_MODE_CAUI2]		= "caui2",
 	[PHY_INTERFACE_MODE_CAUI4]		= "caui4",
+#endif
+#if defined(CONFIG_PHY_NCSI)
 	[PHY_INTERFACE_MODE_NCSI]		= "NC-SI",
-	[PHY_INTERFACE_MODE_10GBASER]		= "10gbase-r",
-	[PHY_INTERFACE_MODE_USXGMII]		= "usxgmii",
+#endif
 };
 
 /* Backplane modes:
diff --git a/include/pxe_utils.h b/include/pxe_utils.h
index 1e5e8424f53..9f195930487 100644
--- a/include/pxe_utils.h
+++ b/include/pxe_utils.h
@@ -93,6 +93,7 @@ typedef int (*pxe_getfile_func)(struct pxe_context *ctx, const char *file_path,
  * @bootdir: Directory that files are loaded from ("" if no directory). This is
  *	allocated
  * @pxe_file_size: Size of the PXE file
+ * @use_ipv6: TRUE : use IPv6 addressing, FALSE : use IPv4 addressing
  */
 struct pxe_context {
 	struct cmd_tbl *cmdtp;
@@ -112,6 +113,7 @@ struct pxe_context {
 	bool allow_abs_path;
 	char *bootdir;
 	ulong pxe_file_size;
+	bool use_ipv6;
 };
 
 /**
@@ -209,12 +211,14 @@ int format_mac_pxe(char *outbuf, size_t outbuf_len);
  * @allow_abs_path: true to allow absolute paths
  * @bootfile: Bootfile whose directory loaded files are relative to, NULL if
  *	none
+ * @use_ipv6: TRUE : use IPv6 addressing
+ *            FALSE : use IPv4 addressing
  * Return: 0 if OK, -ENOMEM if out of memory, -E2BIG if bootfile is larger than
  *	MAX_TFTP_PATH_LEN bytes
  */
 int pxe_setup_ctx(struct pxe_context *ctx, struct cmd_tbl *cmdtp,
 		  pxe_getfile_func getfile, void *userdata,
-		  bool allow_abs_path, const char *bootfile);
+		  bool allow_abs_path, const char *bootfile, bool use_ipv6);
 
 /**
  * pxe_destroy_ctx() - Destroy a PXE context
@@ -251,7 +255,9 @@ int pxe_get_file_size(ulong *sizep);
  *	"rpi/info", which indicates that all files should be fetched from the
  *	"rpi/" subdirectory
  * @sizep: Size of the PXE file (not bootfile)
+ * @use_ipv6: TRUE : use IPv6 addressing
+ *            FALSE : use IPv4 addressing
  */
-int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep);
+int pxe_get(ulong pxefile_addr_r, char **bootdirp, ulong *sizep, bool use_ipv6);
 
 #endif /* __PXE_UTILS_H */
diff --git a/include/splash.h b/include/splash.h
index 33e45e69416..c3922375987 100644
--- a/include/splash.h
+++ b/include/splash.h
@@ -49,7 +49,7 @@ struct splash_location {
 	char *ubivol;	/* UBI volume-name for ubifsmount */
 };
 
-#ifdef CONFIG_SPLASH_SOURCE
+#if CONFIG_IS_ENABLED(SPLASH_SOURCE)
 int splash_source_load(struct splash_location *locations, uint size);
 #else
 static inline int splash_source_load(struct splash_location *locations,
@@ -60,21 +60,8 @@ static inline int splash_source_load(struct splash_location *locations,
 #endif
 
 int splash_screen_prepare(void);
-
-#ifdef CONFIG_SPLASH_SCREEN_ALIGN
 void splash_get_pos(int *x, int *y);
-#else
-static inline void splash_get_pos(int *x, int *y) { }
-#endif
-
-#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_CMD_BMP)
 int splash_display(void);
-#else
-static inline int splash_display(void)
-{
-	return -ENOSYS;
-}
-#endif
 
 #define BMP_ALIGN_CENTER	0x7FFF
 
diff --git a/include/tlv_eeprom.h b/include/tlv_eeprom.h
index a2c333e7446..fd45e5f6ebb 100644
--- a/include/tlv_eeprom.h
+++ b/include/tlv_eeprom.h
@@ -84,11 +84,12 @@ int read_tlv_eeprom(void *eeprom, int offset, int len, int dev);
  * write_tlv_eeprom - Write the entire EEPROM binary data to the hardware
  * @eeprom: Pointer to buffer to hold the binary data
  * @len   : Maximum size of buffer
+ * @dev   : EEPROM device to write
  *
  * Note: this routine does not validate the EEPROM data.
  *
  */
-int write_tlv_eeprom(void *eeprom, int len);
+int write_tlv_eeprom(void *eeprom, int len, int dev);
 
 /**
  * read_tlvinfo_tlv_eeprom - Read the TLV from EEPROM, and validate
diff --git a/include/video.h b/include/video.h
index 4d99e5dc27f..29c4f51efb0 100644
--- a/include/video.h
+++ b/include/video.h
@@ -357,4 +357,12 @@ void *video_get_u_boot_logo(void);
  */
 int bmp_display(ulong addr, int x, int y);
 
+/*
+ * bmp_info() - Show information about bmp file
+ *
+ * @addr: address of bmp file
+ * Returns: 0 if OK, else 1 if bmp image not found
+ */
+int bmp_info(ulong addr);
+
 #endif
diff --git a/include/virtio_ring.h b/include/virtio_ring.h
index c77c212cffd..e8e91044a27 100644
--- a/include/virtio_ring.h
+++ b/include/virtio_ring.h
@@ -86,6 +86,8 @@ struct vring_used {
 
 struct vring {
 	unsigned int num;
+	size_t size;
+	struct bounce_buffer *bouncebufs;
 	struct vring_desc *desc;
 	struct vring_avail *avail;
 	struct vring_used *used;
@@ -137,23 +139,26 @@ struct virtqueue {
 #define vring_used_event(vr)	((vr)->avail->ring[(vr)->num])
 #define vring_avail_event(vr)	(*(__virtio16 *)&(vr)->used->ring[(vr)->num])
 
+static inline unsigned int vring_size(unsigned int num, unsigned long align)
+{
+	return ((sizeof(struct vring_desc) * num +
+		sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
+		sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
+}
+
 static inline void vring_init(struct vring *vr, unsigned int num, void *p,
-			      unsigned long align)
+			      unsigned long align,
+			      struct bounce_buffer *bouncebufs)
 {
 	vr->num = num;
+	vr->size = vring_size(num, align);
+	vr->bouncebufs = bouncebufs;
 	vr->desc = p;
 	vr->avail = p + num * sizeof(struct vring_desc);
 	vr->used = (void *)(((uintptr_t)&vr->avail->ring[num] +
 		   sizeof(__virtio16) + align - 1) & ~(align - 1));
 }
 
-static inline unsigned int vring_size(unsigned int num, unsigned long align)
-{
-	return ((sizeof(struct vring_desc) * num +
-		sizeof(__virtio16) * (3 + num)  + align - 1) & ~(align - 1)) +
-		sizeof(__virtio16) * 3 + sizeof(struct vring_used_elem) * num;
-}
-
 /*
  * The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX.
  * Assuming a given event_idx value from the other side, if we have just
author	Tom Rini <[email protected]>	2023-05-08 14:31:04 -0400
committer	Tom Rini <[email protected]>	2023-05-08 14:31:04 -0400
commit	11910550b65e6072b9542d462c0aa93f4ca81836 (patch)
tree	8308c98ffad76d9693654a28090b03f270a7d250 /include
parent	9876c8c147144db2c120fcc9ffa6de27f6894441 (diff)
parent	f1d33a44ca04fdca241c1d89fd79e2e56c930c7e (diff)