diff options
| author | Tom Rini <[email protected]> | 2023-12-19 15:16:13 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-12-20 08:12:56 -0500 |
| commit | 1f115bdeb804b34a6456fd1f5907ffc98a2977ba (patch) | |
| tree | e155297a5e4ce7b08c7a0d9802bb032ab2427c34 /include | |
| parent | 936d0f9dd713a913fe952eae576c893e1d5ecbd1 (diff) | |
| parent | 4989628c1d2b6ea19a38aae34b1c08b12141c64b (diff) | |
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
This PR contains 4 patchsets:
1. PMIC GPIO cells bringup. Created drivers for MAX7663 and Palmas
PMICs and gpio-uclass patch isolated behind configs for these 2
drivers. No unintentional size increase on any board. (proposed
2023-11-06 without any reaction)
2. Simple PLL clocks support in common tegra clock code which allows
use of simple PLL the same way main PLLs are used (before only
clock_start_pll was available). PLLD2 is an example of simple PLL, it
is used as a video subsystem parent clock and was used to test this
code. So far everything worked as expected. (proposed 2023-11-16
without any reaction)
3. A small patch for tegra emmc to allow pass max frequency from
device tree since some devices may not support full speed.
4. Pinmux DM conversion. Patchset consists of commit with DM wrapper
for existing pinmux code for t20/t30/t114, pinmux and funcmux files
relocation into a dedicated folder inside pinctrl, conversion of some
tegra boards to device tree pinmux setup.
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/x3-t30.h | 13 | ||||
| -rw-r--r-- | include/dt-bindings/pmic/max77663.h | 18 | ||||
| -rw-r--r-- | include/power/max77663.h | 1 | ||||
| -rw-r--r-- | include/power/palmas.h | 12 |
4 files changed, 32 insertions, 12 deletions
diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index d29ea700b2e..14532542ea6 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -14,19 +14,8 @@ #include "tegra30-common.h" -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - -#ifdef CONFIG_DEVICE_P880 /* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus 4X HD" -#endif - -#ifdef CONFIG_DEVICE_P895 -/* High-level configuration options */ -#undef CFG_TEGRA_BOARD_STRING -#define CFG_TEGRA_BOARD_STRING "LG Optimus Vu" -#endif +#define CFG_TEGRA_BOARD_STRING "LG X3 Board" #define X3_FLASH_UBOOT \ "flash_uboot=echo Preparing RAM;" \ diff --git a/include/dt-bindings/pmic/max77663.h b/include/dt-bindings/pmic/max77663.h new file mode 100644 index 00000000000..ee169a83e3b --- /dev/null +++ b/include/dt-bindings/pmic/max77663.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright(C) 2023 Svyatoslav Ryhel <[email protected]> + */ + +#ifndef _DT_BINDINGS_MAX77663_H_ +#define _DT_BINDINGS_MAX77663_H_ + +/* + * MAX77663 has 8 GPIO (0 to 7) and 3 KEYS + * KEYS are appended after GPIOs + */ + +#define EN0 10 +#define ACOK 9 +#define LID 8 + +#endif diff --git a/include/power/max77663.h b/include/power/max77663.h index b3ae3dabf46..fcb5916f27e 100644 --- a/include/power/max77663.h +++ b/include/power/max77663.h @@ -13,6 +13,7 @@ #define MAX77663_LDO_DRIVER "max77663_ldo" #define MAX77663_SD_DRIVER "max77663_sd" #define MAX77663_RST_DRIVER "max77663_rst" +#define MAX77663_GPIO_DRIVER "max77663_gpio" /* Step-Down (SD) Regulator calculations */ #define SD_STATUS_MASK 0x30 diff --git a/include/power/palmas.h b/include/power/palmas.h index 0a612052f01..94c99dd4113 100644 --- a/include/power/palmas.h +++ b/include/power/palmas.h @@ -15,6 +15,7 @@ struct palmas_priv { #define PALMAS_LDO_DRIVER "palmas_ldo" #define PALMAS_SMPS_DRIVER "palmas_smps" #define PALMAS_RST_DRIVER "palmas_rst" +#define PALMAS_GPIO_DRIVER "palmas_gpio" #define PALMAS_SMPS_VOLT_MASK 0x7F #define PALMAS_SMPS_RANGE_MASK 0x80 @@ -35,3 +36,14 @@ struct palmas_priv { #define DEV_OFF 0x00 #define PALMAS_INT3_MASK 0x1B #define MASK_VBUS BIT(7) + +/* second chip */ +#define PALMAS_GPIO_DATA_IN 0x80 +#define PALMAS_GPIO_DATA_DIR 0x81 +#define PALMAS_GPIO_DATA_OUT 0x82 +#define PALMAS_GPIO_DEBOUNCE_EN 0x83 +#define PALMAS_GPIO_CLEAR_DATA_OUT 0x84 +#define PALMAS_GPIO_SET_DATA_OUT 0x85 +#define PALMAS_PU_PD_GPIO_CTRL1 0x86 +#define PALMAS_PU_PD_GPIO_CTRL2 0x87 +#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x88 |
