diff options
| author | Paul Barker <[email protected]> | 2024-11-20 09:48:28 +0000 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2024-12-08 23:06:52 +0100 |
| commit | 215663f5e47db92c6c13107e877a943c3e70aa2a (patch) | |
| tree | aa64a1752922b779f1752c38f24586cf4d7d1572 /include | |
| parent | 2b1a5efca8891ea320c23acd3681ca8bdb7fd15b (diff) | |
pinctrl: rzg2l: Support 2.5V PVDD for Ethernet interfaces
The Ethenet interfaces on the Renesas RZ/G2L SoC family can operate at
multiple power supply voltages: 3.3V (default value), 2.5V and 1.8V.
rzg2l_pinconf_set() is extended to support the 2.5V setting, with a
check to ensure this is only used on Ethernet interfaces as it is not
supported on the SD & QSPI interfaces.
While we're modifying rzg2l_pinconf_set(), drop the unnecessary default
value for pwr_reg as it is set in every branch of the following if
condition.
Signed-off-by: Paul Barker <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/renesas/rzg2l-pfc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/renesas/rzg2l-pfc.h b/include/renesas/rzg2l-pfc.h index 2df17ece2a3..d1015b1d2ac 100644 --- a/include/renesas/rzg2l-pfc.h +++ b/include/renesas/rzg2l-pfc.h @@ -77,9 +77,11 @@ #define IEN(n) (0x1800 + (n) * 8) #define PWPR 0x3014 #define SD_CH(n) (0x3000 + (n) * 4) +#define ETH_POC(ch) (0x300c + (ch) * 4) #define QSPI 0x3008 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ |