clk: altera: agilex: Exclude AGILEX_L4_SYS_FREE_CLK from enable/disable operations

AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.

Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.

This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.

Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>

0 files changed, 0 insertions, 0 deletions