diff options
| author | Akshay Saraswat <[email protected]> | 2013-03-22 02:26:36 +0000 |
|---|---|---|
| committer | Minkyu Kang <[email protected]> | 2013-05-21 20:17:30 +0900 |
| commit | 234370cab4b2f096e095fe8f3284fd39740a4023 (patch) | |
| tree | 1ce12817aa13a62f65562f5b9191de5956e4a892 /include | |
| parent | c7c4fe072eeb95852f4a015df3c1a39b37caae51 (diff) | |
Exynos5: clock: Update the equation to calculate PLL output frequency
According to the latest exynos5 user manual, the equation for
calculating PLL output was changed to
FOUT= MDIV x FIN/(PDIV x 2^SDIV)
earlier it was
FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1))
So updating the clock code accordingly.
Signed-off-by: Hatim Ali <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions