diff options
| author | Tom Rini <[email protected]> | 2023-06-12 14:55:33 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-06-12 14:55:33 -0400 |
| commit | 260d4962e06c0a7d2713523c131416a3f70d7f2c (patch) | |
| tree | 14b9d414810e97f1ffdfdaf099db57a5bbf45a79 /include | |
| parent | 5b589e139620214f26eb83c9fb7bbd62b5f8fc1d (diff) | |
| parent | 19b77d3d23966a0d6dbb3c86187765f11100fb6f (diff) | |
Merge tag v2023.07-rc4 into next
Signed-off-by: Tom Rini <[email protected]>
Diffstat (limited to 'include')
37 files changed, 2497 insertions, 66 deletions
diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 4030d25c66a..7ed0443c821 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -923,6 +923,14 @@ int acpi_fill_csrt(struct acpi_ctx *ctx); */ ulong write_acpi_tables(ulong start); +/** + * acpi_find_table() - Look up an ACPI table + * + * @sig: Signature of table (4 characters, upper case) + * Return: pointer to table header, or NULL if not found + */ +struct acpi_table_header *acpi_find_table(const char *sig); + #endif /* !__ACPI__*/ #include <asm/acpi_table.h> diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 65bf8df1e56..a1e1b9d6400 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -457,7 +457,7 @@ struct global_data { */ fdt_addr_t translation_offset; #endif -#ifdef CONFIG_GENERATE_ACPI_TABLE +#ifdef CONFIG_ACPI /** * @acpi_ctx: ACPI context pointer */ @@ -536,7 +536,7 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_dm_priv_base() NULL #endif -#ifdef CONFIG_GENERATE_ACPI_TABLE +#ifdef CONFIG_ACPI #define gd_acpi_ctx() gd->acpi_ctx #define gd_acpi_start() gd->acpi_start #define gd_set_acpi_start(addr) gd->acpi_start = addr diff --git a/include/bootmeth.h b/include/bootmeth.h index b12dfd42c90..c3df9702e87 100644 --- a/include/bootmeth.h +++ b/include/bootmeth.h @@ -255,7 +255,7 @@ int bootmeth_setup_iter_order(struct bootflow_iter *iter, bool include_global); * This selects the ordering to use for bootmeths * * @order_str: String containing the ordering. This is a comma-separate list of - * bootmeth-device names, e.g. "syslinux,efi". If empty then a default ordering + * bootmeth-device names, e.g. "extlinux,efi". If empty then a default ordering * is used, based on the sequence number of devices (i.e. using aliases) * Return: 0 if OK, -ENODEV if an unknown bootmeth is mentioned, -ENOMEM if * out of memory, -ENOENT if there are no bootmeth devices diff --git a/include/configs/anbernic-rgxx3-rk3566.h b/include/configs/anbernic-rgxx3-rk3566.h new file mode 100644 index 00000000000..3c4ea4e7d84 --- /dev/null +++ b/include/configs/anbernic-rgxx3-rk3566.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ANBERNIC_RGXX3_RK3566_H +#define __ANBERNIC_RGXX3_RK3566_H + +#include <configs/rk3568_common.h> + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 7b7bef3ca75..2705587a015 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -131,8 +131,6 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CFG_SYS_FSL_USDHC_NUM 2 - /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR diff --git a/include/configs/rzn1-snarc.h b/include/configs/rzn1-snarc.h new file mode 100644 index 00000000000..9fee2ece54a --- /dev/null +++ b/include/configs/rzn1-snarc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the Schneider RZ/N1 board + */ + +#ifndef __RZN1_SNARC_H +#define __RZN1_SNARC_H + +/* Internal RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE (1 * 1024 * 1024) + +#endif /* __RZN1_SNARC_H */ diff --git a/include/dm/fdtaddr.h b/include/dm/fdtaddr.h index c9d2b27ba6e..dcdc19137cc 100644 --- a/include/dm/fdtaddr.h +++ b/include/dm/fdtaddr.h @@ -111,7 +111,7 @@ void *devfdt_get_addr_index_ptr(const struct udevice *dev, int index); * @dev: Pointer to a device * @index: the 'reg' property can hold a list of <addr, size> pairs * and @index is used to select which one is required - * @size: Pointer to size varible - this function returns the size + * @size: Pointer to size variable - this function returns the size * specified in the 'reg' property here * * Return: addr @@ -120,6 +120,21 @@ fdt_addr_t devfdt_get_addr_size_index(const struct udevice *dev, int index, fdt_size_t *size); /** + * devfdt_get_addr_size_index_ptr() - Return indexed pointer to the address of the + * reg property of a device + * + * @dev: Pointer to a device + * @index: the 'reg' property can hold a list of <addr, size> pairs + * and @index is used to select which one is required + * @size: Pointer to size variable - this function returns the size + * specified in the 'reg' property here + * + * Return: Pointer to addr, or NULL if there is no such property + */ +void *devfdt_get_addr_size_index_ptr(const struct udevice *dev, int index, + fdt_size_t *size); + +/** * devfdt_get_addr_name() - Get the reg property of a device, indexed by name * * @dev: Pointer to a device diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index c00677275ee..443db6252dd 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -678,8 +678,8 @@ int ofnode_read_size(ofnode node, const char *propname); * @size: Pointer to size of the address * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, - fdt_size_t *size); +fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, + fdt_size_t *size); /** * ofnode_get_addr_size_index_notrans() - get an address/size from a node @@ -695,8 +695,8 @@ phys_addr_t ofnode_get_addr_size_index(ofnode node, int index, * @size: Pointer to size of the address * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, - fdt_size_t *size); +fdt_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, + fdt_size_t *size); /** * ofnode_get_addr_index() - get an address from a node @@ -707,7 +707,7 @@ phys_addr_t ofnode_get_addr_size_index_notrans(ofnode node, int index, * @index: Index of address to read (0 for first) * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr_index(ofnode node, int index); +fdt_addr_t ofnode_get_addr_index(ofnode node, int index); /** * ofnode_get_addr() - get an address from a node @@ -717,7 +717,7 @@ phys_addr_t ofnode_get_addr_index(ofnode node, int index); * @node: node to read from * Return: address, or FDT_ADDR_T_NONE if not present or invalid */ -phys_addr_t ofnode_get_addr(ofnode node); +fdt_addr_t ofnode_get_addr(ofnode node); /** * ofnode_get_size() - get size from a node @@ -1067,8 +1067,8 @@ const void *ofprop_get_property(const struct ofprop *prop, * @sizep: place to put size value (on success) * Return: address value, or FDT_ADDR_T_NONE on error */ -phys_addr_t ofnode_get_addr_size(ofnode node, const char *propname, - phys_size_t *sizep); +fdt_addr_t ofnode_get_addr_size(ofnode node, const char *propname, + fdt_size_t *sizep); /** * ofnode_read_u8_array_ptr() - find an 8-bit array diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 4ea6864b418..8e02859d8ce 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ OR MIT */ /* - * Copyright 2021 NXP + * Copyright 2022 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H @@ -28,13 +28,9 @@ #define IMX93_CLK_M33_SYSTICK 19 #define IMX93_CLK_FLEXIO1 20 #define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPIT1 22 -#define IMX93_CLK_LPIT2 23 #define IMX93_CLK_LPTMR1 24 #define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM1 26 #define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM3 28 #define IMX93_CLK_TPM4 29 #define IMX93_CLK_TPM5 30 #define IMX93_CLK_TPM6 31 @@ -197,7 +193,12 @@ #define IMX93_CLK_PMRO_GATE 188 #define IMX93_CLK_32K 189 #define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_END 193 +#define IMX93_CLK_SAI2_IPG 191 +#define IMX93_CLK_SAI3_IPG 192 +#define IMX93_CLK_MU1_A_GATE 193 +#define IMX93_CLK_MU1_B_GATE 194 +#define IMX93_CLK_MU2_A_GATE 195 +#define IMX93_CLK_MU2_B_GATE 196 +#define IMX93_CLK_END 197 + #endif diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h new file mode 100644 index 00000000000..d9d7b8b4f42 --- /dev/null +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R9A06G032 sysctrl IDs + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <[email protected]>, <[email protected]> + */ + +#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ + +#define R9A06G032_CLK_PLL_USB 1 +#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ +#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ +#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ +#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ +#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ +#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ +#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ +#define R9A06G032_CLK_25_PG4 26 +#define R9A06G032_CLK_25_PG5 27 +#define R9A06G032_CLK_25_PG6 28 +#define R9A06G032_CLK_25_PG7 29 +#define R9A06G032_CLK_25_PG8 30 +#define R9A06G032_CLK_ADC 31 +#define R9A06G032_CLK_ECAT100 32 +#define R9A06G032_CLK_HSR100 33 +#define R9A06G032_CLK_I2C0 34 +#define R9A06G032_CLK_I2C1 35 +#define R9A06G032_CLK_MII_REF 36 +#define R9A06G032_CLK_NAND 37 +#define R9A06G032_CLK_NOUSBP2_PG6 38 +#define R9A06G032_CLK_P1_PG2 39 +#define R9A06G032_CLK_P1_PG3 40 +#define R9A06G032_CLK_P1_PG4 41 +#define R9A06G032_CLK_P4_PG3 42 +#define R9A06G032_CLK_P4_PG4 43 +#define R9A06G032_CLK_P6_PG1 44 +#define R9A06G032_CLK_P6_PG2 45 +#define R9A06G032_CLK_P6_PG3 46 +#define R9A06G032_CLK_P6_PG4 47 +#define R9A06G032_CLK_PCI_USB 48 +#define R9A06G032_CLK_QSPI0 49 +#define R9A06G032_CLK_QSPI1 50 +#define R9A06G032_CLK_RGMII_REF 51 +#define R9A06G032_CLK_RMII_REF 52 +#define R9A06G032_CLK_SDIO0 53 +#define R9A06G032_CLK_SDIO1 54 +#define R9A06G032_CLK_SERCOS100 55 +#define R9A06G032_CLK_SLCD 56 +#define R9A06G032_CLK_SPI0 57 +#define R9A06G032_CLK_SPI1 58 +#define R9A06G032_CLK_SPI2 59 +#define R9A06G032_CLK_SPI3 60 +#define R9A06G032_CLK_SPI4 61 +#define R9A06G032_CLK_SPI5 62 +#define R9A06G032_CLK_SWITCH 63 +#define R9A06G032_HCLK_ECAT125 65 +#define R9A06G032_HCLK_PINCONFIG 66 +#define R9A06G032_HCLK_SERCOS 67 +#define R9A06G032_HCLK_SGPIO2 68 +#define R9A06G032_HCLK_SGPIO3 69 +#define R9A06G032_HCLK_SGPIO4 70 +#define R9A06G032_HCLK_TIMER0 71 +#define R9A06G032_HCLK_TIMER1 72 +#define R9A06G032_HCLK_USBF 73 +#define R9A06G032_HCLK_USBH 74 +#define R9A06G032_HCLK_USBPM 75 +#define R9A06G032_CLK_48_PG_F 76 +#define R9A06G032_CLK_48_PG4 77 +#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ +#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ +#define R9A06G032_HCLK_CAN0 85 +#define R9A06G032_HCLK_CAN1 86 +#define R9A06G032_HCLK_DELTASIGMA 87 +#define R9A06G032_HCLK_PWMPTO 88 +#define R9A06G032_HCLK_RSV 89 +#define R9A06G032_HCLK_SGPIO0 90 +#define R9A06G032_HCLK_SGPIO1 91 +#define R9A06G032_RTOS_MDC 92 +#define R9A06G032_CLK_CM3 93 +#define R9A06G032_CLK_DDRC 94 +#define R9A06G032_CLK_ECAT25 95 +#define R9A06G032_CLK_HSR50 96 +#define R9A06G032_CLK_HW_RTOS 97 +#define R9A06G032_CLK_SERCOS50 98 +#define R9A06G032_HCLK_ADC 99 +#define R9A06G032_HCLK_CM3 100 +#define R9A06G032_HCLK_CRYPTO_EIP150 101 +#define R9A06G032_HCLK_CRYPTO_EIP93 102 +#define R9A06G032_HCLK_DDRC 103 +#define R9A06G032_HCLK_DMA0 104 +#define R9A06G032_HCLK_DMA1 105 +#define R9A06G032_HCLK_GMAC0 106 +#define R9A06G032_HCLK_GMAC1 107 +#define R9A06G032_HCLK_GPIO0 108 +#define R9A06G032_HCLK_GPIO1 109 +#define R9A06G032_HCLK_GPIO2 110 +#define R9A06G032_HCLK_HSR 111 +#define R9A06G032_HCLK_I2C0 112 +#define R9A06G032_HCLK_I2C1 113 +#define R9A06G032_HCLK_LCD 114 +#define R9A06G032_HCLK_MSEBI_M 115 +#define R9A06G032_HCLK_MSEBI_S 116 +#define R9A06G032_HCLK_NAND 117 +#define R9A06G032_HCLK_PG_I 118 +#define R9A06G032_HCLK_PG19 119 +#define R9A06G032_HCLK_PG20 120 +#define R9A06G032_HCLK_PG3 121 +#define R9A06G032_HCLK_PG4 122 +#define R9A06G032_HCLK_QSPI0 123 +#define R9A06G032_HCLK_QSPI1 124 +#define R9A06G032_HCLK_ROM 125 +#define R9A06G032_HCLK_RTC 126 +#define R9A06G032_HCLK_SDIO0 127 +#define R9A06G032_HCLK_SDIO1 128 +#define R9A06G032_HCLK_SEMAP 129 +#define R9A06G032_HCLK_SPI0 130 +#define R9A06G032_HCLK_SPI1 131 +#define R9A06G032_HCLK_SPI2 132 +#define R9A06G032_HCLK_SPI3 133 +#define R9A06G032_HCLK_SPI4 134 +#define R9A06G032_HCLK_SPI5 135 +#define R9A06G032_HCLK_SWITCH 136 +#define R9A06G032_HCLK_SWITCH_RG 137 +#define R9A06G032_HCLK_UART0 138 +#define R9A06G032_HCLK_UART1 139 +#define R9A06G032_HCLK_UART2 140 +#define R9A06G032_HCLK_UART3 141 +#define R9A06G032_HCLK_UART4 142 +#define R9A06G032_HCLK_UART5 143 +#define R9A06G032_HCLK_UART6 144 +#define R9A06G032_HCLK_UART7 145 +#define R9A06G032_CLK_UART0 146 +#define R9A06G032_CLK_UART1 147 +#define R9A06G032_CLK_UART2 148 +#define R9A06G032_CLK_UART3 149 +#define R9A06G032_CLK_UART4 150 +#define R9A06G032_CLK_UART5 151 +#define R9A06G032_CLK_UART6 152 +#define R9A06G032_CLK_UART7 153 + +#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/pinctrl/rzn1-pinctrl.h b/include/dt-bindings/pinctrl/rzn1-pinctrl.h new file mode 100644 index 00000000000..21d6cc4d59f --- /dev/null +++ b/include/dt-bindings/pinctrl/rzn1-pinctrl.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/N1 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_RZN1_PINCTRL_H +#define __DT_BINDINGS_RZN1_PINCTRL_H + +#define RZN1_PINMUX(_gpio, _func) \ + (((_func) << 8) | (_gpio)) + +/* + * Given the different levels of muxing on the SoC, it was decided to + * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO + * muxes are all represented by one single value. + * + * You can derive the hardware value pretty easily too, as + * 0...9 are Level 1 + * 10...71 are Level 2. The Level 2 mux will be set to this + * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be + * set accordingly. + * 72...103 are for the 2 MDIO muxes. + */ +#define RZN1_FUNC_HIGHZ 0 +#define RZN1_FUNC_0L 1 +#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 +#define RZN1_FUNC_CLK_ETH_NAND 3 +#define RZN1_FUNC_QSPI 4 +#define RZN1_FUNC_SDIO 5 +#define RZN1_FUNC_LCD 6 +#define RZN1_FUNC_LCD_E 7 +#define RZN1_FUNC_MSEBIM 8 +#define RZN1_FUNC_MSEBIS 9 +#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ + +#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) +#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) +#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) +#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) +#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) +#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) +#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) +#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) +#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) +#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) +#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) +#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) +#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) +#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) +#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) +#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) +#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) +#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) +#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) +#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) +#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) +#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) +#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) +#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) +#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) +#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) +#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) +#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) +#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) +#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) +#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) +#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) +#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) +#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) +#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) +#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) +#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) +#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) +#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) +#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) +#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) +#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) +#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) +#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) +#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) +#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) +#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) +#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) +#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) +#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) +#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) +#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) +#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) +#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) +#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) +#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) +#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) +#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) +#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) +#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) +#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) +#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) + +#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) + +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) +#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) +#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) +#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) +#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) +#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) +#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) +#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) +#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) +#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) +#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) +#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) +#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) + +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) +#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) +#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) +#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) +#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) +#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) +#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) +#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) +#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) +#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) +#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) +#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) +#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) + +#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) + +#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h new file mode 100644 index 00000000000..17f9f015bf7 --- /dev/null +++ b/include/dt-bindings/power/fsl,imx93-power.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DT_BINDINGS_IMX93_POWER_H__ +#define __DT_BINDINGS_IMX93_POWER_H__ + +#define IMX93_MEDIABLK_PD_MIPI_DSI 0 +#define IMX93_MEDIABLK_PD_MIPI_CSI 1 +#define IMX93_MEDIABLK_PD_PXP 2 +#define IMX93_MEDIABLK_PD_LCDIF 3 +#define IMX93_MEDIABLK_PD_ISI 4 + +#endif diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h deleted file mode 100644 index 4e27a2e2809..00000000000 --- a/include/dt-bindings/power/imx93-power.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2021 NXP - */ - -#ifndef __DT_BINDINGS_IMX93_POWER_H__ -#define __DT_BINDINGS_IMX93_POWER_H__ - -#define IMX93_POWER_DOMAIN_MLMIX 0 -#define IMX93_POWER_DOMAIN_MEDIAMIX 1 - -#endif diff --git a/include/efi_api.h b/include/efi_api.h index 2fd0221c1c7..55a4c989fc7 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -1170,7 +1170,33 @@ struct efi_key_descriptor { struct efi_hii_keyboard_layout { u16 layout_length; - efi_guid_t guid; + /* + * The EFI spec defines this as efi_guid_t. + * clang and gcc both report alignment problems here. + * clang with -Wunaligned-access + * warning: field guid within 'struct efi_hii_keyboard_layout' is less + * aligned than 'efi_guid_t' and is usually due to + * 'struct efi_hii_keyboard_layout' being packed, which can lead to + * unaligned accesses + * + * GCC with -Wpacked-not-aligned -Waddress-of-packed-member + * 'efi_guid_t' offset 2 in 'struct efi_hii_keyboard_layout' + * isn't aligned to 4 + * + * Removing the alignment from efi_guid_t is not an option, since + * it is also used in non-packed structs and that would break + * calculations with offsetof + * + * This is the only place we get a report for. That happens because + * all other declarations of efi_guid_t within a packed struct happens + * to be 4-byte aligned. i.e a u32, a u64 a 2 * u16 or any combination + * that ends up landing efi_guid_t on a 4byte boundary precedes. + * + * Replace this with a 1-byte aligned counterpart of b[16]. This is a + * packed struct so the memory placement of efi_guid_t should not change + * + */ + u8 guid[16]; u32 layout_descriptor_string_offset; u8 descriptor_count; /* struct efi_key_descriptor descriptors[]; follows here */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 941d63467ce..11e08a804f7 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -810,7 +810,7 @@ bool efi_dp_is_multi_instance(const struct efi_device_path *dp); struct efi_device_path *efi_dp_from_part(struct blk_desc *desc, int part); /* Create a device node for a block device partition. */ struct efi_device_path *efi_dp_part_node(struct blk_desc *desc, int part); -struct efi_device_path *efi_dp_from_file(struct blk_desc *desc, int part, +struct efi_device_path *efi_dp_from_file(const struct efi_device_path *dp, const char *path); struct efi_device_path *efi_dp_from_eth(void); struct efi_device_path *efi_dp_from_mem(uint32_t mem_type, diff --git a/include/env_default.h b/include/env_default.h index c0df39d62f9..b16c22d5a28 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -10,9 +10,7 @@ #include <env_callback.h> #include <linux/stringify.h> -#ifndef USE_HOSTCC #include <generated/environment.h> -#endif #ifdef DEFAULT_ENV_INSTANCE_EMBEDDED env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { diff --git a/include/environment/ti/k3_rproc.env b/include/environment/ti/k3_rproc.env index 21dad7b2412..87d9d76eba4 100644 --- a/include/environment/ti/k3_rproc.env +++ b/include/environment/ti/k3_rproc.env @@ -7,14 +7,14 @@ boot_rprocs= rproc_load_and_boot_one= if load mmc ${bootpart} $loadaddr ${rproc_fw}; then if rproc load ${rproc_id} ${loadaddr} ${filesize}; then - rproc start ${rproc_id} + rproc start ${rproc_id}; fi; fi boot_rprocs_mmc= env set rproc_id; env set rproc_fw; for i in ${rproc_fw_binaries} ; do - if test -z ${rproc_id} ; then + if test -z "${rproc_id}" ; then env set rproc_id $i; else env set rproc_fw $i; diff --git a/include/event.h b/include/event.h index e4580b68350..fe41080fa63 100644 --- a/include/event.h +++ b/include/event.h @@ -22,7 +22,7 @@ enum event_t { EVT_TEST, /* Events related to driver model */ - EVT_DM_POST_INIT, + EVT_DM_POST_INIT_F, EVT_DM_PRE_PROBE, EVT_DM_POST_PROBE, EVT_DM_PRE_REMOVE, diff --git a/include/distro.h b/include/extlinux.h index 2ee145871b2..721ba46371c 100644 --- a/include/distro.h +++ b/include/extlinux.h @@ -4,18 +4,18 @@ * Written by Simon Glass <[email protected]> */ -#ifndef __distro_h -#define __distro_h +#ifndef __extlinux_h +#define __extlinux_h -#define DISTRO_FNAME "extlinux/extlinux.conf" +#define EXTLINUX_FNAME "extlinux/extlinux.conf" /** - * struct distro_info - useful information for distro_getfile() + * struct extlinux_info - useful information for extlinux_getfile() * * @dev: bootmethod device being used to boot * @bflow: bootflow being booted */ -struct distro_info { +struct extlinux_info { struct udevice *dev; struct bootflow *bflow; struct cmd_tbl *cmdtp; diff --git a/include/fdtdec.h b/include/fdtdec.h index 6716da9c659..bd1149f46d0 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -18,15 +18,18 @@ #include <pci.h> /* - * A typedef for a physical address. Note that fdt data is always big + * Support for 64bit fdt addresses. + * This can be used not only for 64bit SoCs, but also + * for large address extensions on 32bit SoCs. + * Note that fdt data is always big * endian even on a litle endian machine. */ -typedef phys_addr_t fdt_addr_t; -typedef phys_size_t fdt_size_t; #define FDT_SIZE_T_NONE (-1U) -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_FDT_64BIT +typedef u64 fdt_addr_t; +typedef u64 fdt_size_t; #define FDT_ADDR_T_NONE ((ulong)(-1)) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) @@ -35,6 +38,8 @@ typedef phys_size_t fdt_size_t; #define cpu_to_fdt_size(reg) cpu_to_be64(reg) typedef fdt64_t fdt_val_t; #else +typedef u32 fdt_addr_t; +typedef u32 fdt_size_t; #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h new file mode 100644 index 00000000000..39de7f0e3e0 --- /dev/null +++ b/include/firmware/imx/sci/rpc.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2018 NXP + * + */ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Note: Check SCFW API Released DOC before you want to modify something */ +/* Defines */ + +#define SCFW_API_VERSION_MAJOR 1U +#define SCFW_API_VERSION_MINOR 21U + +#define SC_RPC_VERSION 1U + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MSG) ((MSG)->version) +#define RPC_SIZE(MSG) ((MSG)->size) +#define RPC_SVC(MSG) ((MSG)->svc) +#define RPC_FUNC(MSG) ((MSG)->func) +#define RPC_R8(MSG) ((MSG)->func) +#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (s64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (u64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) + +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_SECO 9U +#define SC_RPC_SVC_ABORT 10U + + +/* Types */ + +struct sc_rpc_msg_s { + u8 version; + u8 size; + u8 svc; + u8 func; + union { + s32 i32[(SC_RPC_MAX_MSG - 1U)]; + s16 i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + s8 i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + u32 u32[(SC_RPC_MAX_MSG - 1U)]; + u16 u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + u8 u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +}; + +/* PM RPC */ +#define PM_FUNC_UNKNOWN 0 +#define PM_FUNC_SET_SYS_POWER_MODE 19U +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U +#define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U +#define PM_FUNC_REQ_LOW_POWER_MODE 16U +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U +#define PM_FUNC_SET_CPU_RESUME 21U +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U +#define PM_FUNC_SET_CLOCK_RATE 5U +#define PM_FUNC_GET_CLOCK_RATE 6U +#define PM_FUNC_CLOCK_ENABLE 7U +#define PM_FUNC_SET_CLOCK_PARENT 14U +#define PM_FUNC_GET_CLOCK_PARENT 15U +#define PM_FUNC_RESET 13U +#define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_BOOT 8U +#define PM_FUNC_REBOOT 9U +#define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_CPU_START 11U +#define PM_FUNC_CPU_RESET 23U +#define PM_FUNC_RESOURCE_RESET 29U +#define PM_FUNC_IS_PARTITION_STARTED 24U + +/* MISC RPC */ +#define MISC_FUNC_UNKNOWN 0 +#define MISC_FUNC_SET_CONTROL 1U +#define MISC_FUNC_GET_CONTROL 2U +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U +#define MISC_FUNC_SET_DMA_GROUP 5U +#define MISC_FUNC_SECO_IMAGE_LOAD 8U +#define MISC_FUNC_SECO_AUTHENTICATE 9U +#define MISC_FUNC_SECO_FUSE_WRITE 20U +#define MISC_FUNC_SECO_ENABLE_DEBUG 21U +#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U +#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U +#define MISC_FUNC_SECO_BUILD_INFO 24U +#define MISC_FUNC_DEBUG_OUT 10U +#define MISC_FUNC_WAVEFORM_CAPTURE 6U +#define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_UNIQUE_ID 19U +#define MISC_FUNC_SET_ARI 3U +#define MISC_FUNC_BOOT_STATUS 7U +#define MISC_FUNC_BOOT_DONE 14U +#define MISC_FUNC_OTP_FUSE_READ 11U +#define MISC_FUNC_OTP_FUSE_WRITE 17U +#define MISC_FUNC_SET_TEMP 12U +#define MISC_FUNC_GET_TEMP 13U +#define MISC_FUNC_GET_BOOT_DEV 16U +#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_GET_BOOT_CONTAINER 36U + +/* PAD RPC */ +#define PAD_FUNC_UNKNOWN 0 +#define PAD_FUNC_SET_MUX 1U +#define PAD_FUNC_GET_MUX 6U +#define PAD_FUNC_SET_GP 2U +#define PAD_FUNC_GET_GP 7U +#define PAD_FUNC_SET_WAKEUP 4U +#define PAD_FUNC_GET_WAKEUP 9U +#define PAD_FUNC_SET_ALL 5U +#define PAD_FUNC_GET_ALL 10U +#define PAD_FUNC_SET 15U +#define PAD_FUNC_GET 16U +#define PAD_FUNC_SET_GP_28FDSOI 11U +#define PAD_FUNC_GET_GP_28FDSOI 12U +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U + +/* RM RPC */ +#define RM_FUNC_UNKNOWN 0 +#define RM_FUNC_PARTITION_ALLOC 1U +#define RM_FUNC_SET_CONFIDENTIAL 31U +#define RM_FUNC_PARTITION_FREE 2U +#define RM_FUNC_GET_DID 26U +#define RM_FUNC_PARTITION_STATIC 3U +#define RM_FUNC_PARTITION_LOCK 4U +#define RM_FUNC_GET_PARTITION 5U +#define RM_FUNC_SET_PARENT 6U +#define RM_FUNC_MOVE_ALL 7U +#define RM_FUNC_ASSIGN_RESOURCE 8U +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U +#define RM_FUNC_SET_MASTER_SID 11U +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U +#define RM_FUNC_IS_RESOURCE_OWNED 13U +#define RM_FUNC_GET_RESOURCE_OWNER 33U +#define RM_FUNC_IS_RESOURCE_MASTER 14U +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U +#define RM_FUNC_GET_RESOURCE_INFO 16U +#define RM_FUNC_MEMREG_ALLOC 17U +#define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FREE 18U +#define RM_FUNC_FIND_MEMREG 30U +#define RM_FUNC_ASSIGN_MEMREG 19U +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U +#define RM_FUNC_IS_MEMREG_OWNED 21U +#define RM_FUNC_GET_MEMREG_INFO 22U +#define RM_FUNC_ASSIGN_PAD 23U +#define RM_FUNC_SET_PAD_MOVABLE 24U +#define RM_FUNC_IS_PAD_OWNED 25U +#define RM_FUNC_DUMP 27U + +/* SECO RPC */ +#define SECO_FUNC_UNKNOWN 0 /* Unknown function */ +#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */ +#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */ +#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */ +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */ +#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */ +#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */ +#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */ +#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */ +#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */ +#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */ +#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */ +#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */ +#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */ +#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */ +#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ +#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ +#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ +#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ +#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ +#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */ +#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */ +#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */ +#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */ +#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */ +#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */ +#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */ + +/* IRQ RPC */ +#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */ +#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */ + +/* TIMER RPC */ +#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ + +#endif /* SC_RPC_H */ diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h new file mode 100644 index 00000000000..61c8211b443 --- /dev/null +++ b/include/firmware/imx/sci/sci.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SC_SCI_H +#define _SC_SCI_H + +#include <log.h> +#include <firmware/imx/sci/types.h> +#include <firmware/imx/sci/svc/misc/api.h> +#include <firmware/imx/sci/svc/pad/api.h> +#include <firmware/imx/sci/svc/pm/api.h> +#include <firmware/imx/sci/svc/rm/api.h> +#include <firmware/imx/sci/svc/seco/api.h> +#include <firmware/imx/sci/rpc.h> +#include <dt-bindings/soc/imx_rsrc.h> +#include <linux/errno.h> + +static inline int sc_err_to_linux(sc_err_t err) +{ + int ret; + + switch (err) { + case SC_ERR_NONE: + return 0; + case SC_ERR_VERSION: + case SC_ERR_CONFIG: + case SC_ERR_PARM: + ret = -EINVAL; + break; + case SC_ERR_NOACCESS: + case SC_ERR_LOCKED: + case SC_ERR_UNAVAILABLE: + ret = -EACCES; + break; + case SC_ERR_NOTFOUND: + case SC_ERR_NOPOWER: + ret = -ENODEV; + break; + case SC_ERR_IPC: + ret = -EIO; + break; + case SC_ERR_BUSY: + ret = -EBUSY; + break; + case SC_ERR_FAIL: + ret = -EIO; + break; + default: + ret = 0; + break; + } + + debug("%s %d %d\n", __func__, err, ret); + + return ret; +} + +#if IS_ENABLED(CONFIG_IMX8) +/* PM API*/ +int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); +int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); +int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); +int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog); +int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clk_parent_t parent); +int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); + +/* MISC API */ +int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, u32 val); +int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, + u32 *val); +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); +void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); +int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); +int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + s16 *celsius, s8 *tenths); + +/* RM API */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); +int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end); +int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); +int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end); +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); +int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent); +int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); +int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); +int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); +int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); +int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/* PAD API */ +int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); +int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/* SMMU API */ +int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); + +/* SECO API */ +int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr); +int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); +int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, + u32 *uid_h); +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); +int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size); +int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); +int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); +int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size); +#else +/* PM API*/ +static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clk_parent_t parent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + return false; +} + +static inline int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource) +{ + return -EOPNOTSUPP; +} + +/* MISC API */ +static inline int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev) +{ +} + +static inline void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) +{ +} + +static inline int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) +{ + return -EOPNOTSUPP; +} + +static inline void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit) +{ +} + +static inline int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + s16 *celsius, s8 *tenths) +{ + return -EOPNOTSUPP; +} + +/* RM API */ +static inline sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + return true; +} + +static inline int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_pt_t pt, + sc_rm_perm_t perm) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, + sc_faddr_t *addr_end) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) +{ + return true; +} + +static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource) +{ + return -EOPNOTSUPP; +} + +static inline int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + return -EOPNOTSUPP; +} + +static inline sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + return true; +} + +static inline int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_pt_t *pt) +{ + return -EOPNOTSUPP; +} + +/* PAD API */ +static inline int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val) +{ + return -EOPNOTSUPP; +} + +static inline int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) +{ + return -EOPNOTSUPP; +} + +/* SMMU API */ +static inline int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +{ + return -EOPNOTSUPP; +} + +/* SECO API */ +static inline int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h) +{ + return -EOPNOTSUPP; +} + +void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ +} + +static inline int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, + sc_faddr_t export_addr, u16 max_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size, + sc_faddr_t dst_addr, u16 dst_size) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) +{ + return -EOPNOTSUPP; +} + +static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1, + u32 *data2, u32 *data3, u32 *data4, u8 size) +{ + return -EOPNOTSUPP; +} + +#endif + +#endif diff --git a/include/firmware/imx/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h new file mode 100644 index 00000000000..3629eb68d7a --- /dev/null +++ b/include/firmware/imx/sci/svc/misc/api.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Defines for sc_misc_boot_status_t */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ +#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ + +/* Defines for sc_misc_temp_t */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_seco_auth_cmd_t */ +#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ +#define SC_MISC_REL_CONTAINER 2U /* Release container */ + +typedef u8 sc_misc_boot_status_t; +typedef u8 sc_misc_temp_t; + +#endif /* SC_MISC_API_H */ diff --git a/include/firmware/imx/sci/svc/pad/api.h b/include/firmware/imx/sci/svc/pad/api.h new file mode 100644 index 00000000000..df368e8c8b5 --- /dev/null +++ b/include/firmware/imx/sci/svc/pad/api.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Defines for type widths */ +#define SC_PAD_MUX_W 3U /* Width of mux parameter */ + +/* Defines for sc_pad_config_t */ +#define SC_PAD_CONFIG_NORMAL 0U /* Normal */ +#define SC_PAD_CONFIG_OD 1U /* Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */ + +/* Defines for sc_pad_iso_t */ +#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /* ISO latched data is held */ + +/* Defines for sc_pad_28fdsoi_dse_t */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength dual volt */ + +/* Defines for sc_pad_28fdsoi_ps_t */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */ + +/* Defines for sc_pad_28fdsoi_pus_t */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */ + +/* Defines for sc_pad_wakeup_t */ +#define SC_PAD_WAKEUP_OFF 0U /* Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */ + +#endif /* SC_PAD_API_H */ diff --git a/include/firmware/imx/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h new file mode 100644 index 00000000000..9008b85c6f6 --- /dev/null +++ b/include/firmware/imx/sci/svc/pm/api.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Defines for sc_pm_power_mode_t */ +#define SC_PM_PW_MODE_OFF 0U /* Power off */ +#define SC_PM_PW_MODE_STBY 1U /* Power in standby */ +#define SC_PM_PW_MODE_LP 2U /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /* Power on */ + +/* Defines for sc_pm_clk_t */ +#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */ +#define SC_PM_CLK_PER 2U /* Peripheral clock */ +#define SC_PM_CLK_PHY 3U /* Phy clock */ +#define SC_PM_CLK_MISC 4U /* Misc clock */ +#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /* CPU clock */ +#define SC_PM_CLK_PLL 4U /* PLL */ +#define SC_PM_CLK_BYPASS 4U /* Bypass clock */ + +/* Defines for sc_pm_clk_mode_t */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ + +typedef u8 sc_pm_power_mode_t; +typedef u8 sc_pm_clk_t; +typedef u8 sc_pm_clk_mode_t; +typedef u8 sc_pm_clk_parent_t; +typedef u32 sc_pm_clock_rate_t; + +#endif /* SC_PM_API_H */ diff --git a/include/firmware/imx/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h new file mode 100644 index 00000000000..163d81403c5 --- /dev/null +++ b/include/firmware/imx/sci/svc/rm/api.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +#include <firmware/imx/sci/types.h> + +/* Defines for type widths */ +#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */ + +/* Defines for ALL parameters */ +#define SC_RM_PT_ALL ((sc_rm_pt_t)UINT8_MAX) /* All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t)UINT8_MAX) /* All memory regions */ + +/* Defines for sc_rm_spa_t */ +#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */ + +/* Defines for sc_rm_perm_t */ +#define SC_RM_PERM_NONE 0U /* No access */ +#define SC_RM_PERM_SEC_R 1U /* Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /* Full access */ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef u8 sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef u8 sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef u8 sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef u16 sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef u8 sc_rm_spa_t; + +typedef u8 sc_rm_perm_t; + +#endif /* SC_RM_API_H */ diff --git a/include/firmware/imx/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h new file mode 100644 index 00000000000..6e9c302315b --- /dev/null +++ b/include/firmware/imx/sci/svc/seco/api.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include <firmware/imx/sci/types.h> + +/* Defines */ +#define SC_SECO_AUTH_CONTAINER 0U /* Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /* Verify image */ +#define SC_SECO_REL_CONTAINER 2U /* Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ + +#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ +#define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ +#define SC_SECO_RNG_STAT_READY 2U /* Initialized */ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef u8 sc_seco_auth_cmd_t; + +/*! + * This type is used to return the RNG initialization status. + */ +typedef u32 sc_seco_rng_stat_t; + +#endif /* SC_SECO_API_H */ diff --git a/include/firmware/imx/sci/types.h b/include/firmware/imx/sci/types.h new file mode 100644 index 00000000000..adfed13e330 --- /dev/null +++ b/include/firmware/imx/sci/types.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ +#include <linux/types.h> + +/* Defines */ +/* + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef u64 sc_ipc_t; + +/* Defines for common frequencies */ +#define SC_32KHZ 32768U /* 32KHz */ +#define SC_10MHZ 10000000U /* 10MHz */ +#define SC_20MHZ 20000000U /* 20MHz */ +#define SC_25MHZ 25000000U /* 25MHz */ +#define SC_27MHZ 27000000U /* 27MHz */ +#define SC_40MHZ 40000000U /* 40MHz */ +#define SC_45MHZ 45000000U /* 45MHz */ +#define SC_50MHZ 50000000U /* 50MHz */ +#define SC_60MHZ 60000000U /* 60MHz */ +#define SC_66MHZ 66666666U /* 66MHz */ +#define SC_74MHZ 74250000U /* 74.25MHz */ +#define SC_80MHZ 80000000U /* 80MHz */ +#define SC_83MHZ 83333333U /* 83MHz */ +#define SC_84MHZ 84375000U /* 84.37MHz */ +#define SC_100MHZ 100000000U /* 100MHz */ +#define SC_114MHZ 114000000U /* 114MHz */ +#define SC_125MHZ 125000000U /* 125MHz */ +#define SC_133MHZ 133333333U /* 133MHz */ +#define SC_135MHZ 135000000U /* 135MHz */ +#define SC_150MHZ 150000000U /* 150MHz */ +#define SC_160MHZ 160000000U /* 160MHz */ +#define SC_166MHZ 166666666U /* 166MHz */ +#define SC_175MHZ 175000000U /* 175MHz */ +#define SC_180MHZ 180000000U /* 180MHz */ +#define SC_200MHZ 200000000U /* 200MHz */ +#define SC_250MHZ 250000000U /* 250MHz */ +#define SC_266MHZ 266666666U /* 266MHz */ +#define SC_300MHZ 300000000U /* 300MHz */ +#define SC_312MHZ 312500000U /* 312.5MHZ */ +#define SC_320MHZ 320000000U /* 320MHz */ +#define SC_325MHZ 325000000U /* 325MHz */ +#define SC_333MHZ 333333333U /* 333MHz */ +#define SC_350MHZ 350000000U /* 350MHz */ +#define SC_372MHZ 372000000U /* 372MHz */ +#define SC_375MHZ 375000000U /* 375MHz */ +#define SC_400MHZ 400000000U /* 400MHz */ +#define SC_465MHZ 465000000U /* 465MHz */ +#define SC_500MHZ 500000000U /* 500MHz */ +#define SC_594MHZ 594000000U /* 594MHz */ +#define SC_625MHZ 625000000U /* 625MHz */ +#define SC_640MHZ 640000000U /* 640MHz */ +#define SC_650MHZ 650000000U /* 650MHz */ +#define SC_667MHZ 666666667U /* 667MHz */ +#define SC_675MHZ 675000000U /* 675MHz */ +#define SC_700MHZ 700000000U /* 700MHz */ +#define SC_720MHZ 720000000U /* 720MHz */ +#define SC_750MHZ 750000000U /* 750MHz */ +#define SC_800MHZ 800000000U /* 800MHz */ +#define SC_850MHZ 850000000U /* 850MHz */ +#define SC_900MHZ 900000000U /* 900MHz */ +#define SC_1000MHZ 1000000000U /* 1GHz */ +#define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1188MHZ 1188000000U /* 1.188GHz */ +#define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1280MHZ 1280000000U /* 1.28GHz */ +#define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1400MHZ 1400000000U /* 1.4GHz */ +#define SC_1500MHZ 1500000000U /* 1.5GHz */ +#define SC_1600MHZ 1600000000U /* 1.6GHz */ +#define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_1860MHZ 1860000000U /* 1.86GHz */ +#define SC_2000MHZ 2000000000U /* 2.0GHz */ +#define SC_2112MHZ 2112000000U /* 2.12GHz */ + +/* Defines for 24M related frequencies */ +#define SC_8MHZ 8000000U /* 8MHz */ +#define SC_12MHZ 12000000U /* 12MHz */ +#define SC_19MHZ 19800000U /* 19.8MHz */ +#define SC_24MHZ 24000000U /* 24MHz */ +#define SC_48MHZ 48000000U /* 48MHz */ +#define SC_120MHZ 120000000U /* 120MHz */ +#define SC_132MHZ 132000000U /* 132MHz */ +#define SC_144MHZ 144000000U /* 144MHz */ +#define SC_192MHZ 192000000U /* 192MHz */ +#define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_228MHZ 228000000U /* 233MHz */ +#define SC_240MHZ 240000000U /* 240MHz */ +#define SC_264MHZ 264000000U /* 264MHz */ +#define SC_352MHZ 352000000U /* 352MHz */ +#define SC_360MHZ 360000000U /* 360MHz */ +#define SC_384MHZ 384000000U /* 384MHz */ +#define SC_396MHZ 396000000U /* 396MHz */ +#define SC_432MHZ 432000000U /* 432MHz */ +#define SC_456MHZ 456000000U /* 466MHz */ +#define SC_480MHZ 480000000U /* 480MHz */ +#define SC_600MHZ 600000000U /* 600MHz */ +#define SC_744MHZ 744000000U /* 744MHz */ +#define SC_792MHZ 792000000U /* 792MHz */ +#define SC_864MHZ 864000000U /* 864MHz */ +#define SC_912MHZ 912000000U /* 912MHz */ +#define SC_960MHZ 960000000U /* 960MHz */ +#define SC_1056MHZ 1056000000U /* 1056MHz */ +#define SC_1104MHZ 1104000000U /* 1104MHz */ +#define SC_1200MHZ 1200000000U /* 1.2GHz */ +#define SC_1464MHZ 1464000000U /* 1.464GHz */ +#define SC_2400MHZ 2400000000U /* 2.4GHz */ + +/* Defines for A/V related frequencies */ +#define SC_62MHZ 62937500U /* 62.9375MHz */ +#define SC_755MHZ 755250000U /* 755.25MHz */ + +/* Defines for type widths */ +#define SC_FADDR_W 36U /* Width of sc_faddr_t */ +#define SC_BOOL_W 1U /* Width of sc_bool_t */ +#define SC_ERR_W 4U /* Width of sc_err_t */ +#define SC_RSRC_W 10U /* Width of sc_rsrc_t */ +#define SC_CTRL_W 6U /* Width of sc_ctrl_t */ + +/* Defines for sc_bool_t */ +#define SC_FALSE ((sc_bool_t)0U) +#define SC_TRUE ((sc_bool_t)1U) + +/* Defines for sc_err_t */ +#define SC_ERR_NONE 0U /* Success */ +#define SC_ERR_VERSION 1U /* Incompatible API version */ +#define SC_ERR_CONFIG 2U /* Configuration error */ +#define SC_ERR_PARM 3U /* Bad parameter */ +#define SC_ERR_NOACCESS 4U /* Permission error (no access) */ +#define SC_ERR_LOCKED 5U /* Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /* Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /* Not found */ +#define SC_ERR_NOPOWER 8U /* No power */ +#define SC_ERR_IPC 9U /* Generic IPC error */ +#define SC_ERR_BUSY 10U /* Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /* General I/O failure */ +#define SC_ERR_LAST 12U + +/* Defines for sc_ctrl_t. */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_LAST 46U + +#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ + +/* Types */ + +/* This type is used to store a boolean */ +typedef u8 sc_bool_t; + +/* This type is used to store a system (full-size) address. */ +typedef u64 sc_faddr_t; + +/* This type is used to indicate error response for most functions. */ +typedef u8 sc_err_t; + +/* + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef u16 sc_rsrc_t; + +/* This type is used to indicate a control. */ +typedef u8 sc_ctrl_t; + +/* + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef u16 sc_pad_t; + +#endif /* SC_TYPES_H */ diff --git a/include/flash.h b/include/flash.h index 95992fa689b..3710a2731b7 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,6 +46,7 @@ typedef struct { #ifdef CONFIG_CFI_FLASH /* DM-specific parts */ struct udevice *dev; phys_addr_t base; + phys_size_t addr_size; #endif } flash_info_t; diff --git a/include/image.h b/include/image.h index 456197d6fda..01a6787d211 100644 --- a/include/image.h +++ b/include/image.h @@ -230,6 +230,7 @@ enum image_type_t { IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */ IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ + IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/regmap.h b/include/regmap.h index e81a3602aea..22b043408ac 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -378,17 +378,18 @@ int regmap_init_mem(ofnode node, struct regmap **mapp); * * @dev: Device that uses this map * @reg: List of address, size pairs + * @size: Size of one reg array item * @count: Number of pairs (e.g. 1 if the regmap has a single entry) * @mapp: Returns allocated map * Return: 0 if OK, -ve on error * * This creates a new regmap with a list of regions passed in, rather than - * using the device tree. It only supports 32-bit machines. + * using the device tree. * * Use regmap_uninit() to free it. * */ -int regmap_init_mem_plat(struct udevice *dev, fdt_val_t *reg, int count, +int regmap_init_mem_plat(struct udevice *dev, void *reg, int size, int count, struct regmap **mapp); int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); diff --git a/include/renesas/ddr_ctrl.h b/include/renesas/ddr_ctrl.h new file mode 100644 index 00000000000..77d7915b2b5 --- /dev/null +++ b/include/renesas/ddr_ctrl.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Cadence DDR Controller + * + * Copyright (C) 2015 Renesas Electronics Europe Ltd + */ + +#ifndef CADENCE_DDR_CTRL_H +#define CADENCE_DDR_CTRL_H + +enum cdns_ddr_range_prot { + CDNS_DDR_RANGE_PROT_BITS_PRIV_SECURE = 0, + CDNS_DDR_RANGE_PROT_BITS_SECURE = 1, + CDNS_DDR_RANGE_PROT_BITS_PRIV = 2, + CDNS_DDR_RANGE_PROT_BITS_FULL = 3, +}; + +/** + * Initialise the Cadence DDR Controller, but doesn't start it. + * + * It sets up the controller so that all 4 AXI slave ports allow access to all + * of the DDR with the same settings. This means that: + * - Full access permisions. + * - All read/write priorities are set to 2. + * - Bandwidth is set to 50%, overflow is allowed, i.e. it's a soft limit. + * If you want different properties for different ports and/or addr ranges, call + * the other functions before calling cdns_ddr_ctrl_start(). + * + * @ddr_ctrl_base Physical address of the DDR Controller. + * @async 0 if DDR clock is synchronous with the controller clock + * otherwise 1. + * @reg0 Pointer to array of 32-bit values to be written to registers + * 0 to 87. The values are generated by Cadence TCL scripts. + * @reg350 Pointer to array of 32-bit values to be written to registers + * 350 to 374. The values are generated by Cadence TCL scripts. + * @ddr_start_addr Physical address of the start of DDR. + * @ddr_size Size of the DDR in bytes. The controller will set the port + * protection range to match this size. + * @enable_ecc 0 to disable ECC, 1 to enable it. + * @enable_8bit 0 to use 16-bit bus width, 1 to use 8-bit bus width. + */ +void cdns_ddr_ctrl_init(void *ddr_ctrl_base, int async, + const u32 *reg0, const u32 *reg350, + u32 ddr_start_addr, u32 ddr_size, + int enable_ecc, int enable_8bit); + +/** + * Start the Cadence DDR Controller. + * + * @ddr_ctrl_base Physical address of the DDR Controller. + */ +void cdns_ddr_ctrl_start(void *ddr_ctrl_base); + +/** + * Set the priority for read and write operations for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @read_pri Priority for reads. Range is 0 to 3, where 0 is highest priority. + * @write_pri Priority for writes. Range is 0 to 3, where 0 is highest priority. + */ +void cdns_ddr_set_port_rw_priority(void *base, int port, + u8 read_pri, u8 write_pri); + +/** + * Specify address range for a protection entry, for a specific AXI slave port. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_port_addr_range(void *base, int port, int entry, + u32 addr_start, u32 size); + +/** + * Specify address range for a protection entry, for all AXI slave ports. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + * @start_addr Physical of the address range, must be aligned to 16KB. + * @size Size of the address range, must be multiple of 16KB. + */ +void cdns_ddr_enable_addr_range(void *base, int entry, + u32 addr_start, u32 size); + +/** + * Specify protection entry details, for a specific AXI slave port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_port_prot(void *base, int port, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify protection entry details, for all AXI slave ports. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @entry The protection entry. Range is 0 to 15. + */ +void cdns_ddr_enable_prot(void *base, int entry, + enum cdns_ddr_range_prot range_protection_bits, + u16 range_RID_check_bits, + u16 range_WID_check_bits, + u8 range_RID_check_bits_ID_lookup, + u8 range_WID_check_bits_ID_lookup); + +/** + * Specify bandwidth for each AXI port. + * + * See the hardware manual for details of the range check bits. + * + * @base Physical address of the DDR Controller. + * @port Port number. Range is 0 to 3. + * @max_percent 0 to 100. + */ +void cdns_ddr_set_port_bandwidth(void *base, int port, + u8 max_percent, u8 overflow_ok); + +/* Standard JEDEC registers */ +#define MODE_REGISTER_MASK (3 << 14) +#define MODE_REGISTER_MR0 (0 << 14) +#define MODE_REGISTER_MR1 (1 << 14) +#define MODE_REGISTER_MR2 (2 << 14) +#define MODE_REGISTER_MR3 (3 << 14) +#define MR1_DRIVE_STRENGTH_MASK ((1 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_34_OHMS ((0 << 5) | (1 << 1)) +#define MR1_DRIVE_STRENGTH_40_OHMS ((0 << 5) | (0 << 1)) +#define MR1_ODT_IMPEDANCE_MASK ((1 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_60_OHMS ((0 << 9) | (0 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_120_OHMS ((0 << 9) | (1 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_40_OHMS ((0 << 9) | (1 << 6) | (1 << 2)) +#define MR1_ODT_IMPEDANCE_20_OHMS ((1 << 9) | (0 << 6) | (0 << 2)) +#define MR1_ODT_IMPEDANCE_30_OHMS ((1 << 9) | (0 << 6) | (1 << 2)) +#define MR2_DYNAMIC_ODT_MASK (3 << 9) +#define MR2_DYNAMIC_ODT_OFF (0 << 9) +#define MR2_SELF_REFRESH_TEMP_MASK (1 << 7) +#define MR2_SELF_REFRESH_TEMP_EXT (1 << 7) + +/** + * Set certain fields of the JEDEC MR1 register. + */ +void cdns_ddr_set_mr1(void *base, int cs, u16 odt_impedance, u16 drive_strength); + +/** + * Set certain fields of the JEDEC MR2 register. + */ +void cdns_ddr_set_mr2(void *base, int cs, u16 dynamic_odt, u16 self_refresh_temp); + +/** + * Set ODT map of the DDR Controller. + */ +void cdns_ddr_set_odt_map(void *base, int cs, u16 odt_map); + +/** + * Set ODT settings in the DDR Controller. + */ +void cdns_ddr_set_odt_times(void *base, u8 TODTL_2CMD, u8 TODTH_WR, u8 TODTH_RD, + u8 WR_TO_ODTH, u8 RD_TO_ODTH); + +void cdns_ddr_set_same_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); +void cdns_ddr_set_diff_cs_delays(void *base, u8 r2r, u8 r2w, u8 w2r, u8 w2w); + +#endif diff --git a/include/renesas/is43tr16256a_125k_CTL.h b/include/renesas/is43tr16256a_125k_CTL.h new file mode 100644 index 00000000000..fabc2c7b793 --- /dev/null +++ b/include/renesas/is43tr16256a_125k_CTL.h @@ -0,0 +1,419 @@ + +/* **************************************************************** + * CADENCE Copyright (c) 2001-2011 * + * Cadence Design Systems, Inc. * + * All rights reserved. * + * * + ****************************************************************** + * The values calculated from this script are meant to be * + * representative programmings. The values may not reflect the * + * actual required programming for production use. Please * + * closely review all programmed values for technical accuracy * + * before use in production parts. * + ****************************************************************** + * + * Module: regconfig.h + * Documentation: Register programming header file + * + ****************************************************************** + ****************************************************************** + * WARNING: This file was automatically generated. Manual + * editing may result in undetermined behavior. + ****************************************************************** + ******************************************************************/ +// REL: renesas.germany-LCES_DDR__2014-05-21 + +// ******************************************************************** +// Option: IP : IP Mode = CTL +// Option: BL : Burst Length = 8 +// Option: CL : CAS Latency = 8 +// Option: MHZ : Simulation MHz = 500 +// Option: AP : Auto Precharge Mode (0/1) = 0 +// Option: DLLBP : DLL Bypass Mode (0/1) = 1 +// Option: HALF : Half-Memory Support (0/1) = 0 +// Option: RDIMM : Registered Dimm Support (0/1) = 0 +// Option: AL : Additive Latency = 0 +// Option: RSV3 : Reserved (0) = 0 +// Option: TCK : Simulation period in ns = +// Option: RDDBIEN : Read DBI Enable (0/1) = 0 +// Option: SOMA : Memory-SOMA file(s) = is43tr16256a_125k_xml.soma +// ******************************************************************** +// Memory: is43tr16256a_125k_xml.soma +// ******************************************************************** + +#define DENALI_CTL_00_DATA 0x00000600 // VERSION:RD:16:16:=0x0000 DRAM_CLASS:RW:8:4:=0x06 START:RW:0:1:=0x00 +#define DENALI_CTL_01_DATA 0x00000000 // READ_DATA_FIFO_DEPTH:RD:24:8:=0x00 MAX_CS_REG:RD:16:2:=0x00 MAX_COL_REG:RD:8:4:=0x00 MAX_ROW_REG:RD:0:5:=0x00 +#define DENALI_CTL_02_DATA 0x00000000 // ASYNC_CDC_STAGES:RD:24:8:=0x00 WRITE_DATA_FIFO_PTR_WIDTH:RD:16:8:=0x00 WRITE_DATA_FIFO_DEPTH:RD:8:8:=0x00 READ_DATA_FIFO_PTR_WIDTH:RD:0:8:=0x00 +#define DENALI_CTL_03_DATA 0x00000000 // AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI0_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI0_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI0_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_04_DATA 0x00000000 // AXI1_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI1_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI1_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI1_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_05_DATA 0x00000000 // AXI2_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI2_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI2_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI2_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_06_DATA 0x00000000 // AXI3_WRCMD_PROC_FIFO_LOG2_DEPTH:RD:24:8:=0x00 AXI3_WRFIFO_LOG2_DEPTH:RD:16:8:=0x00 AXI3_RDFIFO_LOG2_DEPTH:RD:8:8:=0x00 AXI3_CMDFIFO_LOG2_DEPTH:RD:0:8:=0x00 +#define DENALI_CTL_07_DATA 0x00000005 // TINIT:RW:0:24:=0x000005 +#define DENALI_CTL_08_DATA 0x000186a0 // TRST_PWRON:RW:0:32:=0x000186a0 +#define DENALI_CTL_09_DATA 0x0003d090 // CKE_INACTIVE:RW:0:32:=0x0003d090 +#define DENALI_CTL_10_DATA 0x00000000 // TCPD:RW:8:16:=0x0000 INITAREF:RW:0:4:=0x00 +#define DENALI_CTL_11_DATA 0x10000200 // CASLAT_LIN:RW:24:6:=0x10 NO_CMD_INIT:RW:16:1:=0x00 TDLL:RW:0:16:=0x0200 +#define DENALI_CTL_12_DATA 0x04040006 // TCCD:RW:24:5:=0x04 TBST_INT_INTERVAL:RW:16:3:=0x04 ADDITIVE_LAT:RW:8:5:=0x00 WRLAT:RW:0:5:=0x06 +#define DENALI_CTL_13_DATA 0x04121904 // TWTR:RW:24:6:=0x04 TRAS_MIN:RW:16:8:=0x12 TRC:RW:8:8:=0x19 TRRD:RW:0:8:=0x04 +#define DENALI_CTL_14_DATA 0x04041407 // TMRD:RW:24:5:=0x04 TRTP:RW:16:4:=0x04 TFAW:RW:8:6:=0x14 TRP:RW:0:5:=0x07 +#define DENALI_CTL_15_DATA 0x00891c0c // TRAS_MAX:RW:8:17:=0x00891c TMOD:RW:0:8:=0x0c +#define DENALI_CTL_16_DATA 0x07000503 // TRCD:RW:24:8:=0x07 WRITEINTERP:RW:16:1:=0x00 TCKESR:RW:8:8:=0x05 TCKE:RW:0:3:=0x03 +#define DENALI_CTL_17_DATA 0x01010008 // TRAS_LOCKOUT:RW:24:1:=0x01 CONCURRENTAP:RW:16:1:=0x01 AP:RW:8:1:=0x00 TWR:RW:0:6:=0x08 +#define DENALI_CTL_18_DATA 0x0007030f // REG_DIMM_ENABLE:RW:24:1:=0x00 TRP_AB:RW:16:5:=0x07 BSTLEN:RW_D:8:3:=0x03 TDAL:RW:0:6:=0x0f +#define DENALI_CTL_19_DATA 0x01000000 // TREF_ENABLE:RW:24:1:=0x01 RESERVED:RW:16:1:=0x00 AREFRESH:WR:8:1:=0x00 ADDRESS_MIRRORING:RW:0:2:=0x00 +#define DENALI_CTL_20_DATA 0x0f340082 // TREF:RW:16:14:=0x0f34 TRFC:RW:0:10:=0x0082 +#define DENALI_CTL_21_DATA 0x00000005 // TREF_INTERVAL:RW:0:14:=0x0005 +#define DENALI_CTL_22_DATA 0x000c0003 // TXPDLL:RW:16:16:=0x000c TPDEX:RW:0:16:=0x0003 +#define DENALI_CTL_23_DATA 0x00000000 // TXARDS:RW:16:16:=0x0000 TXARD:RW:0:16:=0x0000 +#define DENALI_CTL_24_DATA 0x00870200 // TXSNR:RW:16:16:=0x0087 TXSR:RW:0:16:=0x0200 +#define DENALI_CTL_25_DATA 0x00010000 // CKE_DELAY:RW:24:3:=0x00 ENABLE_QUICK_SREFRESH:RW:16:1:=0x01 SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PWRUP_SREFRESH_EXIT:RW:0:1:=0x00 +#define DENALI_CTL_26_DATA 0x00050500 // LP_CMD:WR:24:8:=0x00 CKSRX:RW:16:8:=0x05 CKSRE:RW:8:8:=0x05 LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00 +#define DENALI_CTL_27_DATA 0x00000000 // LP_AUTO_EXIT_EN:RW:24:3:=0x00 LP_AUTO_ENTRY_EN:RW:16:3:=0x00 LP_ARB_STATE:RD:8:4:=0x00 LP_STATE:RD:0:6:=0x00 +#define DENALI_CTL_28_DATA 0x00000000 // LP_AUTO_SR_IDLE:RW:24:8:=0x00 LP_AUTO_PD_IDLE:RW:8:12:=0x0000 LP_AUTO_MEM_GATE_EN:RW:0:2:=0x00 +#define DENALI_CTL_29_DATA 0x00000000 // RESERVED:RW:8:7:=0x00 LP_AUTO_SR_MC_GATE_IDLE:RW:0:8:=0x00 +#define DENALI_CTL_30_DATA 0x00000000 // WRITE_MODEREG:RW+:0:26:=0x00000000 +#define DENALI_CTL_31_DATA 0x00084000 // MR0_DATA_0:RW:8:16:=0x0840 MRW_STATUS:RD:0:8:=0x00 +#define DENALI_CTL_32_DATA 0x00080046 // MR2_DATA_0:RW:16:16:=0x0008 MR1_DATA_0:RW:0:16:=0x0046 +#define DENALI_CTL_33_DATA 0x00000000 // MR3_DATA_0:RW:16:16:=0x0000 MRSINGLE_DATA_0:RW:0:16:=0x0000 +#define DENALI_CTL_34_DATA 0x00460840 // MR1_DATA_1:RW:16:16:=0x0046 MR0_DATA_1:RW:0:16:=0x0840 +#define DENALI_CTL_35_DATA 0x00000008 // MRSINGLE_DATA_1:RW:16:16:=0x0000 MR2_DATA_1:RW:0:16:=0x0008 +#define DENALI_CTL_36_DATA 0x00010000 // FWC:WR:24:1:=0x00 ECC_EN:RW:16:1:=0x01 MR3_DATA_1:RW:0:16:=0x0000 +#define DENALI_CTL_37_DATA 0x00000000 // ECC_DISABLE_W_UC_ERR:RW:16:1:=0x00 XOR_CHECK_BITS:RW:0:14:=0x0000 +#define DENALI_CTL_38_DATA 0x00000000 // ECC_U_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 // ECC_U_SYND:RD:0:7:=0x00 +#define DENALI_CTL_40_DATA 0x00000000 // ECC_U_DATA:RD:0:32:=0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 // ECC_C_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 // ECC_C_SYND:RD:0:7:=0x00 +#define DENALI_CTL_43_DATA 0x00000000 // ECC_C_DATA:RD:0:32:=0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 // LONG_COUNT_MASK:RW:16:5:=0x00 ECC_C_ID:RD:8:6:=0x00 ECC_U_ID:RD:0:6:=0x00 +#define DENALI_CTL_45_DATA 0x01000200 // ZQCL:RW:16:12:=0x0100 ZQINIT:RW_D:0:12:=0x0200 +#define DENALI_CTL_46_DATA 0x02000040 // ZQ_ON_SREF_EXIT:RW:24:2:=0x02 ZQ_REQ:WR:16:2:=0x00 ZQCS:RW:0:12:=0x0040 +#define DENALI_CTL_47_DATA 0x00000040 // ZQ_INTERVAL:RW:0:32:=0x00000040 +#define DENALI_CTL_48_DATA 0x01000100 // ROW_DIFF:RW:24:3:=0x01 BANK_DIFF:RW:16:2:=0x00 ZQCS_ROTATE:RW:8:1:=0x01 ZQ_IN_PROGRESS:RD:0:1:=0x00 +#define DENALI_CTL_49_DATA 0xffff0a01 // COMMAND_AGE_COUNT:RW:24:8:=0xff AGE_COUNT:RW:16:8:=0xff APREBIT:RW_D:8:4:=0x0a COL_DIFF:RW:0:4:=0x01 +#define DENALI_CTL_50_DATA 0x01010101 // PLACEMENT_EN:RW:24:1:=0x01 BANK_SPLIT_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x01 ADDR_CMP_EN:RW:0:1:=0x01 +#define DENALI_CTL_51_DATA 0x01010101 // CS_SAME_EN:RW:24:1:=0x01 RW_SAME_PAGE_EN:RW:16:1:=0x01 RW_SAME_EN:RW:8:1:=0x01 PRIORITY_EN:RW:0:1:=0x01 +#define DENALI_CTL_52_DATA 0x01030101 // SWAP_EN:RW:24:1:=0x01 NUM_Q_ENTRIES_ACT_DISABLE:RW:16:3:=0x03 DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01 W2R_SPLIT_EN:RW:0:1:=0x01 +#define DENALI_CTL_53_DATA 0x0c030000 // BURST_ON_FLY_BIT:RW:24:4:=0x0c CS_MAP:RW:16:2:=0x03 INHIBIT_DRAM_CMD:RW:8:1:=0x00 DISABLE_RD_INTERLEAVE:RW:0:1:=0x00 +#define DENALI_CTL_54_DATA 0x00000000 // CONTROLLER_BUSY:RD:24:1:=0x00 IN_ORDER_ACCEPT:RW:16:1:=0x00 Q_FULLNESS:RW:8:3:=0x00 REDUC:RW:0:1:=0x00 +#define DENALI_CTL_55_DATA 0x00000100 // CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 CTRLUPD_REQ:WR:0:1:=0x00 +#define DENALI_CTL_56_DATA 0x00000000 // INT_STATUS:RD:0:23:=0x000000 +#define DENALI_CTL_57_DATA 0x00000000 // INT_ACK:WR:0:22:=0x000000 +#define DENALI_CTL_58_DATA 0x00000000 // INT_MASK:RW:0:23:=0x000000 +#define DENALI_CTL_59_DATA 0x00000000 // OUT_OF_RANGE_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_60_DATA 0x00000000 // OUT_OF_RANGE_SOURCE_ID:RD:16:6:=0x00 OUT_OF_RANGE_TYPE:RD:8:6:=0x00 OUT_OF_RANGE_LENGTH:RD:0:7:=0x00 +#define DENALI_CTL_61_DATA 0x00000000 // PORT_CMD_ERROR_ADDR:RD:0:32:=0x00000000 +#define DENALI_CTL_62_DATA 0x01020000 // ODT_WR_MAP_CS0:RW:24:2:=0x01 ODT_RD_MAP_CS0:RW:16:2:=0x02 PORT_CMD_ERROR_TYPE:RD:8:3:=0x00 PORT_CMD_ERROR_ID:RD:0:6:=0x00 +#define DENALI_CTL_63_DATA 0x06050201 // TODTH_WR:RW:24:4:=0x06 TODTL_2CMD:RW:16:8:=0x05 ODT_WR_MAP_CS1:RW:8:2:=0x02 ODT_RD_MAP_CS1:RW:0:2:=0x01 +#define DENALI_CTL_64_DATA 0x02000106 // RD_TO_ODTH:RW:24:7:=0x02 WR_TO_ODTH:RW:16:7:=0x00 ODT_EN:RW:8:1:=0x01 TODTH_RD:RW:0:4:=0x06 +#define DENALI_CTL_65_DATA 0x00000000 // +#define DENALI_CTL_66_DATA 0x02020202 // W2W_DIFFCS_DLY:RW_D:24:4:=0x02 W2R_DIFFCS_DLY:RW_D:16:3:=0x02 R2W_DIFFCS_DLY:RW_D:8:3:=0x02 R2R_DIFFCS_DLY:RW_D:0:3:=0x02 +#define DENALI_CTL_67_DATA 0x00000200 // W2W_SAMECS_DLY:RW:24:3:=0x00 W2R_SAMECS_DLY:RW:16:3:=0x00 R2W_SAMECS_DLY:RW_D:8:3:=0x02 R2R_SAMECS_DLY:RW:0:3:=0x00 +#define DENALI_CTL_68_DATA 0x00000000 // SWLVL_LOAD:WR:24:1:=0x00 SW_LEVELING_MODE:RW:16:2:=0x00 OCD_ADJUST_PUP_CS_0:RW:8:5:=0x00 OCD_ADJUST_PDN_CS_0:RW:0:5:=0x00 +#define DENALI_CTL_69_DATA 0x00000000 // LVL_STATUS:RD:24:4:=0x00 SWLVL_OP_DONE:RD:16:1:=0x00 SWLVL_EXIT:WR:8:1:=0x00 SWLVL_START:WR:0:1:=0x00 +#define DENALI_CTL_70_DATA 0x00000000 // WRLVL_REQ:WR:24:1:=0x00 SWLVL_RESP_2:RD:16:8:=0x00 SWLVL_RESP_1:RD:8:8:=0x00 SWLVL_RESP_0:RD:0:8:=0x00 +#define DENALI_CTL_71_DATA 0x00280d00 // WRLVL_EN:RW:24:1:=0x00 WLMRD:RW:16:6:=0x28 WLDQSEN:RW:8:6:=0x0d WRLVL_CS:RW:0:1:=0x00 +#define DENALI_CTL_72_DATA 0x00000000 // WRLVL_ERROR_STATUS:RD:24:8:=0x00 RESERVED:RW:16:3:=0x00 WRLVL_INTERVAL:RW:0:16:=0x0000 +#define DENALI_CTL_73_DATA 0x00000100 // WRLVL_DELAY_0:RW+:8:16:=0x0001 WRLVL_REG_EN:RW:0:1:=0x00 +#define DENALI_CTL_74_DATA 0x00010001 // WRLVL_DELAY_2:RW+:16:16:=0x0001 WRLVL_DELAY_1:RW+:0:16:=0x0001 +#define DENALI_CTL_75_DATA 0x00000000 // RDLVL_EDGE:RW:24:1:=0x00 RDLVL_CS:RW:16:1:=0x00 RDLVL_GATE_REQ:WR:8:1:=0x00 RDLVL_REQ:WR:0:1:=0x00 +#define DENALI_CTL_76_DATA 0x00000000 // RDLVL_GATE_REG_EN:RW:16:1:=0x00 RDLVL_REG_EN:RW:8:1:=0x00 RDLVL_BEGIN_DELAY_EN:RW:0:1:=0x00 +#define DENALI_CTL_77_DATA 0x00000000 // RDLVL_END_DELAY_0:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_0:RD:0:16:=0x0000 +#define DENALI_CTL_78_DATA 0x00000000 // RDLVL_OFFSET_DELAY_0:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_0:RD:0:16:=0x0000 +#define DENALI_CTL_79_DATA 0x00212100 // RDLVL_DELAY_0:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_0:RW:0:1:=0x00 +#define DENALI_CTL_80_DATA 0x00000001 // RDLVL_BEGIN_DELAY_1:RD:16:16:=0x0000 RDLVL_GATE_DELAY_0:RW+:0:16:=0x0001 +#define DENALI_CTL_81_DATA 0x00000000 // RDLVL_MIDPOINT_DELAY_1:RD:16:16:=0x0000 RDLVL_END_DELAY_1:RD:0:16:=0x0000 +#define DENALI_CTL_82_DATA 0x00000000 // RDLVL_OFFSET_DIR_1:RW:16:1:=0x00 RDLVL_OFFSET_DELAY_1:RW:0:16:=0x0000 +#define DENALI_CTL_83_DATA 0x00012121 // RDLVL_GATE_DELAY_1:RW+:16:16:=0x0001 RDLVL_DELAY_1:RW:0:16:=0x2121 +#define DENALI_CTL_84_DATA 0x00000000 // RDLVL_END_DELAY_2:RD:16:16:=0x0000 RDLVL_BEGIN_DELAY_2:RD:0:16:=0x0000 +#define DENALI_CTL_85_DATA 0x00000000 // RDLVL_OFFSET_DELAY_2:RW:16:16:=0x0000 RDLVL_MIDPOINT_DELAY_2:RD:0:16:=0x0000 +#define DENALI_CTL_86_DATA 0x00212100 // RDLVL_DELAY_2:RW:8:16:=0x2121 RDLVL_OFFSET_DIR_2:RW:0:1:=0x00 +#define DENALI_CTL_87_DATA 0x02020001 // AXI0_W_PRIORITY:RW:24:2:=0x02 AXI0_R_PRIORITY:RW:16:2:=0x02 RDLVL_GATE_DELAY_2:RW+:0:16:=0x0001 +#define DENALI_CTL_88_DATA 0x00020200 // AXI1_FIFO_TYPE_REG:RW:24:2:=0x00 AXI1_W_PRIORITY:RW:16:2:=0x02 AXI1_R_PRIORITY:RW:8:2:=0x02 AXI0_FIFO_TYPE_REG:RW:0:2:=0x00 +#define DENALI_CTL_89_DATA 0x02000202 // AXI3_R_PRIORITY:RW:24:2:=0x02 AXI2_FIFO_TYPE_REG:RW:16:2:=0x00 AXI2_W_PRIORITY:RW:8:2:=0x02 AXI2_R_PRIORITY:RW:0:2:=0x02 +#define DENALI_CTL_90_DATA 0x01000002 // PORT_ADDR_PROTECTION_EN:RW:24:1:=0x01 AXI3_FIFO_TYPE_REG:RW:8:2:=0x00 AXI3_W_PRIORITY:RW:0:2:=0x02 +#define DENALI_CTL_91_DATA 0x00000000 // AXI0_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_92_DATA 0x0003ffff // AXI0_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_93_DATA 0x00000000 // AXI0_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_94_DATA 0x0003ffff // AXI0_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_95_DATA 0x00000000 // AXI0_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_96_DATA 0x0003ffff // AXI0_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_97_DATA 0x00000000 // AXI0_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_98_DATA 0x0003ffff // AXI0_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_99_DATA 0x00000000 // AXI0_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_100_DATA 0x0003ffff // AXI0_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_101_DATA 0x00000000 // AXI0_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_102_DATA 0x0003ffff // AXI0_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_103_DATA 0x00000000 // AXI0_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_104_DATA 0x0003ffff // AXI0_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_105_DATA 0x00000000 // AXI0_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_106_DATA 0x0003ffff // AXI0_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_107_DATA 0x00000000 // AXI0_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_108_DATA 0x0003ffff // AXI0_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_109_DATA 0x00000000 // AXI0_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_110_DATA 0x0003ffff // AXI0_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_111_DATA 0x00000000 // AXI0_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_112_DATA 0x0003ffff // AXI0_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_113_DATA 0x00000000 // AXI0_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_114_DATA 0x0003ffff // AXI0_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_115_DATA 0x00000000 // AXI0_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_116_DATA 0x0003ffff // AXI0_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_117_DATA 0x00000000 // AXI0_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_118_DATA 0x0003ffff // AXI0_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_119_DATA 0x00000000 // AXI0_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_120_DATA 0x0003ffff // AXI0_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_121_DATA 0x00000000 // AXI0_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_122_DATA 0x0003ffff // AXI0_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_123_DATA 0x00000000 // AXI1_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_124_DATA 0x0003ffff // AXI1_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_125_DATA 0x00000000 // AXI1_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_126_DATA 0x0003ffff // AXI1_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_127_DATA 0x00000000 // AXI1_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_128_DATA 0x0003ffff // AXI1_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_129_DATA 0x00000000 // AXI1_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_130_DATA 0x0003ffff // AXI1_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_131_DATA 0x00000000 // AXI1_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_132_DATA 0x0003ffff // AXI1_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_133_DATA 0x00000000 // AXI1_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_134_DATA 0x0003ffff // AXI1_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_135_DATA 0x00000000 // AXI1_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_136_DATA 0x0003ffff // AXI1_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_137_DATA 0x00000000 // AXI1_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_138_DATA 0x0003ffff // AXI1_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_139_DATA 0x00000000 // AXI1_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_140_DATA 0x0003ffff // AXI1_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_141_DATA 0x00000000 // AXI1_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_142_DATA 0x0003ffff // AXI1_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_143_DATA 0x00000000 // AXI1_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_144_DATA 0x0003ffff // AXI1_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_145_DATA 0x00000000 // AXI1_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_146_DATA 0x0003ffff // AXI1_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_147_DATA 0x00000000 // AXI1_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_148_DATA 0x0003ffff // AXI1_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_149_DATA 0x00000000 // AXI1_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_150_DATA 0x0003ffff // AXI1_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_151_DATA 0x00000000 // AXI1_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_152_DATA 0x0003ffff // AXI1_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_153_DATA 0x00000000 // AXI1_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_154_DATA 0x0003ffff // AXI1_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_155_DATA 0x00000000 // AXI2_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_156_DATA 0x0003ffff // AXI2_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_157_DATA 0x00000000 // AXI2_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_158_DATA 0x0003ffff // AXI2_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_159_DATA 0x00000000 // AXI2_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_160_DATA 0x0003ffff // AXI2_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_161_DATA 0x00000000 // AXI2_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_162_DATA 0x0003ffff // AXI2_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_163_DATA 0x00000000 // AXI2_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_164_DATA 0x0003ffff // AXI2_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_165_DATA 0x00000000 // AXI2_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_166_DATA 0x0003ffff // AXI2_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_167_DATA 0x00000000 // AXI2_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_168_DATA 0x0003ffff // AXI2_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_169_DATA 0x00000000 // AXI2_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_170_DATA 0x0003ffff // AXI2_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_171_DATA 0x00000000 // AXI2_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_172_DATA 0x0003ffff // AXI2_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_173_DATA 0x00000000 // AXI2_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_174_DATA 0x0003ffff // AXI2_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_175_DATA 0x00000000 // AXI2_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_176_DATA 0x0003ffff // AXI2_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_177_DATA 0x00000000 // AXI2_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_178_DATA 0x0003ffff // AXI2_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_179_DATA 0x00000000 // AXI2_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_180_DATA 0x0003ffff // AXI2_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_181_DATA 0x00000000 // AXI2_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_182_DATA 0x0003ffff // AXI2_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_183_DATA 0x00000000 // AXI2_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_184_DATA 0x0003ffff // AXI2_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_185_DATA 0x00000000 // AXI2_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_186_DATA 0x0003ffff // AXI2_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_187_DATA 0x00000000 // AXI3_START_ADDR_0:RW:0:18:=0x000000 +#define DENALI_CTL_188_DATA 0x0003ffff // AXI3_END_ADDR_0:RW:0:18:=0x03ffff +#define DENALI_CTL_189_DATA 0x00000000 // AXI3_START_ADDR_1:RW:0:18:=0x000000 +#define DENALI_CTL_190_DATA 0x0003ffff // AXI3_END_ADDR_1:RW:0:18:=0x03ffff +#define DENALI_CTL_191_DATA 0x00000000 // AXI3_START_ADDR_2:RW:0:18:=0x000000 +#define DENALI_CTL_192_DATA 0x0003ffff // AXI3_END_ADDR_2:RW:0:18:=0x03ffff +#define DENALI_CTL_193_DATA 0x00000000 // AXI3_START_ADDR_3:RW:0:18:=0x000000 +#define DENALI_CTL_194_DATA 0x0003ffff // AXI3_END_ADDR_3:RW:0:18:=0x03ffff +#define DENALI_CTL_195_DATA 0x00000000 // AXI3_START_ADDR_4:RW:0:18:=0x000000 +#define DENALI_CTL_196_DATA 0x0003ffff // AXI3_END_ADDR_4:RW:0:18:=0x03ffff +#define DENALI_CTL_197_DATA 0x00000000 // AXI3_START_ADDR_5:RW:0:18:=0x000000 +#define DENALI_CTL_198_DATA 0x0003ffff // AXI3_END_ADDR_5:RW:0:18:=0x03ffff +#define DENALI_CTL_199_DATA 0x00000000 // AXI3_START_ADDR_6:RW:0:18:=0x000000 +#define DENALI_CTL_200_DATA 0x0003ffff // AXI3_END_ADDR_6:RW:0:18:=0x03ffff +#define DENALI_CTL_201_DATA 0x00000000 // AXI3_START_ADDR_7:RW:0:18:=0x000000 +#define DENALI_CTL_202_DATA 0x0003ffff // AXI3_END_ADDR_7:RW:0:18:=0x03ffff +#define DENALI_CTL_203_DATA 0x00000000 // AXI3_START_ADDR_8:RW:0:18:=0x000000 +#define DENALI_CTL_204_DATA 0x0003ffff // AXI3_END_ADDR_8:RW:0:18:=0x03ffff +#define DENALI_CTL_205_DATA 0x00000000 // AXI3_START_ADDR_9:RW:0:18:=0x000000 +#define DENALI_CTL_206_DATA 0x0003ffff // AXI3_END_ADDR_9:RW:0:18:=0x03ffff +#define DENALI_CTL_207_DATA 0x00000000 // AXI3_START_ADDR_10:RW:0:18:=0x000000 +#define DENALI_CTL_208_DATA 0x0003ffff // AXI3_END_ADDR_10:RW:0:18:=0x03ffff +#define DENALI_CTL_209_DATA 0x00000000 // AXI3_START_ADDR_11:RW:0:18:=0x000000 +#define DENALI_CTL_210_DATA 0x0003ffff // AXI3_END_ADDR_11:RW:0:18:=0x03ffff +#define DENALI_CTL_211_DATA 0x00000000 // AXI3_START_ADDR_12:RW:0:18:=0x000000 +#define DENALI_CTL_212_DATA 0x0003ffff // AXI3_END_ADDR_12:RW:0:18:=0x03ffff +#define DENALI_CTL_213_DATA 0x00000000 // AXI3_START_ADDR_13:RW:0:18:=0x000000 +#define DENALI_CTL_214_DATA 0x0003ffff // AXI3_END_ADDR_13:RW:0:18:=0x03ffff +#define DENALI_CTL_215_DATA 0x00000000 // AXI3_START_ADDR_14:RW:0:18:=0x000000 +#define DENALI_CTL_216_DATA 0x0003ffff // AXI3_END_ADDR_14:RW:0:18:=0x03ffff +#define DENALI_CTL_217_DATA 0x00000000 // AXI3_START_ADDR_15:RW:0:18:=0x000000 +#define DENALI_CTL_218_DATA 0x0303ffff // AXI0_RANGE_PROT_BITS_0:RW:24:2:=0x03 AXI3_END_ADDR_15:RW:0:18:=0x03ffff +#define DENALI_CTL_219_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_220_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_221_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_222_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_223_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_224_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_225_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_226_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_227_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_228_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_229_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_230_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_231_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_232_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_233_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_234_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_235_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_236_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_237_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_238_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_239_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_240_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_241_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_242_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_243_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_244_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_245_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_246_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_247_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_248_DATA 0x00030f0f // AXI0_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_249_DATA 0xffffffff // AXI0_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI0_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_250_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_251_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_252_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_253_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_254_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_255_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_256_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_257_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_258_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_259_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_260_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_261_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_262_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_263_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_264_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_265_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_266_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_267_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_268_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_269_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_270_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_271_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_272_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_273_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_274_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_275_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_276_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_277_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_278_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_279_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_280_DATA 0x00030f0f // AXI1_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_281_DATA 0xffffffff // AXI1_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI1_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_282_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI1_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI1_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_283_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_284_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_285_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_286_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_287_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_288_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_289_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_290_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_291_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_292_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_293_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_294_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_295_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_296_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_297_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_298_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_299_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_300_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_301_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_302_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_303_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_304_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_305_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_306_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_307_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_308_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_309_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_310_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_311_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_312_DATA 0x00030f0f // AXI2_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_313_DATA 0xffffffff // AXI2_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI2_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_314_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_0:RW:16:2:=0x03 AXI2_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI2_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_315_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff +#define DENALI_CTL_316_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_1:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:4:=0x0f +#define DENALI_CTL_317_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff +#define DENALI_CTL_318_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_2:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:4:=0x0f +#define DENALI_CTL_319_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff +#define DENALI_CTL_320_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_3:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:4:=0x0f +#define DENALI_CTL_321_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff +#define DENALI_CTL_322_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_4:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:4:=0x0f +#define DENALI_CTL_323_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff +#define DENALI_CTL_324_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_5:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:4:=0x0f +#define DENALI_CTL_325_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff +#define DENALI_CTL_326_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_6:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:4:=0x0f +#define DENALI_CTL_327_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff +#define DENALI_CTL_328_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_7:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:4:=0x0f +#define DENALI_CTL_329_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff +#define DENALI_CTL_330_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_8:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:4:=0x0f +#define DENALI_CTL_331_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff +#define DENALI_CTL_332_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_9:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:4:=0x0f +#define DENALI_CTL_333_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff +#define DENALI_CTL_334_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_10:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:4:=0x0f +#define DENALI_CTL_335_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff +#define DENALI_CTL_336_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_11:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:4:=0x0f +#define DENALI_CTL_337_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff +#define DENALI_CTL_338_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_12:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:4:=0x0f +#define DENALI_CTL_339_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff +#define DENALI_CTL_340_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_13:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:4:=0x0f +#define DENALI_CTL_341_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff +#define DENALI_CTL_342_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_14:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:4:=0x0f +#define DENALI_CTL_343_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff +#define DENALI_CTL_344_DATA 0x00030f0f // AXI3_RANGE_PROT_BITS_15:RW:16:2:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:4:=0x0f +#define DENALI_CTL_345_DATA 0xffffffff // AXI3_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff AXI3_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff +#define DENALI_CTL_346_DATA 0x32030f0f // AXI0_BDW:RW:24:7:=0x32 ARB_CMD_Q_THRESHOLD:RW:16:3:=0x03 AXI3_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:4:=0x0f AXI3_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:4:=0x0f +#define DENALI_CTL_347_DATA 0x01320001 // AXI1_BDW_OVFLOW:RW:24:1:=0x01 AXI1_BDW:RW:16:7:=0x32 AXI0_CURRENT_BDW:RD:8:7:=0x00 AXI0_BDW_OVFLOW:RW:0:1:=0x01 +#define DENALI_CTL_348_DATA 0x00013200 // AXI2_CURRENT_BDW:RD:24:7:=0x00 AXI2_BDW_OVFLOW:RW:16:1:=0x01 AXI2_BDW:RW:8:7:=0x32 AXI1_CURRENT_BDW:RD:0:7:=0x00 +#define DENALI_CTL_349_DATA 0x00000132 // CKE_STATUS:RD:24:2:=0x00 AXI3_CURRENT_BDW:RD:16:7:=0x00 AXI3_BDW_OVFLOW:RW:8:1:=0x01 AXI3_BDW:RW:0:7:=0x32 +#define DENALI_CTL_350_DATA 0x00000000 // DLL_RST_ADJ_DLY:RW:24:8:=0x00 DLL_RST_DELAY:RW:8:16:=0x0000 MEM_RST_VALID:RD:0:1:=0x00 +#define DENALI_CTL_351_DATA 0x000d0000 // TDFI_RDDATA_EN:RD:24:6:=0x00 TDFI_PHY_RDLAT:RW_D:16:6:=0x0d UPDATE_ERROR_STATUS:RD:8:7:=0x00 TDFI_PHY_WRLAT:RD:0:6:=0x00 +#define DENALI_CTL_352_DATA 0x1e680000 // TDFI_CTRLUPD_MAX:RW:16:14:=0x1e68 TDFI_CTRLUPD_MIN:RD:8:4:=0x00 DRAM_CLK_DISABLE:RW:0:2:=0x00 +#define DENALI_CTL_353_DATA 0x02000200 // TDFI_PHYUPD_TYPE1:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE0:RW:0:16:=0x0200 +#define DENALI_CTL_354_DATA 0x02000200 // TDFI_PHYUPD_TYPE3:RW:16:16:=0x0200 TDFI_PHYUPD_TYPE2:RW:0:16:=0x0200 +#define DENALI_CTL_355_DATA 0x00001e68 // TDFI_PHYUPD_RESP:RW:0:14:=0x1e68 +#define DENALI_CTL_356_DATA 0x00009808 // TDFI_CTRLUPD_INTERVAL:RW:0:32:=0x00009808 +#define DENALI_CTL_357_DATA 0x00020608 // TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x00 TDFI_CTRL_DELAY:RW_D:16:4:=0x02 WRLAT_ADJ:RW:8:6:=0x06 RDLAT_ADJ:RW:0:6:=0x08 +#define DENALI_CTL_358_DATA 0x000a0a01 // TDFI_WRLVL_WW:RW:16:10:=0x000a TDFI_WRLVL_EN:RW:8:8:=0x0a TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x01 +#define DENALI_CTL_359_DATA 0x00000000 // TDFI_WRLVL_RESP:RW:0:32:=0x00000000 +#define DENALI_CTL_360_DATA 0x00000000 // TDFI_WRLVL_MAX:RW:0:32:=0x00000000 +#define DENALI_CTL_361_DATA 0x04038000 // TDFI_WRLVL_RESPLAT:RW:24:8:=0x04 TDFI_WRLVL_DLL:RW:16:8:=0x03 DFI_WRLVL_MAX_DELAY:RW:0:16:=0x8000 +#define DENALI_CTL_362_DATA 0x07030a07 // TDFI_RDLVL_LOAD:RW:24:8:=0x07 TDFI_RDLVL_DLL:RW:16:8:=0x03 TDFI_RDLVL_EN:RW:8:8:=0x0a TDFI_WRLVL_LOAD:RW:0:8:=0x07 +#define DENALI_CTL_363_DATA 0x00ffff22 // RDLVL_MAX_DELAY:RW:8:16:=0xffff TDFI_RDLVL_RESPLAT:RW:0:8:=0x22 +#define DENALI_CTL_364_DATA 0x000f0010 // TDFI_RDLVL_RR:RW:16:10:=0x000f RDLVL_GATE_MAX_DELAY:RW:0:16:=0x0010 +#define DENALI_CTL_365_DATA 0x00000000 // TDFI_RDLVL_RESP:RW:0:32:=0x00000000 +#define DENALI_CTL_366_DATA 0x00000000 // RDLVL_RESP_MASK:RW:0:20:=0x000000 +#define DENALI_CTL_367_DATA 0x00000000 // RDLVL_EN:RW:24:1:=0x00 RDLVL_GATE_RESP_MASK:RW:0:20:=0x000000 +#define DENALI_CTL_368_DATA 0x00000000 // RDLVL_GATE_PREAMBLE_CHECK_EN:RW:8:1:=0x00 RDLVL_GATE_EN:RW:0:1:=0x00 +#define DENALI_CTL_369_DATA 0x00000000 // TDFI_RDLVL_MAX:RW:0:32:=0x00000000 +#define DENALI_CTL_370_DATA 0x00000204 // RDLVL_ERROR_STATUS:RD:16:14:=0x0000 RDLVL_GATE_DQ_ZERO_COUNT:RW:8:4:=0x02 RDLVL_DQ_ZERO_COUNT:RW:0:4:=0x04 +#define DENALI_CTL_371_DATA 0x00000000 // RDLVL_GATE_INTERVAL:RW:16:16:=0x0000 RDLVL_INTERVAL:RW:0:16:=0x0000 +#define DENALI_CTL_372_DATA 0x01000001 // OPTIMAL_RMODW_EN:RW:24:1:=0x01 MEMCD_RMODW_FIFO_PTR_WIDTH:RD:16:8:=0x00 MEMCD_RMODW_FIFO_DEPTH:RD:8:8:=0x00 TDFI_PHY_WRDATA:RW:0:3:=0x01 +#define DENALI_CTL_373_DATA 0x00000001 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:5:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x01 +#define DENALI_CTL_374_DATA 0x00000000 // AXI3_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00 AXI2_ALL_STROBES_USED_ENABLE:RW:16:1:=0x00 AXI1_ALL_STROBES_USED_ENABLE:RW:8:1:=0x00 AXI0_ALL_STROBES_USED_ENABLE:RW:0:1:=0x00 + diff --git a/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h new file mode 100644 index 00000000000..cfef7fa0bfa --- /dev/null +++ b/include/renesas/jedec_ddr3_2g_x16_1333h_500_cl8.h @@ -0,0 +1,399 @@ + +/* **************************************************************** + * CADENCE Copyright (c) 2001-2011 * + * Cadence Design Systems, Inc. * + * All rights reserved. * + * * + ****************************************************************** + * The values calculated from this script are meant to be * + * representative programmings. The values may not reflect the * + * actual required programming for production use. Please * + * closely review all programmed values for technical accuracy * + * before use in production parts. * + ****************************************************************** + * + * Module: regconfig.h + * Documentation: Register programming header file + * + ****************************************************************** + ****************************************************************** + * WARNING: This file was automatically generated. Manual + * editing may result in undetermined behavior. + ****************************************************************** + ******************************************************************/ + +#define DENALI_CTL_00_DATA 0x00000600 +#define DENALI_CTL_01_DATA 0x00000000 +#define DENALI_CTL_02_DATA 0x00000000 +#define DENALI_CTL_03_DATA 0x00000000 +#define DENALI_CTL_04_DATA 0x00000000 +#define DENALI_CTL_05_DATA 0x00000000 +#define DENALI_CTL_06_DATA 0x00000000 +#define DENALI_CTL_07_DATA 0x00000005 +#define DENALI_CTL_08_DATA 0x000186a0 +#define DENALI_CTL_09_DATA 0x0003d090 +#define DENALI_CTL_10_DATA 0x00000000 +#define DENALI_CTL_11_DATA 0x10000200 +#define DENALI_CTL_12_DATA 0x04040006 +#define DENALI_CTL_13_DATA 0x04121904 +#define DENALI_CTL_14_DATA 0x04041707 +#define DENALI_CTL_15_DATA 0x00891c0c +#define DENALI_CTL_16_DATA 0x07000503 +#define DENALI_CTL_17_DATA 0x01010008 +#define DENALI_CTL_18_DATA 0x0007030f +#define DENALI_CTL_19_DATA 0x01000000 +#define DENALI_CTL_20_DATA 0x0f340050 +#define DENALI_CTL_21_DATA 0x00000005 +#define DENALI_CTL_22_DATA 0x000c0003 +#define DENALI_CTL_23_DATA 0x00000000 +#define DENALI_CTL_24_DATA 0x00550200 +#define DENALI_CTL_25_DATA 0x00010000 +#define DENALI_CTL_26_DATA 0x00050500 +#define DENALI_CTL_27_DATA 0x00000000 +#define DENALI_CTL_28_DATA 0x00000000 +#define DENALI_CTL_29_DATA 0x00000000 +#define DENALI_CTL_30_DATA 0x00000000 +#define DENALI_CTL_31_DATA 0x00084000 +#define DENALI_CTL_32_DATA 0x00080046 +#define DENALI_CTL_33_DATA 0x00000000 +#define DENALI_CTL_34_DATA 0x00460840 +#define DENALI_CTL_35_DATA 0x00000008 +#define DENALI_CTL_36_DATA 0x00010000 +#define DENALI_CTL_37_DATA 0x00000000 +#define DENALI_CTL_38_DATA 0x00000000 +#define DENALI_CTL_39_DATA 0x00000000 +#define DENALI_CTL_40_DATA 0x00000000 +#define DENALI_CTL_41_DATA 0x00000000 +#define DENALI_CTL_42_DATA 0x00000000 +#define DENALI_CTL_43_DATA 0x00000000 +#define DENALI_CTL_44_DATA 0x00000000 +#define DENALI_CTL_45_DATA 0x01000200 +#define DENALI_CTL_46_DATA 0x02000040 +#define DENALI_CTL_47_DATA 0x00000040 +#define DENALI_CTL_48_DATA 0x02000100 +#define DENALI_CTL_49_DATA 0xffff0a01 +#define DENALI_CTL_50_DATA 0x01010101 +#define DENALI_CTL_51_DATA 0x01010101 +#define DENALI_CTL_52_DATA 0x01030101 +#define DENALI_CTL_53_DATA 0x0c030000 +#define DENALI_CTL_54_DATA 0x00000000 +#define DENALI_CTL_55_DATA 0x00000100 +#define DENALI_CTL_56_DATA 0x00000000 +#define DENALI_CTL_57_DATA 0x00000000 +#define DENALI_CTL_58_DATA 0x00000000 +#define DENALI_CTL_59_DATA 0x00000000 +#define DENALI_CTL_60_DATA 0x00000000 +#define DENALI_CTL_61_DATA 0x00000000 +#define DENALI_CTL_62_DATA 0x01020000 +#define DENALI_CTL_63_DATA 0x06050201 +#define DENALI_CTL_64_DATA 0x02000106 +#define DENALI_CTL_65_DATA 0x00000000 +#define DENALI_CTL_66_DATA 0x02020202 +#define DENALI_CTL_67_DATA 0x00000200 +#define DENALI_CTL_68_DATA 0x00000000 +#define DENALI_CTL_69_DATA 0x00000000 +#define DENALI_CTL_70_DATA 0x00000000 +#define DENALI_CTL_71_DATA 0x00280d00 +#define DENALI_CTL_72_DATA 0x00000000 +#define DENALI_CTL_73_DATA 0x00000100 +#define DENALI_CTL_74_DATA 0x00010001 +#define DENALI_CTL_75_DATA 0x00000000 +#define DENALI_CTL_76_DATA 0x00000000 +#define DENALI_CTL_77_DATA 0x00000000 +#define DENALI_CTL_78_DATA 0x00000000 +#define DENALI_CTL_79_DATA 0x00222200 +#define DENALI_CTL_80_DATA 0x00000001 +#define DENALI_CTL_81_DATA 0x00000000 +#define DENALI_CTL_82_DATA 0x00000000 +#define DENALI_CTL_83_DATA 0x00012222 +#define DENALI_CTL_84_DATA 0x00000000 +#define DENALI_CTL_85_DATA 0x00000000 +#define DENALI_CTL_86_DATA 0x00222200 +#define DENALI_CTL_87_DATA 0x02020001 +#define DENALI_CTL_88_DATA 0x00020200 +#define DENALI_CTL_89_DATA 0x02000202 +#define DENALI_CTL_90_DATA 0x01000002 +#define DENALI_CTL_91_DATA 0x00000000 +#define DENALI_CTL_92_DATA 0x0003ffff +#define DENALI_CTL_93_DATA 0x00000000 +#define DENALI_CTL_94_DATA 0x0003ffff +#define DENALI_CTL_95_DATA 0x00000000 +#define DENALI_CTL_96_DATA 0x0003ffff +#define DENALI_CTL_97_DATA 0x00000000 +#define DENALI_CTL_98_DATA 0x0003ffff +#define DENALI_CTL_99_DATA 0x00000000 +#define DENALI_CTL_100_DATA 0x0003ffff +#define DENALI_CTL_101_DATA 0x00000000 +#define DENALI_CTL_102_DATA 0x0003ffff +#define DENALI_CTL_103_DATA 0x00000000 +#define DENALI_CTL_104_DATA 0x0003ffff +#define DENALI_CTL_105_DATA 0x00000000 +#define DENALI_CTL_106_DATA 0x0003ffff +#define DENALI_CTL_107_DATA 0x00000000 +#define DENALI_CTL_108_DATA 0x0003ffff +#define DENALI_CTL_109_DATA 0x00000000 +#define DENALI_CTL_110_DATA 0x0003ffff +#define DENALI_CTL_111_DATA 0x00000000 +#define DENALI_CTL_112_DATA 0x0003ffff +#define DENALI_CTL_113_DATA 0x00000000 +#define DENALI_CTL_114_DATA 0x0003ffff +#define DENALI_CTL_115_DATA 0x00000000 +#define DENALI_CTL_116_DATA 0x0003ffff +#define DENALI_CTL_117_DATA 0x00000000 +#define DENALI_CTL_118_DATA 0x0003ffff +#define DENALI_CTL_119_DATA 0x00000000 +#define DENALI_CTL_120_DATA 0x0003ffff +#define DENALI_CTL_121_DATA 0x00000000 +#define DENALI_CTL_122_DATA 0x0003ffff +#define DENALI_CTL_123_DATA 0x00000000 +#define DENALI_CTL_124_DATA 0x0003ffff +#define DENALI_CTL_125_DATA 0x00000000 +#define DENALI_CTL_126_DATA 0x0003ffff +#define DENALI_CTL_127_DATA 0x00000000 +#define DENALI_CTL_128_DATA 0x0003ffff +#define DENALI_CTL_129_DATA 0x00000000 +#define DENALI_CTL_130_DATA 0x0003ffff +#define DENALI_CTL_131_DATA 0x00000000 +#define DENALI_CTL_132_DATA 0x0003ffff +#define DENALI_CTL_133_DATA 0x00000000 +#define DENALI_CTL_134_DATA 0x0003ffff +#define DENALI_CTL_135_DATA 0x00000000 +#define DENALI_CTL_136_DATA 0x0003ffff +#define DENALI_CTL_137_DATA 0x00000000 +#define DENALI_CTL_138_DATA 0x0003ffff +#define DENALI_CTL_139_DATA 0x00000000 +#define DENALI_CTL_140_DATA 0x0003ffff +#define DENALI_CTL_141_DATA 0x00000000 +#define DENALI_CTL_142_DATA 0x0003ffff +#define DENALI_CTL_143_DATA 0x00000000 +#define DENALI_CTL_144_DATA 0x0003ffff +#define DENALI_CTL_145_DATA 0x00000000 +#define DENALI_CTL_146_DATA 0x0003ffff +#define DENALI_CTL_147_DATA 0x00000000 +#define DENALI_CTL_148_DATA 0x0003ffff +#define DENALI_CTL_149_DATA 0x00000000 +#define DENALI_CTL_150_DATA 0x0003ffff +#define DENALI_CTL_151_DATA 0x00000000 +#define DENALI_CTL_152_DATA 0x0003ffff +#define DENALI_CTL_153_DATA 0x00000000 +#define DENALI_CTL_154_DATA 0x0003ffff +#define DENALI_CTL_155_DATA 0x00000000 +#define DENALI_CTL_156_DATA 0x0003ffff +#define DENALI_CTL_157_DATA 0x00000000 +#define DENALI_CTL_158_DATA 0x0003ffff +#define DENALI_CTL_159_DATA 0x00000000 +#define DENALI_CTL_160_DATA 0x0003ffff +#define DENALI_CTL_161_DATA 0x00000000 +#define DENALI_CTL_162_DATA 0x0003ffff +#define DENALI_CTL_163_DATA 0x00000000 +#define DENALI_CTL_164_DATA 0x0003ffff +#define DENALI_CTL_165_DATA 0x00000000 +#define DENALI_CTL_166_DATA 0x0003ffff +#define DENALI_CTL_167_DATA 0x00000000 +#define DENALI_CTL_168_DATA 0x0003ffff +#define DENALI_CTL_169_DATA 0x00000000 +#define DENALI_CTL_170_DATA 0x0003ffff +#define DENALI_CTL_171_DATA 0x00000000 +#define DENALI_CTL_172_DATA 0x0003ffff +#define DENALI_CTL_173_DATA 0x00000000 +#define DENALI_CTL_174_DATA 0x0003ffff +#define DENALI_CTL_175_DATA 0x00000000 +#define DENALI_CTL_176_DATA 0x0003ffff +#define DENALI_CTL_177_DATA 0x00000000 +#define DENALI_CTL_178_DATA 0x0003ffff +#define DENALI_CTL_179_DATA 0x00000000 +#define DENALI_CTL_180_DATA 0x0003ffff +#define DENALI_CTL_181_DATA 0x00000000 +#define DENALI_CTL_182_DATA 0x0003ffff +#define DENALI_CTL_183_DATA 0x00000000 +#define DENALI_CTL_184_DATA 0x0003ffff +#define DENALI_CTL_185_DATA 0x00000000 +#define DENALI_CTL_186_DATA 0x0003ffff +#define DENALI_CTL_187_DATA 0x00000000 +#define DENALI_CTL_188_DATA 0x0003ffff +#define DENALI_CTL_189_DATA 0x00000000 +#define DENALI_CTL_190_DATA 0x0003ffff +#define DENALI_CTL_191_DATA 0x00000000 +#define DENALI_CTL_192_DATA 0x0003ffff +#define DENALI_CTL_193_DATA 0x00000000 +#define DENALI_CTL_194_DATA 0x0003ffff +#define DENALI_CTL_195_DATA 0x00000000 +#define DENALI_CTL_196_DATA 0x0003ffff +#define DENALI_CTL_197_DATA 0x00000000 +#define DENALI_CTL_198_DATA 0x0003ffff +#define DENALI_CTL_199_DATA 0x00000000 +#define DENALI_CTL_200_DATA 0x0003ffff +#define DENALI_CTL_201_DATA 0x00000000 +#define DENALI_CTL_202_DATA 0x0003ffff +#define DENALI_CTL_203_DATA 0x00000000 +#define DENALI_CTL_204_DATA 0x0003ffff +#define DENALI_CTL_205_DATA 0x00000000 +#define DENALI_CTL_206_DATA 0x0003ffff +#define DENALI_CTL_207_DATA 0x00000000 +#define DENALI_CTL_208_DATA 0x0003ffff +#define DENALI_CTL_209_DATA 0x00000000 +#define DENALI_CTL_210_DATA 0x0003ffff +#define DENALI_CTL_211_DATA 0x00000000 +#define DENALI_CTL_212_DATA 0x0003ffff +#define DENALI_CTL_213_DATA 0x00000000 +#define DENALI_CTL_214_DATA 0x0003ffff +#define DENALI_CTL_215_DATA 0x00000000 +#define DENALI_CTL_216_DATA 0x0003ffff +#define DENALI_CTL_217_DATA 0x00000000 +#define DENALI_CTL_218_DATA 0x0303ffff +#define DENALI_CTL_219_DATA 0xffffffff +#define DENALI_CTL_220_DATA 0x00030f0f +#define DENALI_CTL_221_DATA 0xffffffff +#define DENALI_CTL_222_DATA 0x00030f0f +#define DENALI_CTL_223_DATA 0xffffffff +#define DENALI_CTL_224_DATA 0x00030f0f +#define DENALI_CTL_225_DATA 0xffffffff +#define DENALI_CTL_226_DATA 0x00030f0f +#define DENALI_CTL_227_DATA 0xffffffff +#define DENALI_CTL_228_DATA 0x00030f0f +#define DENALI_CTL_229_DATA 0xffffffff +#define DENALI_CTL_230_DATA 0x00030f0f +#define DENALI_CTL_231_DATA 0xffffffff +#define DENALI_CTL_232_DATA 0x00030f0f +#define DENALI_CTL_233_DATA 0xffffffff +#define DENALI_CTL_234_DATA 0x00030f0f +#define DENALI_CTL_235_DATA 0xffffffff +#define DENALI_CTL_236_DATA 0x00030f0f +#define DENALI_CTL_237_DATA 0xffffffff +#define DENALI_CTL_238_DATA 0x00030f0f +#define DENALI_CTL_239_DATA 0xffffffff +#define DENALI_CTL_240_DATA 0x00030f0f +#define DENALI_CTL_241_DATA 0xffffffff +#define DENALI_CTL_242_DATA 0x00030f0f +#define DENALI_CTL_243_DATA 0xffffffff +#define DENALI_CTL_244_DATA 0x00030f0f +#define DENALI_CTL_245_DATA 0xffffffff +#define DENALI_CTL_246_DATA 0x00030f0f +#define DENALI_CTL_247_DATA 0xffffffff +#define DENALI_CTL_248_DATA 0x00030f0f +#define DENALI_CTL_249_DATA 0xffffffff +#define DENALI_CTL_250_DATA 0x00030f0f +#define DENALI_CTL_251_DATA 0xffffffff +#define DENALI_CTL_252_DATA 0x00030f0f +#define DENALI_CTL_253_DATA 0xffffffff +#define DENALI_CTL_254_DATA 0x00030f0f +#define DENALI_CTL_255_DATA 0xffffffff +#define DENALI_CTL_256_DATA 0x00030f0f +#define DENALI_CTL_257_DATA 0xffffffff +#define DENALI_CTL_258_DATA 0x00030f0f +#define DENALI_CTL_259_DATA 0xffffffff +#define DENALI_CTL_260_DATA 0x00030f0f +#define DENALI_CTL_261_DATA 0xffffffff +#define DENALI_CTL_262_DATA 0x00030f0f +#define DENALI_CTL_263_DATA 0xffffffff +#define DENALI_CTL_264_DATA 0x00030f0f +#define DENALI_CTL_265_DATA 0xffffffff +#define DENALI_CTL_266_DATA 0x00030f0f +#define DENALI_CTL_267_DATA 0xffffffff +#define DENALI_CTL_268_DATA 0x00030f0f +#define DENALI_CTL_269_DATA 0xffffffff +#define DENALI_CTL_270_DATA 0x00030f0f +#define DENALI_CTL_271_DATA 0xffffffff +#define DENALI_CTL_272_DATA 0x00030f0f +#define DENALI_CTL_273_DATA 0xffffffff +#define DENALI_CTL_274_DATA 0x00030f0f +#define DENALI_CTL_275_DATA 0xffffffff +#define DENALI_CTL_276_DATA 0x00030f0f +#define DENALI_CTL_277_DATA 0xffffffff +#define DENALI_CTL_278_DATA 0x00030f0f +#define DENALI_CTL_279_DATA 0xffffffff +#define DENALI_CTL_280_DATA 0x00030f0f +#define DENALI_CTL_281_DATA 0xffffffff +#define DENALI_CTL_282_DATA 0x00030f0f +#define DENALI_CTL_283_DATA 0xffffffff +#define DENALI_CTL_284_DATA 0x00030f0f +#define DENALI_CTL_285_DATA 0xffffffff +#define DENALI_CTL_286_DATA 0x00030f0f +#define DENALI_CTL_287_DATA 0xffffffff +#define DENALI_CTL_288_DATA 0x00030f0f +#define DENALI_CTL_289_DATA 0xffffffff +#define DENALI_CTL_290_DATA 0x00030f0f +#define DENALI_CTL_291_DATA 0xffffffff +#define DENALI_CTL_292_DATA 0x00030f0f +#define DENALI_CTL_293_DATA 0xffffffff +#define DENALI_CTL_294_DATA 0x00030f0f +#define DENALI_CTL_295_DATA 0xffffffff +#define DENALI_CTL_296_DATA 0x00030f0f +#define DENALI_CTL_297_DATA 0xffffffff +#define DENALI_CTL_298_DATA 0x00030f0f +#define DENALI_CTL_299_DATA 0xffffffff +#define DENALI_CTL_300_DATA 0x00030f0f +#define DENALI_CTL_301_DATA 0xffffffff +#define DENALI_CTL_302_DATA 0x00030f0f +#define DENALI_CTL_303_DATA 0xffffffff +#define DENALI_CTL_304_DATA 0x00030f0f +#define DENALI_CTL_305_DATA 0xffffffff +#define DENALI_CTL_306_DATA 0x00030f0f +#define DENALI_CTL_307_DATA 0xffffffff +#define DENALI_CTL_308_DATA 0x00030f0f +#define DENALI_CTL_309_DATA 0xffffffff +#define DENALI_CTL_310_DATA 0x00030f0f +#define DENALI_CTL_311_DATA 0xffffffff +#define DENALI_CTL_312_DATA 0x00030f0f +#define DENALI_CTL_313_DATA 0xffffffff +#define DENALI_CTL_314_DATA 0x00030f0f +#define DENALI_CTL_315_DATA 0xffffffff +#define DENALI_CTL_316_DATA 0x00030f0f +#define DENALI_CTL_317_DATA 0xffffffff +#define DENALI_CTL_318_DATA 0x00030f0f +#define DENALI_CTL_319_DATA 0xffffffff +#define DENALI_CTL_320_DATA 0x00030f0f +#define DENALI_CTL_321_DATA 0xffffffff +#define DENALI_CTL_322_DATA 0x00030f0f +#define DENALI_CTL_323_DATA 0xffffffff +#define DENALI_CTL_324_DATA 0x00030f0f +#define DENALI_CTL_325_DATA 0xffffffff +#define DENALI_CTL_326_DATA 0x00030f0f +#define DENALI_CTL_327_DATA 0xffffffff +#define DENALI_CTL_328_DATA 0x00030f0f +#define DENALI_CTL_329_DATA 0xffffffff +#define DENALI_CTL_330_DATA 0x00030f0f +#define DENALI_CTL_331_DATA 0xffffffff +#define DENALI_CTL_332_DATA 0x00030f0f +#define DENALI_CTL_333_DATA 0xffffffff +#define DENALI_CTL_334_DATA 0x00030f0f +#define DENALI_CTL_335_DATA 0xffffffff +#define DENALI_CTL_336_DATA 0x00030f0f +#define DENALI_CTL_337_DATA 0xffffffff +#define DENALI_CTL_338_DATA 0x00030f0f +#define DENALI_CTL_339_DATA 0xffffffff +#define DENALI_CTL_340_DATA 0x00030f0f +#define DENALI_CTL_341_DATA 0xffffffff +#define DENALI_CTL_342_DATA 0x00030f0f +#define DENALI_CTL_343_DATA 0xffffffff +#define DENALI_CTL_344_DATA 0x00030f0f +#define DENALI_CTL_345_DATA 0xffffffff +#define DENALI_CTL_346_DATA 0x32030f0f +#define DENALI_CTL_347_DATA 0x01320001 +#define DENALI_CTL_348_DATA 0x00013200 +#define DENALI_CTL_349_DATA 0x00000132 +#define DENALI_CTL_350_DATA 0x00000000 +#define DENALI_CTL_351_DATA 0x000d0000 +#define DENALI_CTL_352_DATA 0x1e680000 +#define DENALI_CTL_353_DATA 0x02000200 +#define DENALI_CTL_354_DATA 0x02000200 +#define DENALI_CTL_355_DATA 0x00001e68 +#define DENALI_CTL_356_DATA 0x00009808 +#define DENALI_CTL_357_DATA 0x00020608 +#define DENALI_CTL_358_DATA 0x000a0a01 +#define DENALI_CTL_359_DATA 0x00000000 +#define DENALI_CTL_360_DATA 0x00000000 +#define DENALI_CTL_361_DATA 0x04038000 +#define DENALI_CTL_362_DATA 0x07030a07 +#define DENALI_CTL_363_DATA 0x00ffff22 +#define DENALI_CTL_364_DATA 0x000f0010 +#define DENALI_CTL_365_DATA 0x00000000 +#define DENALI_CTL_366_DATA 0x00000000 +#define DENALI_CTL_367_DATA 0x00000000 +#define DENALI_CTL_368_DATA 0x00000000 +#define DENALI_CTL_369_DATA 0x00000000 +#define DENALI_CTL_370_DATA 0x00000204 +#define DENALI_CTL_371_DATA 0x00000000 +#define DENALI_CTL_372_DATA 0x01000001 +#define DENALI_CTL_373_DATA 0x00000001 +#define DENALI_CTL_374_DATA 0x00000000 diff --git a/include/syscon.h b/include/syscon.h index f5e6cc1a4b1..7a5ee3fa26b 100644 --- a/include/syscon.h +++ b/include/syscon.h @@ -25,19 +25,6 @@ struct syscon_ops { #define syscon_get_ops(dev) ((struct syscon_ops *)(dev)->driver->ops) -#if CONFIG_IS_ENABLED(OF_PLATDATA) -/* - * We don't support 64-bit machines. If they are so resource-contrained that - * they need to use OF_PLATDATA, something is horribly wrong with the - * education of our hardware engineers. - * - * Update: 64-bit is now supported and we have an education crisis. - */ -struct syscon_base_plat { - fdt_val_t reg[2]; -}; -#endif - /** * syscon_get_regmap() - Get access to a register map * diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h index b025779d59f..db8a29e9bbd 100644 --- a/include/ubifs_uboot.h +++ b/include/ubifs_uboot.h @@ -21,7 +21,7 @@ int ubifs_init(void); int uboot_ubifs_mount(char *vol_name); void uboot_ubifs_umount(void); int ubifs_is_mounted(void); -int ubifs_load(char *filename, u32 addr, u32 size); +int ubifs_load(char *filename, unsigned long addr, u32 size); int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); int ubifs_ls(const char *dir_name); diff --git a/include/usb.h b/include/usb.h index 80cb8467203..42b001c3dd5 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,12 +11,15 @@ #ifndef _USB_H_ #define _USB_H_ +#include <stdbool.h> #include <fdtdec.h> #include <usb_defs.h> #include <linux/usb/ch9.h> #include <asm/cache.h> #include <part.h> +extern bool usb_started; /* flag for the started/stopped USB status */ + /* * The EHCI spec says that we must align to at least 32 bytes. However, * some platforms require larger alignment. |