diff options
| author | York Sun <[email protected]> | 2018-01-29 09:44:33 -0800 |
|---|---|---|
| committer | York Sun <[email protected]> | 2018-01-30 09:14:06 -0800 |
| commit | 426230a65f2dd62c3b6c1509e9775d5500db20d3 (patch) | |
| tree | 1f500bcdf25fc0ed2a5840bcdecd558173de9da1 /include | |
| parent | a9b1c2164a45e0c1af59b8e7a1c92f2f53babe92 (diff) | |
drivers/ddr/fsl: Fix DDR4 RDIMM support
For DDR4, command/address delay in mode registers and parity latency
in timing config register are only needed for UDIMMs, but not RDIMMs.
Add additional register rcw_3 for DDR4 RDIMM. Fix mirrored bit for
dual rank RDIMMs. Set sdram_cfg_3[DIS_MRS_PAR] for RDIMMs. Fix
calculation of timing config registers. Use hexadecimal format for
printing RCW (register control word) registers.
Signed-off-by: York Sun <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/fsl_ddr_sdram.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 6a1f04b81ac..de7ef9b53ff 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -408,6 +408,7 @@ typedef struct memctl_options_s { unsigned int rcw_override; unsigned int rcw_1; unsigned int rcw_2; + unsigned int rcw_3; /* control register 1 */ unsigned int ddr_cdr1; unsigned int ddr_cdr2; |