Merge tag 'xilinx-for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2019.10

fpga:
- Xilinx virtex2 cleanup
- Altera cyclon2 cleanup

zynq:
- Minor Kconfig cleanup
- Add psu_init configuration for Z-turn board

zynqmp:
- Add support for pmufw config passing to PMU
- script for psu_init conversion
- zcu1275 renaming

xilinx:
- Add support for UltraZed-EV SoM

5 files changed, 14 insertions, 13 deletions

diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index 9814bba2846..7c5253c66cc 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -60,6 +60,16 @@ typedef struct {
 #define Altera_EP2C35_SIZE	883905
 #define Altera_EP3C5_SIZE	368011		/* .rbf size in bytes */
 
+#define ALTERA_EP4CE6_SIZE	368011		/* 2944088 Bits */
+#define ALTERA_EP4CE10_SIZE	368011		/* 2944088 Bits */
+#define ALTERA_EP4CE15_SIZE	510856		/* 4086848 Bits */
+#define ALTERA_EP4CE22_SIZE	718569		/* 5748552 Bits */
+#define ALTERA_EP4CE30_SIZE	1191788		/* 9534304 Bits */
+#define ALTERA_EP4CE40_SIZE	1191788		/* 9534304 Bits */
+#define ALTERA_EP4CE55_SIZE	1861195		/* 14889560 Bits */
+#define ALTERA_EP4CE75_SIZE	2495719		/* 19965752 Bits */
+#define ALTERA_EP4CE115_SIZE	3571462		/* 28571696 Bits */
+
 /* Descriptor Macros
  *********************************************************************/
 /* ACEX1K devices */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 684faaee2e8..bbcb20737b0 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -62,7 +62,6 @@
 #if defined(CONFIG_ZYNQMP_USB)
 #define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x1800000
 #define DFU_DEFAULT_POLL_TIMEOUT	300
-#define CONFIG_USB_CABLE_CHECK
 #define CONFIG_THOR_RESET_OFF
 #define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index b51914d1e02..62fbf8866f0 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -65,7 +65,6 @@
 
 # define CONFIG_SYS_DFU_DATA_BUF_SIZE	0x600000
 # define DFU_DEFAULT_POLL_TIMEOUT	300
-# define CONFIG_USB_CABLE_CHECK
 # define CONFIG_THOR_RESET_OFF
 # define DFU_ALT_INFO_RAM \
 	"dfu_ram_info=" \
diff --git a/include/fpga.h b/include/fpga.h
index 51de5c55f83..ec5144334df 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -15,7 +15,7 @@
 
 /* fpga_xxxx function return value definitions */
 #define FPGA_SUCCESS		0
-#define FPGA_FAIL		-1
+#define FPGA_FAIL		1
 
 /* device numbers must be non-negative */
 #define FPGA_INVALID_DEVICE	-1
diff --git a/include/virtex2.h b/include/virtex2.h
index a48113060e7..7e8d93f24da 100644
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -11,7 +11,7 @@
 #include <xilinx.h>
 
 /*
- * Slave SelectMap Implementation function table.
+ * Slave SelectMap or Serial Implementation function table.
  */
 typedef struct {
 	xilinx_pre_fn	pre;
@@ -24,18 +24,11 @@ typedef struct {
 	xilinx_wr_fn	wr;
 	xilinx_rdata_fn	rdata;
 	xilinx_wdata_fn	wdata;
+	xilinx_bwr_fn   wbulkdata;
 	xilinx_busy_fn	busy;
 	xilinx_abort_fn	abort;
 	xilinx_post_fn	post;
-} xilinx_virtex2_slave_selectmap_fns;
-
-/* Slave Serial Implementation function table */
-typedef struct {
-	xilinx_pgm_fn	pgm;
-	xilinx_clk_fn	clk;
-	xilinx_rdata_fn	rdata;
-	xilinx_wdata_fn	wdata;
-} xilinx_virtex2_slave_serial_fns;
+} xilinx_virtex2_slave_fns;
 
 #if defined(CONFIG_FPGA_VIRTEX2)
 extern struct xilinx_fpga_op virtex2_op;