diff options
| author | Tom Rini <[email protected]> | 2025-06-20 07:59:34 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-06-20 07:59:34 -0600 |
| commit | 4bbfd1c04277d83783266fae754b2227cbc5caae (patch) | |
| tree | e2f5b4822110a7cda34c6979b97fd45f6bd01b7b /include | |
| parent | 5ba5cbf5a29d54763f30b6685e6c06ffd51d29eb (diff) | |
| parent | 9b9a2c99946a7ad43d9716618ae48ea01947f5fa (diff) | |
Merge tag 'u-boot-at91-2025.10-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2025.10 cycle:
This feature set includes the addition of new sam9x7 SoC and a new board
named sam9x7-curiosity. There is also new support for sam9x60 compatible
at91 watchdog.
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/sam9x75_curiosity.h | 23 | ||||
| -rw-r--r-- | include/configs/sama5d27_wlsom1_ek.h | 6 |
2 files changed, 23 insertions, 6 deletions
diff --git a/include/configs/sam9x75_curiosity.h b/include/configs/sam9x75_curiosity.h new file mode 100644 index 00000000000..62a855d9f01 --- /dev/null +++ b/include/configs/sam9x75_curiosity.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAM9X75 CURIOSITY board. + * + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan <[email protected]> + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +#define CFG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_ID 0 /* ignored in arm */ + +/* SDRAM */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ + +#endif diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 1979cb366e5..b54e3d5c710 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -15,10 +15,4 @@ #undef CFG_SYS_AT91_MAIN_CLOCK #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -/* SDRAM */ -#define CFG_SYS_SDRAM_BASE 0x20000000 -#define CFG_SYS_SDRAM_SIZE 0x10000000 - -/* SPL */ - #endif |