spi: designware_spi: revisit FIFO size detection again

By specification the FIFO size would be in a range 2-256 bytes. From TX Level
prospective it means we can set threshold in the range 0-(FIFO size - 1) bytes.
Hence there are currently two issues:
  a) FIFO size 2 bytes is actually skipped since TX Level is 1 bit and could be
     either 0 or 1 byte;
  b) FIFO size is incorrectly decreased by 1 which already done by meaning of
     TX Level register.

Fixes: 501943696ea4 (spi: designware_spi: Fix detecting FIFO depth)
Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Pavel Machek <[email protected]>
Reviewed-by: Jagannadha Sutradharudu Teki <[email protected]>

0 files changed, 0 insertions, 0 deletions