diff options
| author | Bin Meng <[email protected]> | 2023-06-21 23:11:44 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2023-07-12 13:21:40 +0800 |
| commit | 5764acb2617658af76c25285685e791ce6d0b051 (patch) | |
| tree | db44e07045cc57d1888f8efed317f5228f1423c1 /include | |
| parent | c9745365f516a361be9cbe3568d2b8608084bbbf (diff) | |
riscv: timer: Update the sifive clint timer driver to support aclint
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Rick Chen <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/qemu-riscv.h | 2 | ||||
| -rw-r--r-- | include/configs/sifive-unleashed.h | 2 | ||||
| -rw-r--r-- | include/configs/starfive-visionfive2.h | 1 |
3 files changed, 3 insertions, 2 deletions
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569eb..f6d326bda0d 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index de3a0dcdd59..f208f5e20db 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -14,8 +14,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 93dcc22d366..4ee02b8420f 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -9,6 +9,7 @@ #define _STARFIVE_VISIONFIVE2_H #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 4000000 #define RISCV_SMODE_TIMER_FREQ 4000000 |