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authorMarek Vasut <[email protected]>2020-12-01 11:34:48 +0100
committerPatrick Delaunay <[email protected]>2021-01-13 09:52:58 +0100
commit69ea30e688c4171830b94cd56d936ef6456877df (patch)
tree6d4f01244e1c32435ae566aa36332936ce3d3898 /include
parent635e233b220b7fa4f4e8e8623f971b5cf66c4856 (diff)
ARM: dts: stm32: Switch to MCO2 for PHY 50 MHz clock
The LAN8710i PHY currently uses 50 MHz clock direct from PLL4P. To permit PLL4P to run at faster frequency, use MCO2 as a divider. The PLL4P runs at 100 MHz, supplies MCO2 which divides it by 2 to 50MHz, and supplies the PHY with 50 MHz via pin PG2. The feedback clock are fed back in via pin PA1. Signed-off-by: Marek Vasut <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Reviewed-by: Patrice Chotard <[email protected]> Reviewed-by: Patrick Delaunay <[email protected]> Change-Id: Ia9bf7119785d49b633a3ae761c3dc4a30b92628a
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