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| author | Joakim Tjernlund <[email protected]> | 2017-09-12 19:56:41 +0200 |
|---|---|---|
| committer | York Sun <[email protected]> | 2018-08-08 08:23:48 -0700 |
| commit | 6ce83fb3d6ac1cd25772b3c8c1265afbfa42f718 (patch) | |
| tree | c34f38c831d61a5f2943ff96658f1f98e764061f /include | |
| parent | b2486b40dce98ca26bcb6e1dda69efb1b0443b9a (diff) | |
FSL PCI: Configure PCIe reference ratio
Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.
Signed-off-by: Joakim Tjernlund <[email protected]>
Reviewed-by: York Sun <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions