clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen

Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed.

Signed-off-by: Christian Marangi <[email protected]>

1 files changed, 61 insertions, 89 deletions

diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h
index 0048d183389..478538d7cce 100644
--- a/include/dt-bindings/clock/mt7986-clk.h
+++ b/include/dt-bindings/clock/mt7986-clk.h
@@ -19,95 +19,67 @@
 #define CK_TOP_XTAL_D2			1
 #define CK_TOP_RTC_32K			2
 #define CK_TOP_RTC_32P7K		3
-#define CK_TOP_NFI1X			4
-#define CK_TOP_USB_EQ_RX250M		5
-#define CK_TOP_USB_TX250M		6
-#define CK_TOP_USB_LN0_CK		7
-#define CK_TOP_USB_CDR_CK		8
-#define CK_TOP_SPINFI_BCK		9
-#define CK_TOP_I2C_BCK			10
-#define CK_TOP_PEXTP_TL			11
-#define CK_TOP_EMMC_250M		12
-#define CK_TOP_EMMC_416M		13
-#define CK_TOP_F_26M_ADC_CK		14
-#define CK_TOP_SYSAXI			15
-#define CK_TOP_NETSYS_WED_MCU		16
-#define CK_TOP_NETSYS_2X		17
-#define CK_TOP_SGM_325M			18
-#define CK_TOP_A1SYS			19
-#define CK_TOP_EIP_B			20
-#define CK_TOP_F26M			21
-#define CK_TOP_AUD_L			22
-#define CK_TOP_A_TUNER			23
-#define CK_TOP_U2U3_REF			24
-#define CK_TOP_U2U3_SYS			25
-#define CK_TOP_U2U3_XHCI		26
-#define CK_TOP_AP2CNN_HOST		27
-#define CK_TOP_CB_MPLL_416M		28
-#define CK_TOP_MPLL_D2			29
-#define CK_TOP_MPLL_D4			30
-#define CK_TOP_MPLL_D8			31
-#define CK_TOP_MPLL_D8_D2		32
-#define CK_TOP_MPLL_D3_D2		33
-#define CK_TOP_MMPLL_D2			34
-#define CK_TOP_MMPLL_D4			35
-#define CK_TOP_MMPLL_D8			36
-#define CK_TOP_MMPLL_D8_D2		37
-#define CK_TOP_MMPLL_D3_D8		38
-#define CK_TOP_MMPLL_U2PHYD		39
-#define CK_TOP_CB_APLL2_196M		40
-#define CK_TOP_APLL2_D4			41
-#define CK_TOP_NET1PLL_D4		42
-#define CK_TOP_NET1PLL_D5		43
-#define CK_TOP_NET1PLL_D5_D2		44
-#define CK_TOP_NET1PLL_D5_D4		45
-#define CK_TOP_NET1PLL_D8_D2		46
-#define CK_TOP_NET1PLL_D8_D4		47
-#define CK_TOP_CB_NET2PLL_800M		48
-#define CK_TOP_NET2PLL_D4		49
-#define CK_TOP_NET2PLL_D4_D2		50
-#define CK_TOP_NET2PLL_D3_D2		51
-#define CK_TOP_CB_WEDMCUPLL_760M	52
-#define CK_TOP_WEDMCUPLL_D5_D2		53
-#define CK_TOP_CB_SGMPLL_325M		54
-#define CK_TOP_NFI1X_SEL		55
-#define CK_TOP_SPINFI_SEL		56
-#define CK_TOP_SPI_SEL			57
-#define CK_TOP_SPIM_MST_SEL		58
-#define CK_TOP_UART_SEL			59
-#define CK_TOP_PWM_SEL			60
-#define CK_TOP_I2C_SEL			61
-#define CK_TOP_PEXTP_TL_SEL		62
-#define CK_TOP_EMMC_250M_SEL		63
-#define CK_TOP_EMMC_416M_SEL		64
-#define CK_TOP_F_26M_ADC_SEL		65
-#define CK_TOP_DRAMC_SEL		66
-#define CK_TOP_DRAMC_MD32_SEL		67
-#define CK_TOP_SYSAXI_SEL		68
-#define CK_TOP_SYSAPB_SEL		69
-#define CK_TOP_ARM_DB_MAIN_SEL		70
-#define CK_TOP_ARM_DB_JTSEL		71
-#define CK_TOP_NETSYS_SEL		72
-#define CK_TOP_NETSYS_500M_SEL		73
-#define CK_TOP_NETSYS_MCU_SEL		74
-#define CK_TOP_NETSYS_2X_SEL		75
-#define CK_TOP_SGM_325M_SEL		76
-#define CK_TOP_SGM_REG_SEL		77
-#define CK_TOP_A1SYS_SEL		78
-#define CK_TOP_CONN_MCUSYS_SEL		79
-#define CK_TOP_EIP_B_SEL		80
-#define CK_TOP_PCIE_PHY_SEL		81
-#define CK_TOP_USB3_PHY_SEL		82
-#define CK_TOP_F26M_SEL			83
-#define CK_TOP_AUD_L_SEL		84
-#define CK_TOP_A_TUNER_SEL		85
-#define CK_TOP_U2U3_SEL			86
-#define CK_TOP_U2U3_SYS_SEL		87
-#define CK_TOP_U2U3_XHCI_SEL		88
-#define CK_TOP_DA_U2_REFSEL		89
-#define CK_TOP_DA_U2_CK_1P_SEL		90
-#define CK_TOP_AP2CNN_HOST_SEL		91
-#define CLK_TOP_NR_CLK			92
+#define CK_TOP_A_TUNER			4
+#define CK_TOP_MPLL_D2			5
+#define CK_TOP_MPLL_D4			6
+#define CK_TOP_MPLL_D8			7
+#define CK_TOP_MPLL_D8_D2		8
+#define CK_TOP_MPLL_D3_D2		9
+#define CK_TOP_MMPLL_D2			10
+#define CK_TOP_MMPLL_D4			11
+#define CK_TOP_MMPLL_D8			12
+#define CK_TOP_MMPLL_D8_D2		13
+#define CK_TOP_MMPLL_D3_D8		14
+#define CK_TOP_MMPLL_U2PHYD		15
+#define CK_TOP_APLL2_D4			16
+#define CK_TOP_NET1PLL_D4		17
+#define CK_TOP_NET1PLL_D5		18
+#define CK_TOP_NET1PLL_D5_D2		19
+#define CK_TOP_NET1PLL_D5_D4		20
+#define CK_TOP_NET1PLL_D8_D2		21
+#define CK_TOP_NET1PLL_D8_D4		22
+#define CK_TOP_NET2PLL_D4		23
+#define CK_TOP_NET2PLL_D4_D2		24
+#define CK_TOP_NET2PLL_D3_D2		25
+#define CK_TOP_WEDMCUPLL_D5_D2		26
+#define CK_TOP_NFI1X_SEL		27
+#define CK_TOP_SPINFI_SEL		28
+#define CK_TOP_SPI_SEL			29
+#define CK_TOP_SPIM_MST_SEL		30
+#define CK_TOP_UART_SEL			31
+#define CK_TOP_PWM_SEL			32
+#define CK_TOP_I2C_SEL			33
+#define CK_TOP_PEXTP_TL_SEL		34
+#define CK_TOP_EMMC_250M_SEL		35
+#define CK_TOP_EMMC_416M_SEL		36
+#define CK_TOP_F_26M_ADC_SEL		37
+#define CK_TOP_DRAMC_SEL		38
+#define CK_TOP_DRAMC_MD32_SEL		39
+#define CK_TOP_SYSAXI_SEL		40
+#define CK_TOP_SYSAPB_SEL		41
+#define CK_TOP_ARM_DB_MAIN_SEL		42
+#define CK_TOP_ARM_DB_JTSEL		43
+#define CK_TOP_NETSYS_SEL		44
+#define CK_TOP_NETSYS_500M_SEL		45
+#define CK_TOP_NETSYS_MCU_SEL		46
+#define CK_TOP_NETSYS_2X_SEL		47
+#define CK_TOP_SGM_325M_SEL		48
+#define CK_TOP_SGM_REG_SEL		49
+#define CK_TOP_A1SYS_SEL		50
+#define CK_TOP_CONN_MCUSYS_SEL		51
+#define CK_TOP_EIP_B_SEL		52
+#define CK_TOP_PCIE_PHY_SEL		53
+#define CK_TOP_USB3_PHY_SEL		54
+#define CK_TOP_F26M_SEL			55
+#define CK_TOP_AUD_L_SEL		56
+#define CK_TOP_A_TUNER_SEL		57
+#define CK_TOP_U2U3_SEL			58
+#define CK_TOP_U2U3_SYS_SEL		59
+#define CK_TOP_U2U3_XHCI_SEL		60
+#define CK_TOP_DA_U2_REFSEL		61
+#define CK_TOP_DA_U2_CK_1P_SEL		62
+#define CK_TOP_AP2CNN_HOST_SEL		63
+#define CLK_TOP_NR_CLK			64
 
 /*
  * INFRACFG_AO