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authorTom Rini <[email protected]>2024-02-14 15:23:10 -0500
committerTom Rini <[email protected]>2024-02-14 15:23:10 -0500
commit77ff61a5bb437b5b19c50d8791f14a3b917e882c (patch)
treeee0d8f7efd458c4246b41eb10a0d2fcdf8ffe86e /include
parent37345abb97ef0dd9c50a03b2a72617612dcae585 (diff)
parentc2ad5fb616d4e8aa2ac00e224030589847731fbe (diff)
Merge tag 'xilinx-for-v2024.04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.04-rc3 zynqmp: - Cover missing _SE chip variants to fix fpga programming versal: - Enable LTO for mini configurations versal-net: - Enable LTO for mini configurations - Fix GIC address to aligned with real silicon xilinx: - DTs cleanup and fixups - Enable HTTP boot - Add missing spl header to zynqmp.c
Diffstat (limited to 'include')
-rw-r--r--include/configs/xilinx_versal_net.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h
index 2b441da91a1..9cb6b2bfea3 100644
--- a/include/configs/xilinx_versal_net.h
+++ b/include/configs/xilinx_versal_net.h
@@ -16,8 +16,8 @@
/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0xF9000000
-#define GICR_BASE 0xF9060000
+#define GICD_BASE 0xe2000000
+#define GICR_BASE 0xe2060000
/* Serial setup */
#define CFG_SYS_BAUDRATE_TABLE \