Merge tag 'xilinx-for-v2025.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

AMD/Xilinx/FPGA changes for v2025.10-rc1 v2

zynqmp:
- Generate fit-dtb.blob all the time
- Simplify power-domain driver bind

zynqmp_mini:
- Remove PSCI_RESET

fpga:
- Improve user feedback in case of FPGA bitstream load failure

misc:
- Fix kernel-doc in gpio zynq and axi_mrmac

spi:
- Revert fix in STIG mode

[trini: Remove CONFIG_FPGA_VERSALPL=y from sandbox due to
        sandbox+clang+asan test problem]
Signed-off-by: Tom Rini <[email protected]>

2 files changed, 4 insertions, 4 deletions

diff --git a/include/fpga.h b/include/fpga.h
index 4cc44164b2f..a144238e66a 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -79,7 +79,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
 int fpga_dump(int devnum, const void *buf, size_t bsize);
 int fpga_info(int devnum);
 const fpga_desc *fpga_validate(int devnum, const void *buf,
-			       size_t bsize, char *fn);
+			       size_t bsize);
 int fpga_compatible2flag(int devnum, const char *compatible);
 
 #endif	/* _FPGA_H_ */
diff --git a/include/stratixII.h b/include/stratixII.h
index 3c06bb2955a..785cdf41cb8 100644
--- a/include/stratixII.h
+++ b/include/stratixII.h
@@ -6,8 +6,8 @@
 #ifndef _STRATIXII_H_
 #define _STRATIXII_H_
 
-extern int StratixII_load (Altera_desc * desc, void *image, size_t size);
-extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize);
-extern int StratixII_info (Altera_desc * desc);
+int StratixII_load(Altera_desc *desc, const void *buf, size_t size);
+int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize);
+int StratixII_info(Altera_desc *desc);
 
 #endif				/* _STRATIXII_H_ */