Squashed 'dts/upstream/' changes from 4d52919c55f4..08831944f4e7

08831944f4e7 Merge tag 'v6.18-dts-raw'
e841b58a158a Merge tag 'soc-fixes-6.18-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
39170f727a25 Merge tag 'sunxi-fixes-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
e9f0786f8e53 Merge tag 'v6.18-rc7-dts-raw'
5abff9069f15 Merge tag 'mips-fixes_6.18_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
c619d09bc2a6 Merge tag 'input-for-v6.18-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
77873560a276 riscv: dts: allwinner: d1: fix vlenb property
41ed2a4ab2c6 Merge tag 'imx-fixes-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
1fa9bb6519ee Merge tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
16355683758e dt-bindings: pinctrl: xlnx,versal-pinctrl: Add missing unevaluatedProperties on '^conf' nodes
e0fd60dd80bf Merge tag 'v6.18-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
cdcd6bfe3736 Input: rename INPUT_PROP_HAPTIC_TOUCHPAD to INPUT_PROP_PRESSUREPAD
0549a59f2769 arm64: dts: imx8qm-mek: fix mux-controller select/enable-gpios polarity
b78811c3f8ff Merge tag 'arm-soc/for-6.18/devicetree-arm64-fixes-v2' of https://github.com/Broadcom/stblinux into arm/fixes
7243a2ca6f79 Merge tag 'arm-soc/for-6.18/devicetree-fixes-part2' of https://github.com/Broadcom/stblinux into arm/fixes
686012a81a67 Merge tag 'imx-fixes-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
a33786d352e1 Merge tag 'aspeed-6.18-fixes-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into arm/fixes
54903efc29cc Merge tag 'tegra-for-6.18-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
8159bf6bc307 arm64: dts: rockchip: fix PCIe 3.3V regulator voltage on orangepi-5
5499e2a55d2a arm64: dts: rockchip: disable HS400 on RK3588 Tiger
894188faaba0 arm64: dts: rockchip: drop reset from rk3576 i2c9 node
7871010daca0 mips: dts: econet: fix EN751221 core type
cf42ab9b90d9 ARM: dts: nxp: imx6ul: correct SAI3 interrupt line
cff4d036ba5d arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos
4361a3b60f4c arm64: dts: imx8dxl: Correct pcie-ep interrupt number
3269d1383f31 Merge tag 'v6.18-rc5-dts-raw'
228e8634eb6c Merge tag 'gpio-fixes-for-v6.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
244da4da7149 arm64: dts: rockchip: Fix USB power enable pin for BTT CB2 and Pi2
0017e64d4c71 Merge tag 'platform-drivers-x86-v6.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
bbb189420a69 arm64: dts: broadcom: bcm2712: rpi-5: Add ethernet0 alias
3fc465e4809d arm64: dts: broadcom: Assign clock rates in eth node for RPi5
94b152a741e8 ARM: dts: BCM53573: Fix address of Luxul XAP-1440's Ethernet PHY
d1507a3f9753 dt-bindings: gpio: ti,twl4030: Correct the schema $id path
b1c7a2850906 Merge tag 'v6.18-rc4-dts-raw'
4151b9236833 arm64: dts: rockchip: Fix vccio4-supply on rk3566-pinetab2
8b15ff90ce93 arm64: dts: rockchip: include rk3399-base instead of rk3399 in rk3399-op1
ec884da0ca6b Merge tag 'sound-6.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
7a964ccce3bc Merge tag 'net-6.18-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
5eef9306d2b2 ASoC: dt-bindings: pm4125-sdw: correct number of soundwire ports
903215514653 Input: Add keycodes for electronic privacy screen on/off hotkeys
0586567f9bab Merge tag 'v6.18-rc3-dts-raw'
322f4f061398 arm64: dts: imx8mp-kontron: Fix USB OTG role switching
867498ab6161 dt-bindings: net: sparx5: Narrow properly LAN969x register space windows
4ee9a255dc06 arm64: dts: imx95: Fix MSI mapping for PCIe endpoint nodes
c568a74a3e4d arm64: dts: imx8-ss-img: Avoid gpio0_mipi_csi GPIOs being deferred
9ed8688b79b6 Merge tag 'tty-6.18-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
3fd67994b13e Merge tag 'usb-6.18-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
503e4204284b Merge tag 'soc-fixes-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
46a50a92b4a6 Merge tag 'spi-fix-v6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
936ecbc6e501 Merge tag 'arm-soc/for-6.18/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes
98469e86b44f dt-bindings: pinctrl: toshiba,visconti: Fix number of items in groups
b7f04f80d750 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
41caf35d5645 spi: dt-bindings: spi-rockchip: Add RK3506 compatible
9e3ee5db9e70 dt-bindings: serial: sh-sci: Fix r8a78000 interrupts
3f77eab0f1e0 Merge tag 'v6.18-rc2-dts-raw'
2759bbffd9d2 arm64: dts: rockchip: Fix indentation on rk3399 haikou demo dtso
25599cc3738d ARM: dts: imx51-zii-rdu1: Fix audmux node names
b32a66085455 ARM: dts: imx6ull-engicam-microgea-rmm: fix report-rate-hz value
a81001d3a83e Merge tag 'sound-6.18-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
d85a0ded1941 ARM: dts: aspeed: fuji-data64: Enable mac3 controller
517683e7714c ASoC: Add QCS615 sound card support
e8de45bae3eb arm64: tegra: Mark Jetson Xavier NX's PHY as a wakeup source
58300460b0a5 ASoC: dt-bindings: Add compatible string fsl,imx-audio-tlv320
d727c37c3ab7 arm64: dts: rockchip: Make RK3588 GPU OPP table naming less generic
7ad1203e7d2b arm64: dts: rockchip: Drop 'rockchip,grf' prop from tsadc on rk3328
b2c138ea1248 arm64: dts: rockchip: Remove non-functioning CPU OPPs from RK3576
7b953f6f3a03 arm64: dts: rockchip: Fix PCIe power enable pin for BigTreeTech CB2 and Pi2
7d90aff77c4e arm64: dts: rockchip: Set correct pinctrl for I2S1 8ch TX on odroid-m1
cd2aaa2d845f dt-bindings: i2c: Convert apm,xgene-slimpro-i2c to DT schema
43619ef8a901 Merge branch '6.18/scsi-queue' into 6.18/scsi-fixes
e8592302eccd ARM: dts: broadcom: rpi: Switch to V3D firmware clock
b6d8f5beb2cd arm64: dts: broadcom: bcm2712: Define VGIC interrupt
2809c9680f30 spi: Merge up v6.18-rc1
c764697fe251 ASoC: tas2781: Update ti,tas2781.yaml for adding tas58xx
d05f266f23ab ASoC: dt-bindings: qcom,sm8250: Add QCS615 sound card
71f3189ea79e dt-bindings: usb: qcom,snps-dwc3: Fix bindings for X1E80100
17a05c8253c8 dt-bindings: usb: switch: split out ports definition
6c1cec8bf7fc dt-bindings: usb: dwc3-imx8mp: dma-range is required only for imx8mp
4fc38e39092c Merge tag 'v6.18-rc1-dts-raw'
de0470cbae03 Merge tag 'rtc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
c3a773fa1208 Merge tag 'devicetree-fixes-for-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
f5cbb7c8268d dt-bindings: bus: renesas-bsc: allow additional properties
7d218c6d8b04 dt-bindings: bus: allwinner,sun50i-a64-de2: don't check node names
7940f5e69c67 Merge tag 'i2c-for-6.18-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
5bb4dfaa66f3 dt-bindings: i2c: hisilicon,hix5hd2: convert to DT schema
2d049f37eaf6 Merge tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
ff46d56507a5 Merge tag 'input-for-v6.18-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
845f8f8d67c0 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
1d973f603340 scsi: ufs: phy: dt-bindings: Add QMP UFS PHY compatible for Kaanapali
b8949190e6af scsi: ufs: qcom: dt-bindings: Document the Kaanapali UFS controller
564d968edfb9 dt-bindings: mailbox: Add MT8196 GPUEB Mailbox
09c16ff644ef dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
570e237659ae dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding
dedfb01a1c3d Merge branches 'clk-aspeed' and 'clk-rockchip' into clk-next
8660ea6835c5 Merge tag 'linux-watchdog-6.18-rc1' of git://www.linux-watchdog.org/linux-watchdog
fd8a7414ed9c Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next
bf5308d84dc0 Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next
7a6dfc334958 Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next
bb6f21a2eab1 Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next
8bec3c9dde0f Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
2292e8120c5c Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next
78a14fd472ee Merge tag 'pci-v6.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
de186e77d19d Merge tag 'dmaengine-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
28a5e1fb4c45 Merge tag 'phy-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
4794a05abcf1 Merge tag 'ata-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
5398c7a0c659 dt-bindings: rtc: Convert apm,xgene-rtc to DT schema
934a619dd311 Merge tag 'mips_6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
1716ed709f8f Merge tag 'char-misc-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
168488bd1037 Merge tag 'usb-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
677aec7df0d4 Merge tag 'tty-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
428f86048f33 Merge tag 'mtd/for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
b249fb5b314d Merge tag 'rproc-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
d896aaaa3f4c Merge tag 'hid-for-linus-2025093001' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
8443d1c20194 Merge tag 'platform-drivers-x86-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86
38ab97438fb0 Merge tag 'v6.18-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
75a25edacaea Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
1545e4aa056d Merge tag 'i2c-host-6.18-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
0a09d15734fd dt-bindings: i2c: realtek,rtl9301-i2c: extend for RTL9310 support
cda2f36343e3 dt-bindings: i2c: realtek,rtl9301-i2c: fix wording and typos
3e4101a94d62 Merge tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
9ff73a85a570 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
d9d607321637 Merge tag 'docs-6.18' of git://git.lwn.net/linux
053af8446dcb Merge branch 'pci/controller/stm32'
e1b21802b057 Merge branch 'pci/controller/sophgo'
5008bd934bb9 Merge branch 'pci/controller/mediatek-gen3'
bf1719dbb5ce Merge branch 'pci/controller/amd-mdb'
82b0a0a5e990 Merge tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
c5f724026a23 Merge tag 'media/v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
8a782dd24f67 Merge tag 'drm-next-2025-10-01' of https://gitlab.freedesktop.org/drm/kernel
9721d6737772 Merge tag 'sound-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
2c52d7408beb spi: dt-bindings: cadence: add soc-specific compatible strings for zynqmp and versal-net
b48f196041fb Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
1f56b7e4f995 Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
6eba5be14319 Merge tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c56390ab2f4c Merge tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
8a791cad48d2 Merge tag 'thermal-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
4a0f143ed581 Merge tag 'pm-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
5c0ca4621858 Merge tag 'i3c/for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
f0c6e92d7c6b Merge tag 'i2c-for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
0e7edb6068a7 Merge tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
594897eb42bb Merge tag 'for-linus-6.18-1' of https://github.com/cminyard/linux-ipmi
b2be7ef32a99 Merge tag 'for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
91f4df7c80c8 Merge tag 'leds-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
dba793224811 Merge tag 'mfd-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
38848f8bf84a Merge tag 'mmc-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
204f6a8b0709 Merge tag 'pmdomain-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
9b588d8b5363 Merge tag 'spi-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
016c3efc7827 Merge tag 'regulator-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
51be3e99d5c3 Merge tag 'gpio-updates-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
31fe31e908d2 Merge tag 'pwm/for-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
dcc798bf424a Merge tag 'hwmon-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
b1480164cdb8 dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings
9f599b02944e dt-bindings: mmc: Correct typo "upto" to "up to"
9ae67dcdf8cb dt-bindings: mfd: twl: Add missing sub-nodes for TWL4030 & TWL603x
4694868f891f dt-bindings: watchdog: Add SMARC-sAM67 support
d34fa3e97108 dt-bindings: mfd: tps6594: Allow gpio-line-names
7befb8a27553 dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
629a916a07c1 dt-bindings: mfd: Convert aspeed,ast2400-p2a-ctrl to DT schema
be6bfca6fc8e dt-bindings: mfd: fsl,mc13xxx: Add buttons node
3d2276743b6d dt-bindings: mfd: fsl,mc13xxx: Convert txt to DT schema
bfea5a67f2ef dt-bindings: mfd: syscon: Document the control-scb syscon on PolarFire SoC
9a87778d5560 dt-bindings: mfd: Add support the SpacemiT P1 PMIC
b2b11df054fc dt-bindings: mfd: sl28cpld: Add sa67mcu compatible
8df7d5ca4268 dt-bindings: mfd: Move embedded controllers to own directory
5e3cb2f01ea7 dt-bindings: mfd: syscon: Add "marvell,armada-3700-usb2-host-device-misc" compatible
9b87c54c3556 dt-bindings: mfd: aspeed-lpc: Add missing "clocks" property on lpc-snoop node
473ad863c485 dt-bindings: mfd: qnap,ts433-mcu: Allow nvmem-layout child node
6b7353e610b5 dt-bindings: mfd: qnap,ts433-mcu: Add qnap,ts233-mcu compatible
177df608f976 Merge branches 'ib-mfd-char-crypto-6.18', 'ib-mfd-gpio-6.18', 'ib-mfd-gpio-hwmon-i2c-can-rtc-watchdog-6.18', 'ib-mfd-gpio-input-pinctrl-pwm-6.18', 'ib-mfd-input-6.18', 'ib-mfd-input-rtc-6.18' and 'ib-mfd-power-regulator-6.18' into ibs-for-mfd-merged
74170ed49214 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1c1bb3d0c25d dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible
22041f2f1575 Merge tag 'timers-clocksource-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
efb4c0c10d40 Merge tag 'irq-drivers-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
a84811c71829 Merge tag 'edac_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
319a6cde69bb Merge branch 'for-6.18/haptic' into for-linus
bce788ad3d12 Merge branch 'for-6.18/core' into for-linus
1a2d0da1e503 Merge tag 'riscv-for-linus-6.18-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
ec5ed566c69a Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
99c7e89afb86 dt-bindings: mtd: Add realtek,rtl9301-ecc
26cd750d58df dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
f075079dd0d5 Merge tag 'asoc-v6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
10a4ec9efe54 dt-bindings: watchdog: add SMARC-sAM67 support
40520b1a7c2f dt-bindings: input: Add Awinic AW86927
cd2e9cfc3f3b dt-bindings: rng: hisi-rng: convert to DT schema
9954fce9c8cf dt-bindings: i2c: i2c-mt65xx: Add MediaTek MT8196/6991 compatibles
bbfd144444cf Merge tag 'i2c-host-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
7600ec6c05ed dt-bindings: net: cdns,macb: allow tsu_clk without tx_clk
7547752db920 dt-bindings: net: dsa: nxp,sja1105: Add reset-gpios property
08c0795b0a45 dt-bindings: gpu: Convert nvidia,gk20a to DT schema
3f5fdb74bd77 dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
2d9db654d43c dt-bindings: net: sparx5: correct LAN969x register space windows
d68ed67bf381 dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
e883f596c93d dt-bindings: vendor-prefixes: update regex for properties without a prefix
faec16722844 dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
d0283fff5061 dt-bindings: fix spelling, typos, grammar, duplicated words
833f1b0f6b71 Merge tag 'thermal-v6.18-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
45c858eaf300 dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
10fab40c90c4 dt-bindings: soc: mediatek: pwrap: Add power-domains property
57499b3beba1 dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
79cc954ce5f0 dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
b419e5c86956 dt-bindings: arm: mediatek: Support mt8183-audiosys variant
382b81dd64c3 dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
39ec7f275c2f dt-bindings: regulator: mediatek,mt6331: Add missing compatible
5b98cc3c3352 dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
f3796c9f43b9 dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
776e892d4085 dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
6926112ea443 dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
cb122a6d81e8 dt-bindings: timer: mediatek: Add compatible for MT6795 GP Timer
7dc2c4b2b3d7 dt-bindings: display: mediatek: dpi: Allow specifying resets
e2864d0e36d8 dt-bindings: interrupt-controller: qcom,pdc: Document Glymur PDC
69a88842393f dt-bindings: interrupt-controller: arm,gic: Add tegra264-agic
c35087d37345 dt-bindings: display: simple: Add innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24
9ab849a89061 dt-bindings: gpu: arm,mali-midgard: add exynos8890-mali compatible
7c7c766bdc70 dt-bindings: edac: Convert aspeed,ast2400-sdram-edac to DT schema
48340486cabc dt-bindings: thermal: qcom-tsens: Document the Glymur temperature Sensor
2beac1c3f166 arm64: dts: qcom: x1e80100-t14s: add EC
2dada80d0e34 dt-bindings: hwmon: (lm75) allow interrupt for ti,tmp75
38e925ef3366 dt-bindings: Add RPMI system MSI interrupt controller bindings
300748f7ff9b dt-bindings: Add RPMI system MSI message proxy bindings
6e8fd5a2484f dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
7dd1f0075e4f dt-bindings: thermal: rockchip: Tighten grf requirements
9853b1d75300 dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit
c70d31b356c2 dt-bindings: thermal: add Tegra114 soctherm header
79f7ed4a59a5 dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System
fc1a87d7bcd0 dt-bindings: thermal: tsens: Add QCS615 compatible
8ff49ad28ead dt-bindings: clock: Add RPMI clock service controller bindings
0ba55b71bd8b dt-bindings: clock: Add RPMI clock service message proxy bindings
94d3faf8012b dt-bindings: touchscreen: remove touchscreen.txt
1361ea92bc01 dt-bindings: arm: bcm: raspberrypi,bcm2835-firmware: Add touchscreen child node
c050d20b17c6 dt-bindings: touchscreen: convert eeti bindings to json schema
aea0393975e4 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
cc60a023facd dt-bindings: hwmon: sl28cpld: add sa67mcu compatible
2e2051eeddf6 dt-bindings: leds: as3645: Convert to DT schema
c87d624d0590 riscv: dts: eswin: add HiFive Premier P550 board device tree
3d14d9a6679e riscv: dts: add initial support for EIC7700 SoC
c8f34d95bf48 dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
480d6b6e05e8 dt-bindings: riscv: Add SiFive HiFive Premier P550 board
4578586265fb dt-bindings: riscv: Add SiFive P550 CPU compatible
dcc0e5336db7 dt-bindings: input: pm8941-pwrkey: Document wakeup-source property
ea80e6374801 dt-bindings: input: touchscreen: add hynitron cst816x series
3b4fcbf49c09 Merge patch series "Add DT-based gear and rate limiting support"
84cd8eafde6e scsi: ufs: dt-bindings: Document gear and rate limit properties
44529c04b0f8 dt-bindings: i2c: i2c-mt65xx: Document MediaTek MT6878 I2C
e2dc5e88462d dt-bindings: i2c: samsung,s3c2410-i2c: Drop S3C2410
a3e1d6cb5a0f dt-bindings: net: ethernet-controller: Fix grammar in comment
84279df597fe dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension
31727e081d77 Merge tag 'riscv-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
d51247639e9d dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold
4adff022247d dt-bindings: touchscreen: add debounce-delay-us property
ad4ad8b205c6 Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
886b8d597c27 Merge back earlier cpufreq material for 6.18
386477eb6f36 dt-bindings: trivial-devices: add mps,mp5998
92fac5907dec dt-bindings: timer: exynos4210-mct: Add compatible for ARTPEC-9 SoC
65e9e633eb33 Merge tag 'coresight-next-v6.18-v2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
d7721b5b74f1 ASoC: dt-binding: Convert MediaTek mt8183-mt6358 to DT schema
e780e0ccfdff ASoC: Convert MT8183 DA7219 sound card to DT schema
06e463ef8486 ASoC: dt-binding: Convert mt8183-afe-pcm to dt-schema
6ec0961f01c4 dt-bindings: mailbox: Add bindings for RPMI shared memory transport
af397e51cf24 Merge tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
a08b119d496e Merge tag 'apple-soc-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers
930619ace581 Merge tag 'qcom-drivers-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
8cd625d4d310 Merge tag 'cix-dt-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt
61cba382b701 Merge tag 'at91-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
c3789a733c56 Merge tag 'sunxi-dt-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
937134e66872 Merge tag 'v6.18-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
a3ccd594d690 Merge tag 'qcom-arm64-for-6.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
2e86c05ffc93 Merge tag 'apple-soc-dt-6.18-part2' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
88666287acaa Merge tag 'omap-for-v6.18/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
0569c5d514e0 arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
ea4557793ae6 arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
7d3b0a09aef6 Merge tag 'amlogic-arm64-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
f7307996bf97 Merge tag 'v6.17-rockchip-dtsfixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
6bb5000ecfc4 Merge tag 'spacemit-dt-for-6.18-1' of https://github.com/spacemit-com/linux into soc/dt
69783591949f Merge tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
09f77b4b56a4 Merge tag 'v6.17-next-dts64.2' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
833d00eb55d5 Merge tag 'riscv-sophgo-dt-for-v6.18' of https://github.com/sophgo/linux into soc/dt
1e311ba1e86a Merge tag 'ti-keystone-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
6669aa23c66c Merge tag 'ti-k3-dt-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
314519575e65 dt-bindings: i2c: spacemit,k1-i2c: Minor whitespace cleanup in example
161d4e96ee7b dt-bindings: i2c: exynos5: add samsung,exynos8890-hsi2c compatible
f581ef766bc7 Merge tag 'at24-updates-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
696dba09e88f dt-bindings: mmc: samsung,exynos-dw-mshc: add specific compatible for exynos8890
79afd86cadd5 dt-bindings: arm: Add label in the coresight components
a67b0f200fad Merge tag 'iio-for-6.18a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
efda47062b2f Merge tag 'icc-6.18-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
62061ddd6579 dt: bindings: fsl,vf610-pit: Add compatible for s32g2 and s32g3
ee904954623a regulator: dt-bindings: qcom,sdm845-refgen-regulator: document more platforms
4328f231e4bd regulator: dt-bindings: qcom,sdm845-refgen-regulator: document more platforms
feecfe482b2e dt-bindings: timer: mediatek,timer: Add MediaTek MT8196 compatible
3c5c0ad81897 dt-bindings: timer: Add fsl,timrot.yaml
8f2fc304af8f dt-bindings: timer: fsl,ftm-timer: use items for reg
3ed13b2b25b0 dt-bindings: timer: mediatek: add MT6572
c29c87717c2c dt-bindings: timer: Convert faraday,fttmr010 to DT schema
a793143e2f7f Support reading Subsystem ID from Device Tree
f6b3c97bd97f dt-bindings: embedded-controller: Add Lenovo Thinkpad T14s EC
0b9b400c798f dt-bindings: net: dsa: microchip: Add strap description to set SPI mode
48fa1c66a660 dt-bindings: net: dsa: microchip: Group if clause under allOf tag
7b1f28927040 ARM: dts: microchip: sam9x7: Add qspi controller
0be2d7c97d01 dt-bindings: ata: apm,xgene-ahci: Add apm,xgene-ahci-v2 support
8ad917edccc3 ASoC: dt-bindings: cirrus,cs35l41: Document the cirrus,subsystem-id property
b1209e0fcbeb ASoC: tas2781: Correct the wrong description and register address on tas2781
45482a70ac26 dt-bindings: clock: ast2700: modify soc0/1 clock define
fbf881f7ba37 dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
e69ba49c9649 dt-bindings: clock: samsung,s2mps11: add s2mpg10
93fcd6e76a2d dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
0f4d1e666951 dt-bindings: stm32: add STM32MP21 clocks and reset bindings
8c72bb9204d5 dt-bindings: clock: st: flexgen: remove deprecated compatibles
b80246941237 dt-bindings: clock: mediatek: Describe MT8196 clock controllers
9417eb46bf6f dt-bindings: clock: mt7622: Add AFE_MRGIF clock
42b2b5aa8376 dt-bindings: remoteproc: qcom,milos-pas: Document remoteprocs
6de78bcea3b5 Merge tag 'asoc-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next
6c44da7c1585 dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock
3f2311c885a2 dt-bindings: clock: mediatek: Add power-domains property
4515c37cb58d arm64: dts: qcom: Add MST pixel streams for displayport
b28808e04ea0 arm64: dts: qcom: sm6350: correct DP compatibility strings
c20f0e03c8f1 arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
4fbb962c1a0a arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
1713b1063225 arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
a3953851af6f dt-bindings: arm: marvell: Convert marvell,orion5x boards to DT schema
c48565196ccf dt-bindings: arm: marvell: Convert marvell,dove boards to DT schema
116398de7f0c dt-bindings: arm: marvell: Convert marvell,kirkwood boards to DT schema
f6c62a808539 dt-bindings: arm: marvell: Convert marvell,armada390 boards to DT schema
c71ca2443ed2 dt-bindings: arm: marvell: Convert marvell,armada375 boards to DT schema
8258bf096397 dt-bindings: arm: marvell: Convert marvell,armada-370-xp boards to DT schema
94ea65889280 dt-bindings: input: maxtouch: add common touchscreen properties
02758ab8ecc3 dt-bindings: pci: Add Sophgo SG2042 PCIe host
79e58e20985a dt-bindings: watchdog: Convert nuvoton,npcm-wdt to DT schema
62c03b54fe53 dt-bindings: arm: Add Arm C1 cores and PMUs
75e13105d270 dt-bindings: display: mediatek,ufoe: Add mediatek,gce-client-reg property
32824ecfaa6c dt-bindings: display: mediatek,od: Add mediatek,gce-client-reg property
04d3d0976e8a dt-bindings: edac: Convert apm,xgene-edac to DT schema
4c5b48f1ecb0 dt-binding: thermal: Convert marvell,armada-ap806-thermal to DT schema
f123c58db054 dt-bindings: thermal: Convert marvell,armada370-thermal to DT schema
40dcc83c3518 dt-bindings: watchdog: Convert marvell,armada-3700-wdt to DT schema
d7bb7bc16f8b dt-bindings: mailbox: Convert brcm,iproc-flexrm-mbox to DT schema
630d3897d554 dt-bindings: mailbox: Convert brcm,iproc-pdc-mbox to DT schema
89c90dc61ca6 dt-bindings: mailbox: Convert marvell,armada-3700-rwtm-mailbox to DT schema
7c53b02121b4 dt-bindings: mailbox: Convert rockchip,rk3368-mailbox to DT schema
a91d42e3760f dt-bindings: watchdog: Drop duplicate moxa,moxart-watchdog.txt
6f9bf8c5d914 Add QSPI support for sam9x7 and sama7d65 SoCs
a0378f478d0f arm64: dts: allwinner: h313: Add Amediatech X96Q
a6565ddb26a2 dt-bindings: arm: sunxi: Add Amediatech X96Q
f33520e3553a dt-bindings: riscv: Add xmipsexectl ISA extension description
4be4d54be4ca dt-bindings: touchscreen: convert zet6223 bindings to json schema
bfed910f1ee0 dt-bindings: touchscreen: convert bu21013 bindings to json schema
3d7a4ea10e12 dt-bindings: spi: Define sama7d65 QSPI
0644e2030051 dt-bindings: spi: Document sam9x7 QSPI
51f686eb4ffa arm64: dts: apple: t8015: Add SPMI node
439d4388b229 arm64: dts: apple: t8012: Add SPMI node
bc35ff2c8270 dt-bindings: spmi: Add Apple A11 and T2 compatible
f019428ff379 arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
1da2a7ce7e45 arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
89e9fbe5fe39 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
4b7b5272d002 dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
6e1925d64e29 arm64: dts: rockchip: update pinctrl names for Radxa E52C
999d0b9bc0a8 arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
513b2fd9e001 dt-bindings: perf: fsl-imx-ddr: Add a compatible string fsl,imx94-ddr-pmu for i.MX94
bbaf1fe647d5 Merge tag 'ib-mfd-gpio-input-pinctrl-pwm-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
b012198d6af7 arm64: dts: apple: Add J474s, J475c and J475d device trees
b3801de750e9 arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
f787720f3d1b arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
2347f0d413f5 arm64: dts: apple: Add ethernet0 alias for J375 template
0cde7a3b82a3 dt-bindings: arm: apple: Add t6020x compatibles
ba757c4617c3 dt-bindings: touchscreen: resistive-adc-touch: change to unevaluatedProperties
a751b93d6375 dt-bindings: input: convert tca8418_keypad.txt to yaml format
0e16104ee2c0 dt-bindings: arm: qcom: sort sm8450 boards
783752a0c3dc arm64: dts: qcom: Add base HAMOA-IOT-EVK board
f42ab725663f arm64: dts: qcom: Add HAMOA-IOT-SOM platform
c4441056dc15 dt-bindings: arm: qcom: Document HAMOA-IOT-EVK board
824094fafd08 dt-bindings: soc: qcom,pmic-glink: Add charge limit nvmem properties
2d6dcc585b92 dt-bindings: power: supply: bq24190: document charge enable pin
a5ebb82ce391 dt-bindings: input: touchscreen: document Himax HX852x(ES)
13e6aafdaa3f Merge tag 'ib-mfd-gpio-input-pinctrl-pwm-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
88165d844d70 arm64: dts: qcom: sm8750-mtp: Add WiFi and Bluetooth
bcf48a963297 arm64: dts: qcom: msm8953-xiaomi-daisy: fix cd-gpios
e22d6846736d dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
822534a4d0c2 arm64: dts: qcom: ipq5018: add QUP1 UART2 node
de11f51f577c arm64: dts: qcom: lemans: Flatten usb controller nodes
c4bea63873f7 dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu
a66d746b864b dt-bindings: usb: Document Renesas RZ/G3E USB3HOST
44ffc8679bc6 Merge patch series "Add SpacemiT K1 USB3.0 host controller support"
272141715735 dt-bindings: usb: dwc3: add support for SpacemiT K1
2d660cf074f1 dts: sophgo: sg2042: added numa id description
d77314e2563e dt-bindings: clock: silabs,si5341: Add missing properties
0967f93f4cfb Add PM4125 audio codec driver
628497abdb44 ASoC: codecs: pcm1754: add pcm1754 dac driver
3e647282c835 arm64: dts: qcom: qcs615: Enable TSENS support for QCS615 SoC
26203bb1d634 arm64: dts: qcom: sdm845-enchilada: Add notification LED
c1ac80778709 arm64: dts: qcom: apq8016-sbc: Drop redundant HDMI bridge status
8cfb23d09192 arm64: dts: qcom: apq8016-sbc: Correct HDMI bridge #sound-dai-cells
c7821d537e5a riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
ae7213970a0c dt-bindings: riscv: starfive: add milkv,marscm-lite
8e935d097e97 riscv: dts: starfive: add Milk-V Mars CM system-on-module
4df5d2ff67fa dt-bindings: riscv: starfive: add milkv,marscm-emmc
034af14dcd1e riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants
337dbfd5cf02 arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties
201810642a36 dt-bindings: power: supply: bq27xxx: document optional interrupt
bac5160c66d6 arm64: dts: qcom: sm8450: enable camera clock controller by default
29d46a36d67a arm64: dts: qcom: qcm2290: Add CCI node
62438c847740 arm64: dts: qcom: lemans-evk: Add IMX577-based camera overlay
170288a13bda arm64: dts: qcom: lemans: Add CCI definitions
72641ff40bba dt-bindings: rtc: Fix Xicor X1205 vendor prefix
bd3e82898092 dt-bindings: rtc: Drop isil,isl12057.txt
70a3ef9f707d dt-bindings: rtc: s3c: Drop S3C2410
7e74fdb0d63f dt-bindings: rtc: trivial-rtc: add dallas,m41t00
cee3de2d1ca5 dt-bindings: rtc: pcf85063: remove quartz-load-femtofarads restriction for nxp,pcf85063
f37409abcbba arm64: dts: qcom: lemans: Add support for camss
4725c364527e arm64: dts: qcom: sdm845-starqltechn: add slpi support
21ded2776228 arm64: dts: qcom: sdm845-starqltechn: fix slpi reserved mem
0e631d3fe734 arm64: dts: qcom: add initial support for Samsung Galaxy S22
bb5b37eb15b0 arm64: dts: qcom: qcs8300: Flatten usb controller nodes
64f09f9705eb dt-bindings: i3c: renesas,i3c: Add RZ/V2H(P) and RZ/V2N support
0730ee22dd72 dt-bindings: i3c: Add adi-i3c-master
34d8a7fd0863 arm64: dts: qcom: x1-hp-x14: Add support for X1P42100 HP Omnibook X14
19ba7cf5e367 arm64: dts: qcom: x1-hp-x14: Unify HP Omnibook X14 device tree structure
64ac5ff20a4a dt-bindings: arm: qcom: Add HP Omnibook X14 AI X1P4200 variant
6bb73d39853e arm64: dts: qcom: ipq5018: add QUP3 I2C node
820b8d178dbb arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable IRIS
38e749a27a54 arm64: dts: qcom: x1e80100-dell-latitude-7455: Enable IRIS
52b878eb08ea arm64: dts: qcom: x1e80100-dell-inspiron-14-plus-7441: Enable IRIS
8bc8caa76767 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Enable IRIS
14f91c21a106 arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable IRIS
8243d402aafc arm64: dts: qcom: x1e80100-crd: Enable IRIS video codec
ba6a8c9c65f8 arm64: dts: qcom: x1-el2: Disable IRIS for now
2aedf3e2cc31 arm64: dts: qcom: x1e80100: Add IRIS video codec
5c5a8458baa8 arm64: dts: qcom: sm8550/sm8650: Fix typo in IRIS comment
d6b3cf61f1f2 arm64: dts: qcom: msm8916: Add SDCC resets
c973b6feebe3 arm64: dts: qcom: msm8939: Add missing MDSS reset
1834c62f7eab arm64: dts: qcom: msm8916: Add missing MDSS reset
60126fb84484 arm64: dts: qcom: sm8150: Fix reg base of frame@17c27000
8999bb650bbc arm64: dts: qcom: qcm6490: Introduce the Particle Tachyon
49363cc956a8 dt-bindings: arm: qcom: Add Particle Tachyon
6d2c15f08e83 dt-bindings: vendor-prefixes: Add Particle Industries
3186b21bb6ff dt-bindings: leds: Unify 'leds' property
65d921489b65 dt-bindings: leds: Add generic LED consumer documentation
2e6f192121c3 arm64: dts: qcom: lemans-evk: Enable 2.5G Ethernet interface
8bfbb1baf410 arm64: dts: qcom: lemans-evk: Enable SDHCI for SD Card
3c2c4d7fd711 arm64: dts: qcom: lemans-evk: Enable first USB controller in device mode
01be874a5fa5 arm64: dts: qcom: lemans-evk: Enable Iris video codec support
bbd9e7b358ed arm64: dts: qcom: lemans-evk: Enable remoteproc subsystems
f3768d0b3ef1 arm64: dts: qcom: lemans-evk: Enable PCIe support
0e0e4992356b arm64: dts: qcom: lemans-evk: Add EEPROM and nvmem layout
7dfb8a547187 arm64: dts: qcom: lemans-evk: Add TCA9534 I/O expander
cf63e02d9089 arm64: dts: qcom: lemans-evk: Enable GPI DMA and QUPv3 controllers
b85d700d5ad7 arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration
1ee1572f9811 dt-bindings: mfd: gpio: Add MAX7360
8a7581a7ca36 ASoC: dt-bindings: add bindings for pm4125 audio codec
3dd0dbd0770c regulator: max77838: add max77838 regulator driver
d430133ac6ee riscv: dts: spacemit: Add Ethernet support for Jupiter
d7cd71112e12 riscv: dts: spacemit: Add Ethernet support for BPI-F3
f0b73cdd332b riscv: dts: spacemit: Add Ethernet support for K1
75ba7751fb7d dt-bindings: net: Add support for SpacemiT K1
d4a47f98eb25 ASoC: dt-bindings: asahi-kasei,ak4458: Reference common DAI properties
c7b760837170 dt-bindings: gpio: fix trivial-gpio's schema id
cd0c0065d3f9 Merge tag 'extcon-next-for-6.18' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next
d4cf0ade79f2 dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support
67bb1935f301 Merge tag 'exynos-drm-next-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
6dcf4a22d8a3 Merge tag 'exynos-drm-misc-next-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
024d91c805e9 Merge tag 'drm-msm-next-2025-09-12' of https://gitlab.freedesktop.org/drm/msm into drm-next
64fe57f70185 Merge tag 'stm32-dt-for-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
4f7c77fe43e7 dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO
01833d389cff dt-bindings: regulator: document max77838 pmic
c4fbdb4fa1de arm64: dts: st: fix memory region size on stm32mp235f-dk
49bc752936c9 arm64: dts: st: remove gpioj and gpiok banks from stm32mp231
46f3ced834b4 arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
50b3ef11c156 arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
8deec80db582 arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
538ea05f0e42 arm64: dts: st: add eth1 pins for stm32mp2x platforms
2479ca9377a9 ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs
ffc03a35115f arm64: dts: st: enable display support on stm32mp257f-ev1 board
8739d5cd40d1 arm64: dts: st: add clock-cells to syscfg node on stm32mp251
7af98a27ac9e arm64: dts: st: add lvds support on stm32mp255
4f154570d24d arm64: dts: st: add ltdc support on stm32mp255
7fc0ac767225 arm64: dts: st: add ltdc support on stm32mp251
8cfdd52cbf1e ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153
8bb83e9000a8 dt-binding: can: m_can: add optional resets property
82acd1437fab arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board
48aafc132f3c arm64: dts: st: Add PCIe Endpoint mode on stm32mp251
0594689d8740 arm64: dts: st: Add PCIe Root Complex mode on stm32mp251
e9800094c4dc arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi
3acf623b2f97 ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board
b171b02eaf44 ARM: dts: stm32: add alternate pinmux for HDP pin and add HDP pinctrl node
b0d2709e1d32 arm64: dts: st: add Hardware debug port (HDP) on stm32mp25
0b77815b24e4 ARM: dts: socionext: Drop "linux,spdif-dit" port node unit-address
7b358323bef7 Merge tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
b5d706e92320 Merge tag 'imx-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
47d715be6dd3 Merge tag 'imx-bindings-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
363767957d7f Merge tag 'scmi-updates-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
417b02344e08 dt-bindings: memory-controllers: Add support for Versal NET EDAC
d23928f9488f Merge tag 'samsung-drivers-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
de34463d8c66 Merge tag 'qcom-drivers-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
820831e4cad4 Merge tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
658dcf1297df Merge tag 'reset-for-v6.18' of https://git.pengutronix.de/git/pza/linux into soc/drivers
e17545c43a3a Merge tag 'aspeed-6.18-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
1ad035d0bb1b Merge tag 'tegra-for-6.18-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
52db19620bca Merge tag 'tegra-for-6.18-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
7b5140dbf419 Merge tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
93a48fb7a299 Merge tag 'sti-dt-for-v6.18-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
960bf4c90d02 Merge tag 'mvebu-dt64-6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
e129a801aae3 Merge tag 'zynqmp-dt-for-6.18' of https://github.com/Xilinx/linux-xlnx into soc/dt
d578e531c8f8 Merge tag 'renesas-dts-for-v6.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
34009cfba36c Merge tag 'renesas-dt-bindings-for-v6.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
770ba90c13a0 Merge tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
bbec1e6edc33 Merge tag 'qcom-arm32-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
61f1c90d4156 Merge tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
4caab0ab3979 arm64: dts: socionext: Drop "linux,spdif-dit" port node unit-address
2c1bf2c5dab0 arm64: dts: apm: Clean-up clock bindings
fe57047513ea arm64: dts: apm: Move slimpro nodes out of "simple-bus" node
03dac135cae4 Merge tag 'arm-soc/for-6.18/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
9a4b35863464 Merge tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
6559d282c5db Merge tag 'v6.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
2335ab94faa2 Merge tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
4ffa82083fbc Merge tag 'dt64-cleanup-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
b2b1215822d8 Merge tag 'i2c-gpio-fixes-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux into soc/dt
940ac46a9933 Merge tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
3a0cbe230031 Merge tag 'socfpga_dts_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
8dc20f916c40 Merge tag 'v6.18-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
2dd775b2baac Merge tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
4cee86d18eb0 Merge tag 'thead-dt-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
ddb62120f526 Input: add INPUT_PROP_HAPTIC_TOUCHPAD
94af7068da7d dt-bindings: display: samsung,exynos7-decon: document iommus, memory-region, and ports
73099393ff04 dt-bindings: samsung,mipi-dsim: document exynos7870 DSIM compatible
d4bd6c498590 Merge back earlier cpufreq material for 6.18
35807d12cd3a dt-bindings: pwm: samsung: add exynos8890 compatible
3e1e90e612f1 dt-bindings: pwm: apple,s5l-fpwm: Add t6020-fpwm compatible
a0ede17e360a dt-bindings: pwm: nxp,lpc1850-sct-pwm: Minor whitespace cleanup in example
b34619eeccb1 dt-bindings: pwm: fsl,vf610-ftm-pwm: Add compatible for s32g2 and s32g3
2f2514374b7f dt-bindings: timer: renesas,rz-mtu3: Use #pwm-cells = <3>
20ea2c09ea4d Merge tag 'v6.17-rc6' into drm-next
3cb295e1bacf Merge 6.17-rc6 into tty-next
53c11beaf74d Merge 6.17-rc6 into usb-next
ab3b300dfbcb dt-bindings: net: ti: Adds DUAL-EMAC mode support on PRU-ICSS2 for AM57xx, AM43xx and AM33xx SOCs
82776837dd02 spi: dt-bindings: apple,spi: Add t6020-spi compatible
8448d2062e75 ASoC: dt-bindings: apple,mca: Add t6020-mca compatible
d13aae8b92d0 dt-bindings: dma: apple,admac: Add t6020-admac compatible
aeaffa84d866 dt-bindings: clock: apple,nco: Add t6020-nco compatible
9260975ebfa8 dt-bindings: watchdog: apple,wdt: Add t6020-wdt compatible
6378475ae585 dt-bindings: spmi: apple,spmi: Add t6020-spmi compatible
3e54e9b89c08 dt-bindings: mfd: apple,smc: Add t6020-smc compatible
b96dfe28085a dt-bindings: net: bcm4329-fmac: Add BCM4388 PCI compatible
b27029bd80ae dt-bindings: net: bcm4377-bluetooth: Add BCM4388 compatible
c3118a735f20 dt-bindings: nvme: apple: Add apple,t6020-nvme-ans2 compatible
80c6c869125e dt-bindings: iommu: apple,sart: Add apple,t6020-sart compatible
a09a4b8bec17 dt-bindings: gpu: apple,agx: Add agx-{g14s,g14c,g14d} compatibles
6700addfbd3f dt-bindings: mailbox: apple,mailbox: Add t6020 compatible
56eacf61000b dt-bindings: pinctrl: apple,pinctrl: Add apple,t6020-pinctrl compatible
345e27f38eba dt-bindings: iommu: dart: Add apple,t6020-dart compatible
f7e3f246621a dt-bindings: interrupt-controller: apple,aic2: Add apple,t6020-aic compatible
fa940d6e3a2e dt-bindings: cpufreq: apple,cluster-cpufreq: Add t6020 compatible
7dbcd1504d40 dt-bindings: power: apple,pmgr-pwrstate: Add t6020 compatible
ab01dcc27631 dt-bindings: arm: apple: apple,pmgr: Add t6020-pmgr compatible
f89aa207aef6 dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/T2H and RZ/N2H SoCs
2010bb166fe1 arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions
f16b52866ce6 arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal
4e4cb7f44118 arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal
350c2cd012b2 arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal
ccc4585680fa arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks
8342879868ad arm64: dts: s32g: Add device tree information for the OCOTP driver
748b137cdcc4 arm64: dts: add description for solidrun imx8mp hummingboard variants
2648bdb78e1f Merge tag 'v6.17-rc3' into togreg
9b3755b9d262 dt-bindings: mfd: 88pm886: Add #io-channel-cells
2e68d473d59e dt-bindings: iio: adc: add ade9000
af43705991f6 ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier
a1a8c92016dd ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier
6e1679f0972c ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
9b87741fed0f riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
8a940283db0d dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings
b3bbbb977eba ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay
7aa77e217571 ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing
56c2aa9eaafa ARM: dts: allwinner: orangepi-zero: Add default audio routing
5e0e16811424 arm64: dts: allwinner: a523: Add NPU device node
1630da668944 arm64: dts: allwinner: a523: Add MCU PRCM CCU node
c79378367497 Merge branch 'sunxi/shared-dt-headers-for-6.18' into sunxi/dt-for-6.18
521b131765fd dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
9c1199e7867d dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
3ae0c13a0bda dt-bindings: net: Drop duplicate brcm,bcm7445-switch-v4.0.txt
413e8c7300b9 dt-bindings: i2c: nvidia,tegra20-i2c: Add Tegra256 I2C compatible
985422252c46 dt-bindings: i2c: apple,i2c: Add apple,t6020-i2c compatible
ea5da1e5c453 dt-bindings: i2c: exynos5: Add exynos990-hsi2c compatible
a3ac113d03ed dt-bindings: i2c: qcom-cci: Document sa8775p compatible
bca16f47f496 dt-bindings: i2c: qcom-cci: Document QCM2290 compatible
fa00d288a877 dt-bindings: watchdog: renesas,wdt: Add support for RZ/T2H and RZ/N2H
d1cf41522414 ARM: dts: sti: remove dangling stih407-clock file
7b0aeebf06ff arm64: dts: mediatek: mt8516-pumpkin: Fix machine compatible
3a9aa38514b3 arm64: dts: mediatek: mt8395-kontron-i1200: Fix MT6360 regulator nodes
cb32abe6b89f arm64: dts: mediatek: mt8195-cherry: Add missing regulators to rt5682
d9e754a3403e arm64: dts: mediatek: mt8195-cherry: Move VBAT-supply to Tomato R1/R2
ad691969cb56 arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes
fb05a5bdcc3d arm64: dts: mediatek: mt8183-kukui: Move DSI panel node to machine dtsis
702a63b1ec68 arm64: dts: mediatek: mt8183: Migrate to display controller OF graph
85390b9b6784 arm64: dts: mediatek: mt8183-pumpkin: Add power supply for CCI
2307de363804 arm64: dts: mediatek: pumpkin-common: Fix pinctrl node names
052a4b708c9a arm64: dts: mediatek: mt8183: Fix pinctrl node names
18d218bf170d arm64: dts: mediatek: acelink-ew-7886cax: Remove unnecessary cells in spi-nand
591fbfe11078 arm64: dts: mediatek: mt7986a-bpi-r3: Set interrupt-parent to mdio switch
8d9aba110653 arm64: dts: mediatek: mt7986a-bpi-r3: Fix SFP I2C node names
a2dabd4a46f7 arm64: dts: mediatek: mt7986a: Fix PCI-Express T-PHY node address
b9c04bef0394 arm64: dts: mediatek: Fix node name for SYSIRQ controller on all SoCs
a68e3606acd4 arm64: dts: mediatek: mt6795-sony-xperia-m5: Add pinctrl for mmc1/mmc2
726b3ca249b5 dt-bindings: serial: 8250_omap: Add wakeup pinctrl state
528feeb9cac4 arm64: dts: mediatek: mt6795-xperia-m5: Fix mmc0 latch-ck value
162402e337b2 arm64: dts: mediatek: mt6795: Add mediatek,infracfg to iommu node
36f440ccfe4f arm64: dts: mediatek: mt6797: Remove bogus id property in i2c nodes
eebbb29ec01c dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE
b7b3ff468d4a dt-bindings: nvmem: sl28cpld: add sa67mcu compatible
c55741361c3e dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file
5503d89b5430 dt-bindings: misc: qcom,fastrpc: Add GDSP label
f15cb903ad4c slimbus: qcom: remove unused qcom controller driver
be0eb85e2a27 arm64: dts: marvell: cn9130-sr-som: add missing properties to emmc
d6a9423a9f2f arm64: dts: marvell: add dts for RIPE Atlas Probe v5
5510d8ef1a2f dt-bindings: marvell: armada-37xx: add ripe,atlas-v5 compatible
74a87dda7954 dt-bindings: mmc: controller: Add max-sd-hs-hz property
dc506727a32f dt-bindings: mmc: sdhci-msm: Document the Lemans compatible
d9608f794cf2 arm64: dts: mediatek: mt6797: Fix pinctrl node names
6eaae00b82ce arm64: dts: mediatek: mt6331: Fix pmic, regulators, rtc, keys node names
1a22d64e5d57 dt-bindings: mmc: sdhci-pxa: Add minItems to pinctrl-names
c3fb417e1470 Merge tag 'samsung-pinctrl-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
280cc9c435af Merge branch 'icc-glymur' into icc-next
a58fca9152e8 dt-bindings: interconnect: Add OSM L3 compatible for QCS615 SoC
e680d4bd4e66 arm64: dts: renesas: sparrow-hawk-fan-pwm: Rework hwmon comment
1e445716add9 arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J2
82c0db4c8ce7 arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J1
1e50bcdc8674 arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J2
14356477416c arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J1
ff03663d01df arm64: dts: renesas: rcar: Rename dsi-encoder to dsi
a468493ea84f arm64: dts: renesas: r9a09g056: Add I3C node
22ce0e07cb30 arm64: dts: renesas: r9a09g057: Add I3C node
5bbe091c8e69 arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support
557a96035327 arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI function
4abfa5fd2724 arm64: dts: renesas: r9a09g047e57-smarc: Fix gpio key's pin control node
93116ac48fe4 arm64: dts: renesas: r9a09g047: Enable Tx coe support
f0095acb3f8f arm64: dts: renesas: r9a09g087: Add USB2.0 support
9acc03e45aa6 arm64: dts: renesas: r9a09g077: Add USB2.0 support
6bdb8325214e arm64: dts: renesas: rzt2h-n2h-evk-common: Enable WDT2
00f3a560c689 arm64: dts: renesas: r9a09g087: Add WDT nodes
a6fd929b8117 arm64: dts: renesas: r9a09g077: Add WDT nodes
293b8224d3a9 arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot
6fbed4ada1ff arm64: dts: renesas: rzt2h-rzn2h-evk: Enable MicroSD card slot
89cf9b661d9c arm64: dts: renesas: rzt2h-rzn2h-evk: Enable eMMC
d3421e9d10cf arm64: dts: ti: k3-j721s2-evm: Add overlay to enable USB0 Type-A
0cf9389cfc86 arm64: dts: ti: k3-am642-phyboard-electra: Add PEB-C-010 Overlay
67157ee29fcc arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board
f806d7a939e0 arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
82e95a45cfc0 dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
b393b5f72334 arm64: dts: ti: k3-j722s-evm: Add bootph-all tag to usb0_phy_ctrl node
ec1afb0ccba9 arm64: dts: ti: k3-am62x-sk-common: Add bootph-all tag to usb0_phy_ctrl node
3c4fbec174ea arm64: dts: ti: k3-am62p5-sk: Add bootph-all tag to usb0_phy_ctrl node
e2364a2ef60b arm64: dts: ti: k3-am62a7-sk: Add bootph-all tag to usb0_phy_ctrl node
f3a18fbb6399 arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX
c3631a40b264 arm64: dts: ti: k3-pinctrl: Fix the bug in existing macros
848e33676408 arm64: dts: ti: k3-pinctrl: Add the remaining macros
5a79728fa58b arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS
3d5d78c25cdf arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS
353d23c59f84 Merge tag 'renesas-r9a09g047-dt-binding-defs-tag4' into renesas-clk-for-v6.18
ce33a4790fba arm64: dts: rockchip: Add USB and charger to Gameforce Ace
2f17b68e99fc arm64: dts: mediatek: mt8188-geralt: Enable first SCP core
8b32ab27c51d arm64: dts: mediatek: mt8186-tentacruel: Fix touchscreen model
3414492bed49 arm64: dts: mediatek: mt8188: Change efuse fallback compatible to mt8186
d34a43ff0ab1 arm64: dts: ti: k3-am62d2-evm: Add support for OSPI flash
0fa63ab7506d arm64: dts: ti: k3-am62d2-evm: Enable USB support
4e7f76ee5935 arm64: dts: ti: k3-am62a-main: Fix main padcfg length
4d9b7010d8e0 arm64: dts: ti: k3-am62p: Update eMMC HS400 STRB value
3222b21ca60e arm64: dts: ti: k3-am62p/j722s: Remove HS400 support from common
58cd89aff167 arm64: dts: ti: Add support for AM6254atl SiP SK
fa5a6a6e784b arm64: dts: ti: Introduce base support for AM6254atl SiP
5a159a90d515 dt-bindings: arm: ti: Add binding for AM625 SiP
0b0edbbdf43b arm64: dts: ti: k3-am62*: remove SoC dtsi from common dtsi
004add17afb6 arm64: dts: marvell: armada-cp11x: Add default ICU address cells
0c1df7129173 arm64: dts: marvell: armada-37xx: Add default PCI interrup controller address cells
077927a013d0 arm64: dts: ti: k3-am65-ti-ipc-firmware: Refactor IPC cfg into new dtsi
f71b42edfbfd arm64: dts: ti: k3-am64-ti-ipc-firmware: Refactor IPC cfg into new dtsi
93d8f1dac198 arm64: dts: ti: k3-am62a-ti-ipc-firmware: Refactor IPC cfg into new dtsi
09d1212046b3 arm64: dts: ti: k3-am62-ti-ipc-firmware: Refactor IPC cfg into new dtsi
977c818b13e6 arm64: dts: ti: k3-am62p-ti-ipc-firmware: Refactor IPC cfg into new dtsi
9df649b5b448 arm64: dts: ti: k3-j722s-ti-ipc-firmware: Refactor IPC cfg into new dtsi
d991cd694107 arm64: dts: ti: k3-j784s4-ti-ipc-firmware: Refactor IPC cfg into new dtsi
d52c60d3548e arm64: dts: ti: k3-j784s4-j742s2-ti-ipc-firmware-common: Refactor IPC cfg into new dtsi
7ea18e242453 arm64: dts: ti: k3-j721s2-ti-ipc-firmware: Refactor IPC cfg into new dtsi
5551ce22ff64 arm64: dts: ti: k3-j721e-ti-ipc-firmware: Refactor IPC cfg into new dtsi
e3a4254470ea arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi
187e12af2b80 arm64: dts: ti: k3-j721e-beagleboneai64: Switch MAIN R5F clusters to Split-mode
7693a9c9d486 Revert "arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations"
3410b7d820f6 Revert "arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations"
4f40c9876c78 arm64: dts: ti: k3-am642-tqma64xxl: Add missing cfg for TI IPC Firmware
73beabcf51c6 arm64: dts: ti: k3-am64-phycore-som: Add missing cfg for TI IPC Firmware
7ef5b87323e7 arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware
67c4900e1035 arm64: dts: ti: k3-am62-pocketbeagle2: Add missing cfg for TI IPC Firmware
d3a0da88813b arm64: dts: ti: k3-am62-verdin: Add missing cfg for TI IPC Firmware
8dc88bcc9304 arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware
dd1e15e217cc arm64: dts: ti: k3-j721e-beagleboneai64: Add missing cfg for TI IPC FW
94110212e329 arm64: dts: ti: k3: Rename rproc reserved-mem nodes to 'memory@addr'
58c447fe500d arm64: dts: ti: k3-am6*-boards: Add label to reserved-memory node
70247fdd3086 arm64: dts: ti: k3-am62a: Enable Mailbox nodes at the board level
36d1226fac02 arm64: dts: ti: k3-am62: Enable Mailbox nodes at the board level
30f07a7a8320 arm64: dts: ti: k3-am65: Enable remote processors at board level
27677acb3cbf arm64: dts: ti: k3-am64: Enable remote processors at board level
fe2a325fff3a arm64: dts: ti: k3-am62a: Enable remote processors at board level
862972700cd8 arm64: dts: ti: k3-am62: Enable remote processors at board level
c5f48d263563 arm64: dts: ti: k3-am62p-j722s: Enable remote processors at board level
bb05503f668d arm64: dts: ti: k3-j784s4-j742s2: Enable remote processors at board level
cffb26482525 arm64: dts: ti: k3-j721s2: Enable remote processors at board level
30f2bd07b1fc arm64: dts: ti: k3-j721e: Enable remote processors at board level
6342c740d1e8 arm64: dts: ti: k3-j7200: Enable R5F remote processors at board level
7660f5062183 arm64: dts: ti: k3-j742s2-mcu-wakeup: Override firmware-name for MCU R5F cores
375d372313cd dt-bindings: net: Convert APM XGene MDIO to DT schema
bcbd79dc0ca1 dt-bindings: net: Convert apm,xgene-enet to DT schema
e56d3d6eb23f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e4cc61996e49 support for Amlogic SPI Flash Controller IP
ef601c28b56a dt-bindings: soc: renesas: Document R-Car X5H Ironhide
3c028140ae37 dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
9cddf19cc52d arm64: tegra: Add I2C nodes for Tegra264
931de165e2d9 ARM: tegra: add support for ASUS Eee Pad Slider SL101
0d8e66748a07 ARM: tegra: transformer-20: fix audio-codec interrupt
d4702ad0cc4a ARM: tegra: transformer-20: add missing magnetometer interrupt
35d6cd280f97 ARM: tegra: Add DFLL clock support for Tegra114
3b97c7fd9153 ARM: tegra: p880: set correct touchscreen clipping
c9a87d64df9b dt-bindings: arm: tegra: Add ASUS TF101G and SL101
825721de475d dt-bindings: reset: Add Tegra114 CAR header
03766ee54f89 dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
b6dbd6555ea2 dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
8d2c1734b3bd dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
c2f447eab9e4 dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C
5bd0ff6735a3 dt-bindings: mfd: ti,bq25703a: Add TI BQ25703A Charger
a28d661ae8d9 dt-bindings: eeprom: at24: Add compatible for Giantec GT24C256C
6877bdeb0a04 ASoC: dt-bindings: linux,spdif: Add "port" node
4fdbb4df644a ASoC: dt-bindings: ti,pcm1754: add binding documentation
d8f5106d38cc Merge tag 'w1-drv-6.18' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1 into char-misc-next
8804d7810282 arm64: dts: rockchip: enable the Mali GPU on RK3328 boards
a9e5f123c30e arm64: dts: rockchip: add GPU powerdomain, opps, and cooling to rk3328
df0a6883e93c arm64: dts: rockchip: Fix network on rk3576 evb1 board
c924d2e258cb arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588
252b1bce81cf dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon
47b8f27bd9e6 dt-bindings: arm: fsl: add TQMa91xx SOM series
e3bbf5a8fbb7 dt-bindings: fsl: fsl,imx7ulp-smc1: Allow clocks and clock-names
2def6e73363b dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards
64a1c70301b4 arm64: dts: imx8mm-phycore-som: optimize drive strengh
b16bebd800b6 arm64: dts: freescale: imx93-phycore-som: Remove "fsl,magic-packet"
e8154fe0ec23 ARM: dts: imx6sll: Use 'dma-names'
04777a6a156b arm64: dts: freescale: imx93-phyboard-nash: Current sense via iio-hwmon
1aa3dab7253b arm64: dts: imx95: add standard PCI device compatible string to NETC Timer
199b3a657f03 ARM: dts: imx6: change rtc compatible string to st,m41t00 from m41t00
2c4e3d395e72 ARM: dts: imx6: remove undefined linux,default-trigger source
d852c4448c32 ARM: dts: imx6ul-pico: add power-supply for vxt,vl050-8048nt-c01
c6ea89ad917c ARM: dts: imx6ul-14x14-evk: add regulator for ov5640
92f1bb311e6f ARM: dts: imx6: replace isl,isl12022 with isil,isl12022 for RTC
fe859c807331 ARM: dts: imx6: replace gpio-key with gpio-keys compatible string
3622701fcde3 ARM: dts: imx6: rename i2c<n>mux i2c-mux-<n>
ba85aed4625b ARM: dts: imx6: rename node name flash to eeprom
75735395d6e6 ARM: dts: imx6: rename node i2c-gpio to i2c.
9cbe65b007ec ARM: dts: imx6: rename touch screen's node name to touchscreen
7e7a58885d5a ARM: dts: imx6: remove redundant pinctrl-names
8814115e9197 ARM: dts: imx6qdl-aristainetos2: rename ethernet-phy to ethernet-phy@0
d5fcf175ff96 ARM: dts: imx6: add interrupt-cells for dlg,da9063 pmic
548da38bbd54 ARM: dts: imx6: align rtc chip node name to 'rtc'
d542f142b216 ARM: dts: imx6: add key- prefix for gpio-keys
5876701b2d73 ARM: dts: imx6: add #address-cells for gsc@20
74a4ffa0fa33 arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA
2253588537ee arm64: dts: imx93-11x11-evk: remove fec property eee-broken-1000t
6db82b1dff8a arm64: dts: freescale: add i.MX91 11x11 EVK basic support
640a0eafc57c arm64: dts: imx91: add i.MX91 dtsi support
3bc450b7f3d8 arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them
0c66bb7041fe arm64: dts: freescale: move aliases from imx93.dtsi to board dts
98996811d946 arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for x4 and x8 slots
1a6361222b38 arm64: dts: lx2160a-cex7: add interrupts for rtc and ethernet phy
1ece2c19e17b arm64: dts: add description for solidrun imx8mp som and cubox-m
9a3bc0362742 arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability
97c94df5fcc8 arm64: dts: imx8qxp: Add default GIC address cells
2c9a6b05c418 arm64: dts: imx8qm: Add default GIC address cells
4f47a74e93c2 arm64: dts: imx8mq: Add default GIC address cells
f26b067f19b7 arm64: dts: imx8mp: Add default GIC address cells
3552efdc4f11 arm64: dts: imx8mm: Add default GIC address cells
19602862655c arm64: dts: imx8dxl: Add default GIC address cells
5833034e8dea arm64: dts: fsl-ls1046a: Add default GIC address cells
5178412d3f65 arm64: dts: fsl-ls1043a: Add default GIC address cells
fca33139d9bd arm64: dts: fsl-ls1012a: Add default GIC address cells
6c299b17582d arm64: dts: freescale: imx8mp-moduline-display-106: Use phys to replace xceiver-supply
e8a1951f0b87 arm64: dts: imx8mp: Add TechNexion EDM-G-IMX8M-PLUS SOM on WB-EDM-G carrier board
c0eb9566fb32 arm64: dts: imx8mp: add interconnect for lcdif-hdmi
c7971715925c arm64: dts: imx95: Add msi-map for pci-ep device
8faa5fc2c559 arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP
a7496a176cbc ARM: dts: imx6ul-tx6ul: Switch away from deprecated `phy-reset-gpios`
eaf55a1ba158 ARM: dts: mba6ul: Add MicIn routing
40443826dee2 dt-bindings: soc: fsl,imx-iomuxc-gpr: Document i.MX53
c192b31e4b99 dt-bindings: arm: fsl: Add EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board
0249284f99db ARM: dts: ls1021a-tsn: Remove redundant #address-cells for ethernet-switch@1
608d22b4328c ARM: dts: ls1021a: Rename esdhc@1560000 to mmc@1560000
0dc276f44812 ARM: dts: ls1021a: Rename 'mdio-mux-emi1' to 'mdio-mux@54'
ab28361c05d6 ARM: dts: ls1021a: Rename node name nor to flash
e70f98cfd6b5 ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
8c00801d1892 ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
b0f9eb12d42f ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
c38cd7394fae ARM: dts: lpc32xx: Correct SD/MMC controller device node name
5734cd67f49b ARM: dts: lpc32xx: Correct motor PWM device tree node name
77cbea52271c ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
32f3e9d18c34 dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
3d5da24575db ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
78eec0daf020 ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
faf27ebe2f22 ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
2ddee998018f ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
482f03ba8a36 ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
6da3fb0358a3 ARM: dts: lpc: add cfg surfix in pinctrl child node
d5f161691b0b ARM: dts: lpc: add #address-cells and #size-cells for sram node
cf14fa60f4bc ARM: dts: lpc18xx: swap clock-names bic and cui
dff3188d333d ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
ed76dda824ba ARM: dts: lpc18xx: rename node name mmcsd to mmc
bf9277a23550 ARM: dts: lpc18xx: rename node name flash-controller to spi
3528b3cb5b4d dt-bindings: iio: afe: current-sense-amplifier: Add io-channel-cells
1e761273a212 dt-bindings: iio: magnetometer: Infineon TLV493D 3D Magnetic sensor
e5c22e52347a dt-bindings: iio: adc: samsung,exynos: Drop touchscreen support
f6ec9123dbcb dt-bindings: iio: adc: samsung,exynos: Drop S3C2410
2898470124be dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant
3d436d58369f dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required
5bfd4cd54215 arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting
c026d759b53e arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting
47ede27b2341 dt-bindings: phy: Add Sophgo CV1800 USB phy
79994b1f4fb5 arm64: versal-net: Describe L1/L2/L3/LLC caches
058384f7f135 arm64: zynqmp: Enable DP in kr260/kv260 revA
2e942dafc767 arm64: zynqmp: Describe ethernet controllers via aliases on SOM
1802476aa00c arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106
8d4285ab76c1 arm64: zynqmp: Disable coresight by default
7262c0ae62e1 dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
8b4d81e22765 spi: dt-bindings: add Amlogic A113L2 SFC
143c696884e0 dt-bindings: arm: mediatek: Add grinn,genio-510-sbc
76c27df6df70 dt-bindings: arm: mediatek: Add grinn,genio-700-sbc
16af1d5eca56 dt-bindings: memory: tegra210: Add memory client IDs
39c4086b7e5d dt-bindings: memory: tegra210: emc: Document OPP table and interconnect
6286189119bd dt-bindings: mtd: loongson,ls1b-nand-controller: Document the Loongson-2K1000 NAND controller
4210d380da47 dt-bindings: mtd: loongson,ls1b-nand-controller: Document the Loongson-2K0500 NAND controller
d95093867185 dt-bindings: firmware: imx95-scmi: Allow linux,code for protocol@81
14961c557822 ARM: dts: imx6-aristainetos2: Replace license text comment with SPDX identifier
d0a239b42726 arm64: dts: amlogic: gxbb-odroidc2: remove UHS capability for SD card
de195fa87d9a dts: arm: amlogic: fix pwm node for c3
561e022aa70e ARM: dts: aspeed: Drop syscon "reg-io-width" properties
57bc09a2a030 dt-bindings: dp-connector: describe separate DP and AUX lines
e40bda0d5414 docs: dt: writing-schema: Describe defining properties in top-level
504199c26adc arm64: dts: broadcom: Enable USB devicetree entries for Rpi5
488ee067ce8d arm64: dts: broadcom: rp1: Add USB nodes
d7dcc7774b6f riscv: dts: microchip: add a device tree for Discovery Kit
bbd7492f8fa2 dt-bindings: riscv: microchip: document Discovery Kit
0a7068797a5e riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes
dfb3e0f8d631 riscv: dts: microchip: add icicle kit with production device
2a427fa04ab2 dt-bindings: riscv: microchip: document icicle kit with production device
10eec30ba151 riscv: dts: microchip: add common board dtsi for icicle kit variants
0c4b53d264ea arm64: dts: qcom: x1e80100: Update GPU OPP table
10e5e9fe41ad arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
d3256648a8d5 arm64: dts: qcom: add initial support for Samsung Galaxy S20
2cfdd491b570 dt-bindings: arm: qcom: document x1q board binding
8c01a1613314 arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
d0e0f6a646f1 arm64: dts: qcom: lemans-evk: Add sound card
5d6691831311 arm64: dts: qcom: lemans: Add gpr node
51e1dbfe0495 arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
c15c2003f6be arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
eb802d4c4af7 arm64: dts: qcom: sm6150: add venus node to devicetree
fb5cba5fd65f arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
d37938bb7edd dt-bindings: input: qcom,pm8941-pwrkey: Fix formatting of descriptions
6fc39c857556 arm64: dts: qcom: qrb2210-rb1: Enable Venus
b770200ddf5a arm64: dts: qcom: qcm2290: Add Venus video node
3cf3d78e35d6 media: dt-bindings: Add qcom,qcs8300-camss compatible
8992c20adf8d media: dt-bindings: Add qcom,sa8775p-camss compatible
a38bc59a1537 dt-bindings: media: Add qcom,qcm2290-camss
661c142ca35c dt-bindings: media: qcom,sm8550-iris: Do not reference legacy venus properties
d149fe9e044b dt-bindings: media: qcom,sm8550-iris: Add SM8750 video codec
dcb96459599c dt-bindings: media: qcom,sm8550-iris: Add X1E80100 compatible
739e98fea794 dt-bindings: media: qcom,sm8550-iris: Update Dikshita Agarwal's email address
1f2536cfa637 dt-bindings: media: imx274: Make clocks property required
86d67248ac74 dt-bindings: media: imx258: Make clocks property required
ebaf5629146b dt-bindings: media: et8ek8: Deprecate clock-frequency property
5e11a49df7b6 dt-bindings: media: Deprecate clock-frequency property for camera sensors
193b02e99436 dt-bindings: media: i2c: Add ov2735 sensor
bfdde628cc51 dt-bindings: media: i2c: Add OmniVision OG0VE1B camera sensor
73769a23d25e dt-bindings: media: i2c: Add OmniVision OV6211 image sensor
5f3a1973f971 media: dt-bindings: venus: Add qcm2290 dt schema
9f581b78d86b media: include: update Hans Verkuil's email address
9c6ee6af3669 Documentation: update Hans Verkuil's email address
9344da55c29b Documentation: media: update Hans Verkuil's email address
c4636fddf0d8 arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
8c53f0e6e25f arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
7edc5b11e60b arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet
a473a143fe91 arm64: dts: mediatek: mt7988: add switch node
6a2b71a1b1f8 arm64: dts: mediatek: mt7988: add basic ethernet-nodes
be834e2a3aaa arm64: dts: mediatek: mt7986: add interrupts for RSS and interrupt names
a57905a64745 arm64: dts: mediatek: mt7986: add sram node
1bc1923c17d0 arm64: dts: mediatek: add thermal sensor support on mt7981
4b5e20540bdc arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support
03689fe0c81a arm64: dts: mediatek: mt8395-nio-12l: Enable UFS
f6c19075829c arm64: dts: mediatek: mt8183: Fix out of range pull values
6ae0c1e25301 arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0
cd9328c55299 dt-bindings: trivial-devices: Add sht2x sensors
24c3e2399144 dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles
894ba50ce451 dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
b890b3ca96f1 ASoC: tas2781: Add tas2118, tas2x20, tas5825 support
8266bce0403c dt-bindings: arm: cpus: Document pu-supply
666bcc401c1f dt-bindings: display: bridge: simple: document the Realtek RTD2171 DP-to-HDMI bridge
9c18e97b9be4 riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms
cd5d4277d951 riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1
1d088f5be6e4 regulator: dt-bindings: rpi-panel: Split 7" Raspberry Pi 720x1280 v2 binding
33b7b6179c4b spi: dt-bindings: samsung: Drop S3C2443
812501b343ba dt-bindings: ipmi: aspeed,ast2400-kcs-bmc: Add missing "clocks" property
65f6bd5415d5 arm64: dts: qcom: monaco-evk: Add sound card
87b86b72dc5a arm64: dts: qcom: qcs8300: Add gpr node
e72347d5471c arm64: dts: qcom: qcs8300: Add Monaco EVK board
40f007dff19c dt-bindings: arm: qcom: Add Monaco EVK support
21385ee624da arm64: dts: qcom: qcm6490-idp: Add sound card
064926f4b3ae arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
a70b8dfe40bf arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
c751e6d21712 arm64: dts: qcom: qcs6490-rb3gen2: Add WSA8830 speakers amplifier
aaf1f547c2e6 arm64: dts: qcom: qcs6490-audioreach: Enable LPASS macros clock settings for audioreach
8c097fc1c4db arm64: dts: qcom: sc7280: Add WSA SoundWire and LPASS support
470c89c79dae arm64: dts: qcom: qcs6490-audioreach: Add AudioReach support for QCS6490
5d9462e974d7 dt-bindings: display/msm/gpu: describe A505 clocks
a451754c5a06 dt-bindings: pinctrl: qcom: Add Glymur pinctrl
e1eb1695052e dt-bindings: pinctrl: Add support for Broadcom STB pin controller
c9dda4c4de6c arm64: dts: cix: add DT nodes for all I2C and I3C ports for sky1
f432da4981ea dt-bindings: gpio: loongson: Document GPIO controller of LS2K0300 SoC
2b67e10f564b ARM: dts: samsung: smdk5250: add sromc node
448ed501d871 ARM: dts: samsung: exynos5250: describe sromc bank memory map
56be5c69c87e ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges
6220769fcca0 Merge tag 'v6.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
bbc8e1a89f02 dt-bindings: extcon: linux,extcon-usb-gpio: GPIO must be provided
21d520c258cc dt-bindings: extcon: rt8973a: Convert DT bindings to YAML
5975d59c8195 dt-bindings: extcon: Document Maxim MAX14526 MUIC
e8ddaf26864e dt-bindings: hwmon: Add MPS mp2869,mp29608,mp29612,mp29816 and mp29502
0210ef70053f dt-bindings: hwmon: ti,ina2xx: Add INA700
32b21805ee7c dt-bindings: hwmon: pwm-fan: Document after shutdown fan settings
0e54fd844bea dt-bindings: hwmon: ti,ina2xx: Update details for various chips
f950d4302245 dt-bindings: hwmon: ti,ina2xx: Add INA780 device
f1e9e71650ba dt-bindings: hwmon: tmp102: Add label property
3d6e6142b6c6 dt-bindings: hwmon: (pmbus/isl68137) add RAA228244 and RAA228246 support
92cbf8881862 dt-bindings: hwmon: convert lantiq-cputemp to yaml
34e4092042f5 dt-bindings: hwmon: adm1275: add sq24905c support
bdeeaf5d656b dt-bindings: hwmon: (lm75) Add binding for NXP P3T1750
48e47e742b87 arm64: dts: rockchip: Add rk3528 CPU frequency scaling support
9f59dae4799e arm64: dts: rockchip: enable HDMI Receiver on NanoPC T6
7f61aaf9b33d arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers
c76810e42f4a dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
90ae0ffb1f51 bindings: siox: convert eckelmann,siox-gpio.txt to yaml format
20640c182414 dt-bindings: display: bridge: Reference DAI common schema
f93ccfbb0f83 dt-bindings: input: touchscreen: goodix: Drop 'interrupts' requirement
a96d50c09adb dt-bindings: display/msm/gmu: Update Adreno 623 bindings
488cb8dbabf9 dt-bindings: input: convert max11801-ts to yaml format
7dcf9eb82ff9 dt-bindings: input: convert semtech,sx8654 to yaml format
1b5f61d963cd dt-bindings: input: exc3000: move eeti,egalax_ts from egalax-ts.txt to eeti,exc3000.yaml
56388b45fc06 dt-bindings: eeprom: at25: use "size" for FRAMs without device ID
516241d80cfe dt-bindings: usb: usb251xb: support usage case without I2C control
197df2ad62c8 dt-bindings: usb: s3c2410-usb: Drop entirely S3C2410
56984bc19e1b usb: dt-bindings: ti,twl6030-usb: convert to DT schema
d034c629a0b8 usb: dt-bindings: ti,twl4030-usb: convert to DT schema
362deeddb48e dt-bindings: usb: IXP4xx UDC bindings
d4a4225f2b5a arm64: dts: apple: t8015: Add NVMe nodes
117cbe35f021 arm64: dts: apple: t8015: Fix PCIE power domains dependencies
0f48d32058b6 dt-bindings: nvme: apple,nvme-ans: Add Apple A11
1faa77d110ef dt-bindings: iommu: apple,sart: Add Apple A11
2c4bb7338888 dt-bindings: crypto: Add node for True Random Number Generator
8c3093895033 ARM: dts: omap: am335x-cm-t335: Remove unused mcasp num-serializer property
cc606b2662cc ARM: dts: ti: omap: omap3-devkit8000-lcd: Fix ti,keep-vref-on property to use correct boolean syntax in DTS
c2478114d962 ARM: dts: ti: omap: am335x-baltos: Fix ti,en-ck32k-xtal property in DTS to use correct boolean syntax
71ffc58ad228 ARM: dts: omap: Minor whitespace cleanup
1ebdb5958f1e ARM: dts: omap: dm816x: Split 'reg' per entry
c1f5a8c95fe6 ARM: dts: omap: dm814x: Split 'reg' per entry
5350ec6a0bb3 ARM: dts: am33xx-l4: fix UART compatible
8637d04530ae ARM: dts: ti: omap4: Use generic "ethernet" as node name
9641963efd82 regulator: pf530x: NXP PF530x regulator driver
5606650260bc regulator: dt-bindings: nxp,pf530x: Add NXP PF5300/PF5301/PF5302 PMICs
78f1121cc21e dt-bindings: display: Add Mayqueen Pixpaper e-ink panel
1d564eebcf7a dt-bindings: vendor-prefixes: Add Mayqueen name
c4993b157c0e dt-bindings: panel: lvds: Append edt,etml0700z8dha in panel-lvds
bc727b4a6797 dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1
a02fc5a9c2bd arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
1850e210ec24 arm64: dts: broadcom: delete redundant pcie enablement nodes
26b6e040715b arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5
0bb7d2239391 arm64: dts: rp1: Add ethernet DT node
23f3ba6fc2b7 dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller
869b849e4fa7 arm64: dts: broadcom: bcm2712: Add UARTA controller node
cb08d2ab4ad2 arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
d64b6ad21f34 arm64: dts: broadcom: bcm2712: Add one more GPIO node
08d8f09ba8d5 arm64: dts: broadcom: bcm2712: Add pin controller nodes
83a3523dd21b Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
d94b2240bdbe Merge tag 'cpufreq-arm-updates-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
f14fb0f94683 dt-bindings: gpu: Convert aspeed,ast2400-gfx to DT schema
a31c1c85876b riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader
8d5c520b73b7 riscv: dts: starfive: jh7110: add DMC memory controller
bb1e87ac367f dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
d6b27e93db0c ASoC: dt-bindings: Document routing strings for
d04d4e49b79b arm64: dts: axis: Add ARTPEC-8 Grizzly dts support
0590f98a06a3 arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
1cbb9bf7e54d dt-bindings: input: touchscreen: imagis: add missing minItems
2015bb86ed18 dt-bindings: net: sun4i-emac: add dma support
219440dbdabd arm64: dts: toshiba: tmpv7708: Add default GIC address cells
efc1efef0bd4 arm64: dts: amazon: alpine-v3: Add default GIC address cells
b8c23f3df909 arm64: dts: amazon: alpine-v2: Add default GIC address cells
267a737344fa arm64: dts: apm: storm: Add default GIC address cells
32e0bc492da8 dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
540414ac3b51 dt-bindings: arm: axis: Add ARTPEC-8 grizzly board
7fcaa3901481 dt-bindings: firmware: qcom,scm: Add MSM8937
ae3857961984 Merge branch '[email protected]' into clk-for-6.18
e892afe3f097 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller
5233ff9e2110 arm64: dts: amlogic: sm1-bananapi: lower SD card speed for stability
650f1668f8a0 arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC
55db8a117690 arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC
b2ad260ce600 arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC
ab766c705da7 arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC
14c0c64b36fb arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC
d408bdfafffa arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC
a766d4297642 arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS
1e546afc638a arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS
81028408a70e arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS
59213de3a796 arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
c7fcd8e0f226 arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC
29770e598553 arm64: dts: amlogic: C3: Add RTC controller node
50bd168c7fd1 riscv: sophgo: dts: sg2044: Change msi irq type to IRQ_TYPE_EDGE_RISING
e512fbb284c8 riscv: sophgo: dts: sg2042: Change msi irq type to IRQ_TYPE_EDGE_RISING
51e575de2de0 ASoC: dt-bindings: qcom,lpass-va-macro: Update bindings for clocks to support ADSP
dc56bfc8614e ASoC: dt-bindings: wlf,wm8960: Document routing strings (pin names)
750b20f53237 ASoC: dt-bindings: nuvoton,nau8825: Document routing strings
2ab07568c5ad ASoC: dt-bindings: everest,es8316: Document routing strings
e6e69bd01434 dt-bindings: power: add Amlogic S6 S7 S7D power domains
0567c19183d7 arm64: dts: renesas: rzt2h-n2h-evk-common: Enable EEPROM on I2C0
a063405cb585 arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1 support
adb7672dd21b arm64: dts: renesas: rzt2h-n2h-evk-common: Add pinctrl for SCI0 node
46ee8a67e311 arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs
dac839381b24 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs
ac688426ec16 arm64: dts: renesas: r9a09g087: Add pinctrl node
491d15bc999c dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
0d2ffff95ace riscv: dts: spacemit: uart: remove sec_uart1 device node
ec62e3191d7e dt-bindings: display/msm: expand to support MST
b60f6321568b dt-bindings: display/msm: drop assigned-clock-parents for dp controller
cde9388325d5 dt-bindings: display/msm: dp-controller: add X1E80100
22c42d8c32d6 dt-bindings: display/msm: qcom,x1e80100-mdss: correct DP addresses
03f8cc85888d dt-bindings: display/msm: dp-controller: document DP on SM7150
1c7f55cc8d82 dt-bindings: display/msm: dp-controller: fix fallback for SM6350
9de1192883a4 dt-bindings: display/msm: dp-controller: allow eDP for SA8775P
a73794916628 dt-bindings: clock: qcom: document the Glymur Global Clock Controller
98c5b9eb2a4a dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller
cb9fd3d8a4d4 dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs
15330c7665c5 dt-bindings: net: renesas,rzn1-gmac: Constrain interrupts
2fdaab120e9a dt-bindings: net: altr,socfpga-stmmac: Constrain interrupts
2dd65ebea4b9 dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC
f3eacf4f0508 Documentation: Fix spelling mistakes
1fe737607c2c dt-bindings: clock: rp1: Add missing MIPI DSI defines
aabb8fcd0753 ARM: dts: BCM5301X: Add support for Buffalo WXR-1750DHP
ebc4c0b3bce5 dt-bindings: arm: bcm: Add support for Buffalo WXR-1750DHP
312fa59c5a9d arm64: dts: broadcom: bcm2712: Add default GIC address cells
a0d188e592e8 spi: spi-fsl-dspi: Target mode improvements
1d756f0ba611 ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15
e03e862db22b ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp13
7b5cf688073e ARM: dts: stm32: Add leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx
39fea1f73910 ARM: dts: stm32: Add pinmux for CM4 leds pins
e02794c22a50 Documentation: fix typo 'Andorid' -> 'Android' in goldfish pipe binding
0eafb231e89d dt-bindings: display: samsung: Drop S3C2410
0f644227dbe2 dt-bindings: arm: Add Cortex-A320/A520AE/A720AE cores and PMU
66c73bcb58cf dt-bindings: arm: cpus: Allow fsl,soc-operating-points for i.MX6
2cff26c9e40b dt-bindings: display: dsi-controller: add bridge to patternProperties
c71d11ad979e dt-bindings: interrupt-controller: marvell,cp110-icu: Document address-cells
aeaa74d69ed4 dt-bindings: vendor-prefixes: Add undocumented vendor prefixes
c6124ae1aa94 dt-bindings: display: rockchip,dw-mipi-dsi: Narrow clocks for rockchip,rk3288-mipi-dsi
3cbd74ac0448 dt-bindings: display: ti,tdp158: Add missing reg constraint
c2026fa2a004 dt-bindings: display: ingenic,jz4780-hdmi: Add missing clock-names
940904e2b725 yamllint: Drop excluding quoted values with ',' from checks
5bedf044c2f2 docs: devicetree: fix typo in writing-schema.rst
8e0b16666d88 docs: dt: writing-bindings: Document node name ABI and simple-mfd
f41ee6cc7f57 dt-bindings: soc: add vf610 reboot syscon controller
70b2436110d2 dt-bindings: input: touchscreen: tsc2007: Document 'wakeup-source'
d1d29ffcaf1d dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
421ba56af722 dt-bindings: input: tsc2007: use comma in filename
04546acb85d6 ASoC: dt-bindings: qcom: Add Glymur LPASS wsa and va macro codecs
afcae06195f0 ASoC: dt-bindings: qcom,sm8250: Add glymur sound card
823e2c677ad8 arm64: dts: exynos8895: Minor whitespace cleanup
f7d4423d501e ARM: dts: stm32: Drop redundant status=okay
91c7a230444a arm64: dts: stm32: Minor whitespace cleanup
2a775334e7fa ARM: dts: stm32: Minor whitespace cleanup
cb967fc546f9 ARM: dts: stm32: stm32mp151c-plyaqm: Use correct dai-format property
5774eb684791 ARM: dts: aspeed: Drop "sdhci" compatibles
20f9d24996ed ARM: dts: aspeed: Fix/add I2C device vendor prefixes
1e4e54bf47d6 ARM: dts: aspeed: Minor whitespace cleanup
3ddaba20c533 ARM: dts: aspeed: clemente: add Meta Clemente BMC
de60205c44b3 ARM: dts: aspeed: Add NCSI3 and NCSI4 pinctrl nodes
da852bae59b2 dt-bindings: arm: aspeed: add Meta Clemente board
b841bb26c800 ARM: dts: aspeed: harma: add mp5990
24d04f86a522 ARM: dts: aspeed: harma: revise gpio name
c10ce6f16a87 ARM: dts: aspeed: harma: add power monitor support
c0db45c36856 riscv: dts: spacemit: Enable PDMA on Banana Pi F3 and Milkv Jupiter
f970ca778551 riscv: dts: spacemit: Add PDMA node for K1 SoC
56f322700a7f dt-bindings: net: move ptp-timer property to ethernet-controller.yaml
0d6aece064fb dt-bindings: ptp: add NETC Timer PTP clock
30fb0a924efe dt-bindings: pinctrl: samsung: Drop S3C2410
8b3840f9629e dt-bindings: leds: issi,is31fl319x: Drop 'db' suffix duplicating dtschema
4cd49e1e14e5 dt-bindings: arm: samsung: Drop S3C2416
c8208f158486 dt-bindings: mtd samsung-s3c2410: Drop S3C2410 support
7ebc8e150a90 dt-bindings: arm: Add device Trace Network On Chip definition
2fd7dc887d58 dt-bindings: dma: rz-dmac: Document RZ/G3E family of SoCs
e0bca91165ee dt-bindings: dma: Add SpacemiT K1 PDMA controller
84a6a55176bf dt-bindings: dmaengine: xilinx_dma: Remove DMA client properties
fed78b7bdd32 arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX
0e5fa75fd7ba arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B
a01057d657cf arm64: dts: rockchip: Add DP1 for rk3588
0ec6d73b355b arm64: dts: rockchip: Add DP0 for rk3588
6b4efb438e72 arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2
e8f269b8dd8b dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2
3ba04aa78ba7 arm64: dts: rockchip: Add ArmSoM Sige1
0fff3afe12c5 dt-bindings: arm: rockchip: Add ArmSoM Sige1
d272bc0c747a arm64: dts: rockchip: Add Radxa ROCK 2A/2F
0c0db6da54c0 dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F
6b3c30392e27 dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon
f4b5e45377bb arm64: dts: rockchip: add USB3 on Beelink A1
2efe54191266 arm64: dts: rockchip: add SPDIF audio to Beelink A1
5fd233dd2c8b arm64: dts: qcom: sc8180x: Add video clock controller node
d849fe603a9b arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455
dfcad07c9815 dt-bindings: arm: qcom: Add Dell Inspiron 14 Plus 7441
43d178879dd3 arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13: Set up 4-lane DP
6f45f39cbe23 arm64: dts: qcom: msm8953: Add device tree for Billion Capture+
afbe3c5f6307 dt-bindings: arm: qcom: Add Billion Capture+
7ba680df6a36 dt-bindings: vendor-prefixes: Add Flipkart
f9898f68c9ea arm64: dts: qcom: ipq5424: Add reserved memory for TF-A
5cd0591f77bc arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths
1d2e6bf9c57b arm64: dts: qcom: lemans: add GDSP fastrpc-compute-cb nodes
38eecace5051 arm64: dts: qcom: sm8450: Fix address for usb controller node
da961db33736 arm64: dts: qcom: add initial support for Samsung Galaxy S20 FE
a2e4a11f1acb dt-bindings: arm: qcom: document r8q board binding
b54b7a7b66a1 arm64: dts: qcom: Add Lenovo ThinkBook 16 G7 QOY device tree
c7445f7d0809 dt-bindings: arm: qcom: Add Lenovo TB16 support
87e37778975d arm64: dts: qcom: x1e80100-qcp: Add missing pinctrl for eDP HPD
b3f5664c24ca arm64: dts: qcom: x1e80100-microsoft-romulus: Add missing pinctrl for eDP HPD
dcf8c321a37f arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add missing pinctrl for eDP HPD
bb41ac8f2180 arm64: dts: qcom: x1e80100-hp-omnibook-x14: Add missing pinctrl for eDP HPD
4a7dc35355aa arm64: dts: qcom: x1e80100-dell-xps13-9345: Add missing pinctrl for eDP HPD
0a1e158083c8 arm64: dts: qcom: x1e80100-asus-vivobook-s15: Add missing pinctrl for eDP HPD
758733086579 arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Add missing pinctrl for eDP HPD
1e7c7d30bf40 arm64: dts: qcom: x1-crd: Add missing pinctrl for eDP HPD
f560c793e8d1 arm64: dts: qcom: x1-asus-zenbook-a14: Add missing pinctrl for eDP HPD
45b02cbfecb4 arm64: dts: qcom: x1e80100: Add pinctrl template for eDP0 HPD
0b41672cf53c arm64: dts: qcom: x1e80100: Set up 4-lane DP
4ae95e5867f0 arm64: dts: qcom: sm8650: Set up 4-lane DP
c4649a1b354f arm64: dts: qcom: sm8550: Set up 4-lane DP
1f3f37d5ee2a arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi
82cc8ac77533 arm64: dts: qcom: sm8650: move dp0 data-lanes to SoC dtsi
aca71f98a6e4 arm64: dts: qcom: sm8550: move dp0 data-lanes to SoC dtsi
9fc63545c481 arm64: dts: qcom: x1e80100: allow mode-switch events to reach the QMP Combo PHYs
deaf372f15c9 arm64: dts: qcom: sm8650: allow mode-switch events to reach the QMP Combo PHY
7c5c462330b2 arm64: dts: qcom: sm8550: allow mode-switch events to reach the QMP Combo PHY
86fbd39d7db7 arm64: dts: qcom: sm8750: Add PCIe PHY and controller node
416151c12db8 arm64: dts: qcom: msm8976-longcheer-l9360: Add touch keys
22660424f72f arm64: dts: qcom: starqltechn: remove extra empty line
2cb5c61f7a18 arm64: dts: qcom: msm8953: add spi_7
12c5a0073828 arm64: dts: qcom: msm8953: correct SPI pinctrls
76678aebed61 arm64: dts: qcom: msm8953: fix SPI clocks
085e748ae3be arm64: dts: qcom: sdm845-shift-axolotl: set chassis type
0cd57a87a101 arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camcc
7cd23c8c5418 arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc
06dc74f60709 arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camcc
ffb93b6a5b89 arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc
5db504f534fe arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc
25eec3013072 arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc
1d07e4677488 dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1051
98d07b8e8674 ARM: dts: qcom: Use GIC_SPI for interrupt-map for readability
3d87387d32f1 ARM: dts: qcom: sdx55: Add default GIC address cells
6e6cfb89a30a ARM: dts: qcom: ipq8064: Add default GIC address cells
fb6394873a94 ARM: dts: qcom: apq8064: Add default GIC address cells
f903b8d9cdf2 ARM: dts: qcom: ipq4019: Add default GIC address cells
ab6041a0738e dt-bindings: display: sitronix,st7567: add optional inverted property
d0f547e1a15f dt-bindings: display: sitronix,st7571: add optional inverted property
5643bd61260b dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU support
7599ee38a553 Merge tag 'sti-dt-for-v6.18-round1' of https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
080d65a7f129 Merge tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
fe0c15d2897b Merge tag 'ixp4xx-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt
ed08d464e7f6 Merge tag 'ux500-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into soc/dt
f7b26e9a7513 Merge tag 'nuvoton-arm64-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
8911b055a364 Merge tag 'nuvoton-arm-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
62c807a0a494 Merge tag 'aspeed-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
d5b7a460acda Merge tag 'apple-soc-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
fcb4f363bfbf dt-bindings: gpio: Add Tegra256 support
de8db4dc0e7c dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC
b404e489d151 arm64: dts: apple: Add devicetreee for t8112-j415
a37810aacca4 dt-bindings: arm: apple: Add t8112 j415 compatible
bb0d69f15c76 arm64: dts: apple: t600x: Add bluetooth device nodes
997a4f4556b6 arm64: dts: apple: t600x: Add missing WiFi properties
a228e50c5f84 arm64: dts: apple: t8103-j457: Fix PCIe ethernet iommu-map
31c7c2a809c9 dt-bindings: arm: Convert Axis board/soc bindings to json-schema
d01bd7ed514c Merge branch 'for-v6.18/dt-bindings-clk' into next/clk
38979c46b872 dt-bindings: clock: Add ARTPEC-8 clock controller
b62b226e9fd0 dt-bindings: iio: adc: add IIO backend support
3bd2c0dbf7e2 arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
dc7a29526275 arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells
ce5931c24674 arm64: dts: exynos2200: Add default GIC address cells
877a63c3c7b7 dt-bindings: clock: exynos990: Extend clocks IDs
16eceec6e156 dt-bindings: media: rkisp1: Add second power domain on i.MX8MP
be85d1c14a23 dt-bindings: media: rkisp1: Require pclk clock on i.MX8MP variant
66472ace1b07 dt-bindings: media: nxp,imx-mipi-csi2: Add fsl,num-channels property
0aa9a3b8123c dt-bindings: media: nxp,imx-mipi-csi2: Mark clock-frequency as deprecated
5f6d35a16d1b arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
4e356855616c arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5
f20ef6037b7b dt-bindings: iio: adc: adi,ad7124: fix clocks properties
7e1779e28670 ARM: dts: rockchip: add HDMI audio to rk3288-miqi
2769f0b6bb92 ARM: dts: rockchip: add CEC pinctrl to rk3288-miqi
207afd78af6c arm64: dts: rockchip: add IR receiver to rk3328-roc
c75fc79da374 arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro
42dd8fe74691 arm64: dts: fsd: Add default GIC address cells
da17dc8dee63 arm64: dts: google: gs101: Add default GIC address cells
6fd45d92dbfd arm64: dts: exynos5433: Add default GIC address cells
d29690b41a78 arm64: dts: exynos2200: define all usi nodes
a0fc2e71abc0 arm64: dts: exynos2200: increase the size of all syscons
3224f3b2124d arm64: dts: exynos2200: use 32-bit address space for /soc
6ec25e50abe6 arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label
5586b6249733 ARM: dts: microchip: sama7d65: add uart3 definition for flexcom3 peripheral
5cac31fed4e2 ARM: dts: microchip: sama7d65: Add GPIO buttons and LEDs
a39cff09db08 dt-bindings: crypto: Add binding for TI DTHE V2
89e423f37054 Merge tag 'renesas-pinctrl-for-v6.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
12b2dfdc946c dt-bindings: pinctrl: Convert brcm,iproc-gpio to DT schema
a48a46cbdd0b dt-bindings: pinctrl: Convert brcm,bcm2835-gpio to DT schema
c05a21a734dc MIPS: dts: loongson: Add CQ-T300B board
c578b8a0c3a6 MIPS: dts: loongson: Add Smartloong-1C board
b3055587010b MIPS: dts: loongson: Add LSGZ_1B_DEV board
3b75d44a329b MIPS: dts: loongson: Add LS1B-DEMO board
052c71426646 dt-bindings: mips: loongson: Add LS1B-DEMO and CQ-T300B
0547b077bf4a mips: lantiq: danube: rename stp node on EASY50712 reference board
7395a9e2ff11 mips: lantiq: danube: add model to EASY50712 dts
fc24e19178f9 mips: lantiq: danube: add missing device_type in pci node
e5f2abf53381 mips: lantiq: danube: add missing properties to cpu node
3e6761ea1466 dt-bindings: mips: cpu: Add MIPS 34Kc Core
7df383e158f0 MIPS: BMIPS: Properly define memory controller compatible
604ea9b1267a Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
3eb3a812a520 ARM: dts: Add ixp4xx Actiontec MI424WR device trees
ff7783797a22 dt-bindings: arm: ixp4xx: List actiontec devices
2b6da8432e9d dt-bindings: Add Actiontec vendor prefix
314fea36ff83 arm64: zynqmp: Add support for kd240 board
e53ea43f40ba arm64: zynqmp: Add support for kr260 board
b3412fc572c0 dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs
fea6c0fe302e arm64: zynqmp: Enable PSCI 1.0
e57987d44b76 arm64: zynqmp: Enable DP for zcu100, zcu102, zcu104, zcu111
4a4ba1e6fe9d arm64: zynqmp: Introduce DP port labels
d2630f3cd471 arm64: zynqmp: Fix pwm-fan polarity
f42dbd46ef33 arm64: zynqmp: Update the usb5744 hub node as per binding
7e88e8b0bb55 arm64: zynqmp: Add cap-mmc-hw-reset and no-sd, no-sdio property to eMMC
6128385ebba6 arm64: zynqmp: Remove undocumented arasan,has-mdma property
a30d8eae77a9 arm64: zynqmp: Use generic spi@ name in zcu111-revA
fe179e0d3682 arm64: versal-net: Update rtc calibration value
d03547035d66 dt-bindings: display/msm: describe MDSS on SC8180X
d7d75da8eb17 dt-bindings: display/msm: describe DPU on SC8180X
3d8934ee23cd dt-bindings: display/msm: dsi-controller-main: add SC8180X
229117a2752c dt-bindings: display/msm/gpu: describe clocks for each Adreno GPU type
4a073b389a16 dt-bindings: display/msm/gpu: describe alwayson clock
bd882ab50d33 dt-bindings: display/msm/gpu: account for 7xx GPUs in clocks conditions
e93a43f28feb ASoC: renesas: msiof: Make small adjustments to avoid
c138331fd63e ARM: dts: ste-ux500-samsung: dts bluetooth wakeup interrupt
04ee152dbc45 ARM: dts: st: ste-nomadik: Align GPIO hog name with bindings
ca719b5b3128 dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value
44ac10fce3a2 dt-bindings: PCI: ti,am65: Extend for use with PVU
1b0ab27bcb4c dt-bindings: arm: stm32: add required #clock-cells property
56bf5c94fec0 dt-bindings: display: st,stm32mp25-lvds: add power-domains property
fa45080f6fa3 dt-bindings: display: st,stm32mp25-lvds: add access-controllers property
2277e1d13817 dt-bindings: display: st: add new compatible to LVDS device
fdbb5ad45827 dt-bindings: display: st,stm32-ltdc: add access-controllers property
230111b9b98e dt-bindings: display: st: add two new compatibles to LTDC device
43d3828e0eb3 dt-bindings: display: rockchip: Add schema for RK3588 DPTX Controller
3beb528e5517 arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro
9b8f468601f7 arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S
049d02600372 dt-bindings: net: pse-pd: Add bindings for Si3474 PSE controller
3e0a5d2a03b7 ARM: dts: stm32: use recent scl/sda gpio bindings
7d8b59465a20 ARM: dts: cirrus: ep7211: use recent scl/sda gpio bindings
20b11d1c35da dt-bindings: Remove outdated cpufreq-dt.txt
c73494fb39fa dt-bindings: ata: imx: Document 'target-supply'
f1e003301ff9 dt-bindings: ata: highbank: Minor whitespace cleanup in example
21e203a6b2ca dt-bindings: nfc: ti,trf7970a: Restrict the ti,rx-gain-reduction-db values
c9a4bd9e79e3 dt-bindings: PCI: qcom,pcie-sm8550: Add SM8750 compatible
fbab833be11f dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings
ff6ce5753de1 dt-bindings: panel: lvds: Append ampire,amp19201200b5tzqw-t03 in panel-lvds
5831ec3f37b6 dt-bindings: PCI: Correct example indentation
f1ba4466860a dt-bindings: gpio: Minor whitespace cleanup in example
2966c7b78f0b dt-bindings: gpio: Move fsl,mxs-pinctrl.txt into gpio-mxs.yaml
819b99032a79 dt-bindings: net: Drop vim style annotation
d87e82c8ebf0 dt-bindings: net: litex,liteeth: Correct example indentation
74244a8112a8 dt-bindings: gpio-mmio: Add MMIO for IXP4xx expansion bus
e5473be8633e dt-bindings: gpio-mmio: Support hogs
2fcfddbfe05a dt-bindings: iio: adi,ltc2664: Minor whitespace cleanup in example
dd8ead550a9d dt-bindings: iio: adc: max1238: Add #io-channel-cells property
9f014a4118cf dt-bindings: iio: mcp9600: Add microchip,mcp9601 and add constraints
b78354d7fca7 dt-bindings: pinctrl: qcom,sc7280-lpass-lpi-pinctrl: Document the clock property
259f63dc34b1 dt-bindings: iio: mcp9600: Set default 3 for thermocouple-type
03055735dba5 MAINTAINERS: Update xilinx-ams driver maintainers
5d538a419700 Merge 6.17-rc3 into char-misc-next
7c466d53e3c6 Merge 6.17-rc3 into usb-next
fa5a2be1a4a1 riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node
50323bc6f8d9 arm64: dts: rockchip: enable NPU on OPI5/5B
f365b4a0c682 arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10
5e0eac5501c7 arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10
6b0192e3fb2a arm64: dts: rockchip: Add RTC on rk3576-evb1-v10
a9c5b3ecfba2 arm64: dts: rockchip: Add HINLINK H66K
7afb22253146 arm64: dts: rockchip: Add HINLINK H68K
5972684d7a17 dt-bindings: arm: rockchip: Add HINLINK H66K / H68K
48a4d2c422d4 dt-bindings: vendor-prefixes: Add HINLINK
3472597ee6b0 arm64: dts: rockchip: Enable RK3576 watchdog
794820151c0c dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
ab45d49b050f riscv: dts: spacemit: add UART resets for Soc K1
93a1fb39d1e5 arm64: dts: rockchip: add USB-C support for ROCK 5B/5B+/5T
517c83473b22 arm64: dts: rockchip: Add green power LED to rk3588s-rock-5a
35a895f6e903 arm64: dts: rockchip: Enable more power domains for RK3528
9571b3aef6a5 arm64: dts: rockchip: Enable the NPU on the orangepi 5 boards
8059a828c207 arm64: dts: rockchip: Enable HDMI receiver on orangepi 5 plus
c9100db0fb4f arm64: dts: qcom: Use GIC_SPI for interrupt-map for readability
d0bea601505a arm64: dts: qcom: sm8350: Add default GIC address cells
afd47647c7fa arm64: dts: qcom: sm8250: Add default GIC address cells
ab4911bed7d0 arm64: dts: qcom: sm8150: Add default GIC address cells
c1b64ed851d6 arm64: dts: qcom: sm6150: Add default GIC address cells
f6972c659be6 arm64: dts: qcom: sc8180x: Add default GIC address cells
32633ead73dd arm64: dts: qcom: qcs404: Add default GIC address cells
b1db19dbed56 arm64: dts: qcom: msm8996: Add default GIC address cells
7046bc4d8f3b arm64: dts: qcom: lemans: Add default GIC address cells
bbbffc4292fa arm64: dts: qcom: ipq5424: Add default GIC address cells
85071fdfd203 arm64: dts: qcom: x1e80100-qcp: Fix swapped USB MP repeaters
34e182c9c94d arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix swapped USB MP repeaters
82b60b5ee7e4 arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Fix swapped USB MP repeaters
5e7a38f97b76 arm64: dts: qcom: x1e001de-devkit: Fix swapped USB MP repeaters
2d58aca899c1 arm64: dts: qcom: Minor whitespace cleanup
a4969a36d50a arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs
c66c98470fa9 arm64: dts: qcom: sm8550: switch to interrupt-cells 4 to add PPI partitions
b254820aa01b arm64: dts: qcom: sm8750-mtp: Add speaker Soundwire port mapping
94fc921beaff arm64: dts: qcom: sdm845: Fix slimbam num-channels/ees
8ea74c4a68dd arm64: dts: qcom: lemans-evk: Enable Display Port
9cc67e1c14f5 ARM: dts: qcom: apq8064-mako: Minor whitespace cleanup
325733292239 arm64: dts: qcom: qcs615: Add CPU scaling clock node
fd3780d5f9d8 arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock
a85c34087535 arm64: dts: qcom: sm6150: move standard clocks to SoC dtsi
204d4a453797 arm64: dts: qcom: use DT label for DSI outputs
664265b6e32a arm64: dts: qcom: ipq9574-rdp433: remove unused 'sdc-default-state'
e4d89e9d82d5 arm64: dts: qcom: sm8550: Correct the min/max voltages for vreg_l6n_3p3
3843ac7d78b1 arm64: dts: qcom: sdm845-oneplus-*: set constant-charge-current-max-microamp
a7ded3fba331 arm64: dts: qcom: ipq9574: use 'pcie' as node name for 'pcie0'
50cebc4bc198 arm64: dts: qcom: sc8280xp: Enable GPI DMA
b410173d6ddd arm64: dts: qcom: sc8280xp: Describe GPI DMA controller nodes
6ede7c2658bf arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default
b538c059c271 arm64: dts: qcom: sc8180x: modernize MDSS device definition
e3c1430e9b33 ARM: dts: qcom: msm8226-samsung-ms013g: Add touch keys
54ddf81668d2 Merge branch '20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-1-c5a8af040093@yandex.ru' into clk-for-6.18
7cb04968ed30 dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs
31a183d41f4c dt-bindings: mailbox: apple,mailbox: Add ASC mailboxes on Apple A11 and T2
df84281860ad arm64: dts: rockchip: add vcc3v3-lcd-s0 regulator to roc-rk3576-pc
c231e4fe4020 arm64: dts: rockchip: add the dsi controller to rk3576
cb1ced992299 arm64: dts: rockchip: add mipi-dcphy to rk3576
6d5dcc7149d2 dt-bindings: soc: rockchip: add rk3576 mipi dcphy syscon
ff6022bba5a3 dt-bindings: display: rockchip: Add rk3576 to RK3588 DW DSI2 controller schema
ec68cdbe762c dt-bindings: display: ili9881c: Add Bestar BSD1218-A101KL68 LCD panel
b11631c821b3 dt-bindings: vendor-prefixes: Add prefix for Shenzhen Bestar Electronic
d3464eb6b1b3 arm64: dts: ti: k3-am69-sk: Switch to PCIe Multilink + USB configuration
da35feda585b arm64: dts: ti: k3-j721s2: Add default PCI interrupt controller address cells
12d230a533d5 arm64: dts: ti: k3-am6548: Minor whitespace cleanup
389d7a0db217 dt-bindings: display: simple-bridge: Add ra620 compatible
510d62368e0e ARM: dts: microchip: Minor whitespace cleanup
08ded368ed48 arm64: dts: rockchip: Add naneng-combphy for RK3528
df02b2dd9a51 arm64: dts: marvell: Minor whitespace cleanup
c2d28ea2478e dt-bindings: mmc: sdhci-pxa: add state_uhs pinctrl
b591c23ba908 arm64: dts: imx95: add fsl,phy-tx-vref-tune-percent tuning properties for USB3 PHY
6c4466dbf3c5 ARM: dts: vfxxx: add arm,num-irq-priority-bits for nvic
a27e7e708d22 ARM: dts: vf610: add grp surfix to pinctrl
ee42f2118aa0 ARM: dts: vf: Change the NAND controller node name
7d1a1fb28c2d ARM: dts: vf: Change the pinctrl node name
1d7852e76bf3 arm64: dts: freescale: Minor whitespace cleanup
866fdbcc1f4e ARM: dts: nxp: imx6ull: Minor whitespace cleanup
590bcebc53fe arm64: dts: imx95-15x15-evk: Change pinctrl settings for usdhc2
47c04bf28d7e arm64: dts: imx95-19x19-evk: Add pf09 and pf53 thermal zones
c240b8470d00 arm64: dts: imx95-19x19-evk: Add pca9632 node
a349bfe611d5 arm64: dts: imx95-19x19-evk: Add Tsettle delay in m2 regulator
aaa3628026db arm64: dts: imx95-evk: Update alias
82299901f88d arm64: dts: imx95: Add coresight nodes
adf488713543 arm64: dts: imx95: Add OCOTP node
5ddb6047fc2a arm64: dts: imx95: Add more V2X MUs
8d28058f4d5e arm64: dts: imx95: Add LMM/CPU nodes
2fa9cb1bdbbb arm64: dts: imx95: Add System Counter node
f19d4d2e2839 arm64: dts: imx95: Correct the lpuart7 and lpuart8 srcid
858653b946d3 arm64: dts: freescale: Switch to hp-det-gpios
b9b2052d6743 ARM: dts: ls1021a: rename rcpm as wakeup-control from power-control
001259f0552c arm64: dts: imx8dxl-ss-conn: Disable USB3 nodes
a030a8f51635 dt-bindings: arm: fsl: add i.MX91 11x11 evk board
aa847ef6d68b arm64: dts: s32g399a-rdb3: Enable the SWT watchdog
461397d690b0 arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes
594bf34226e9 arm64: dts: s32g274-rd2: Enable the SWT watchdog
adc44397c241 arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes
d8864317d548 arm64: dts: s32g399a-rdb3: Enable the STM timers
7a13254ce1fa arm64: dts: s32g3: Add the System Timer Module nodes
0dbdb9a0878f arm64: dts: s32g274-rd2: Enable the STM timers
9dadd7f4d74d arm64: dts: s32g2: Add the System Timer Module nodes
225637459b3f arm64: dts: ti: k3-am62p: Fix supported hardware for 1GHz OPP
2da8345369a1 arm64: dts: freescale: Add dma err irq info on imx94
d2c79d77dfaf arm64: dts: ls1012a: add DTS for TQMLS1012al module with MBLS1012AL board
ebc510e35d83 dt-bindings: arm: fsl: add TQMLS1012AL
e1bc3499cb49 ARM: dts: ls1021a-tqmals1021a-mbsl1021a: Remove superfluous compatible
d0a3db34e79c ARM: dts: ls1021a-tqmals1021a: Remove superfluous address and size cells for qflash
f980805ab52f ARM: dts: ls1021a: remove undocumented 'big-endian' for memory-controller node
1f869ea60bba ARM: dts: ls1021a: remove property 'snps,host-vbus-glitches'
0c7885799121 ARM: dts: ls1021a: Fix watchdog node
c32c6d38cc78 ARM: dts: ls1021a: remove undocumented 'big-endian' for memory-controller node
936a99947ff4 ARM: dts: ls1021a: Remove superfluous address and size cells for queue-group
fb2d4fcd1761 ARM: dts: ls1021a: Add reg property to enet nodes
f0185e90be5f ARM: dts: ls1021a: Fix FTM node
e73ace9c7539 ARM: dts: ls1021a: Fix sai DMA order
6ee45e6662d2 ARM: dts: ls1021a: Fix qspi node unit address
96473576c77d ARM: dts: ls1021a: Fix gic node unit address
3c91879cb8cc arm64: dts: imx93-kontron: Fix USB port assignment
f7c6aa887447 arm64: dts: imx93-kontron: Fix GPIO for panel regulator
94ff6c2f40ba arm64: dts: imx93-kontron: Add RTC interrupt signal
9cc89bf69624 arm64: dts: imx8mp-kontron: Fix USB hub reset
ed11dd28b4c1 arm64: dts: imx8mp-kontron: Fix GPIO labels for latest BL board
511704512b9b arm64: dts: imx8mp-kontron: Fix CAN_ADDR0 and CAN_ADDR1 GPIOs
5894d0dcc690 arm64: dts: imx8mm-kontron: Name USB regulators according to OSM scheme
36f057e78a41 arm64: dts: imx8mm-kontron: Sort reg nodes alphabetically
70f2901af8be arm64: dts: imx8mm-kontron: Add Sitronix touch controller in DL devicetree
55ecf79d0b89 arm64: dts: imx8mm-kontron: Use GPIO for RS485 transceiver control
84a34e55b96d arm64: dts: imx8mm-kontron: Remove unused regulator
4d6bab1782ab arm64: dts: imx8mm-kontron: Add overlay for LTE extension board
8ab339443804 arm64: dts: imx8mn-evk: support more sample rates for wm8524 card
698f9d7f0860 arm64: dts: imx8mq-evk: support more sample rates for wm8524 card
865a6971c26f arm64: dts: imx8mm-evk: support more sample rates for wm8524 card
02592849c173 dt-bindings: input: convert lpc32xx-key.txt to yaml format
0a850409a315 dt-bindings: firmware: arm,scmi: Allow multiple instances
4866eec362c2 ASoC: dt-bindings: Minor whitespace cleanup in example
ab4f6edac068 dt-bindings: pinctrl: rp1: Describe groups for RP1 pin controller
71eab015e127 dt-bindings: net: Add PPE for Qualcomm IPQ9574 SoC
3d132eb0e990 ARM: dts: imx6ulz-bsh-smm-m2: fix resume via console
bdfe509c8036 arm64: dts: imx: add dts for the imx8ulp evk9 board
2b01751cea79 dt-bindings: arm: fsl: add i.MX8ULP EVK9 board
b9c837538f4f dt-bindings: w1: imx: Add an entry for the interrupts property
fc2f3882243f ASoC: dt-bindings: Convert TI TWL4030 sound
427e8369d0ba dt-bindings: dma: nvidia,tegra20-apbdma: Add undocumented compatibles and "clock-names"
3f4545cf82e1 arm64: dts: allwinner: a527: cubie-a5e: Add LEDs
be9b722c1a08 dt-bindings: phy: Add eDP PHY compatible for QCS8300
360e6b390bf8 dt-bindings: phy: renesas,usb2-phy: Add RZ/T2H and RZ/N2H support
9ea781098a87 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Reference usb-switch.yaml to allow mode-switch
a6c42a1fb760 ASoC: dt-bindings: omap-twl4030: convert to DT schema
7ad628891b17 ASoC: dt-bindings: ti,twl4030-audio: convert to DT schema
4d9ec462be3f arm64: dts: renesas: Minor whitespace cleanup
96b048797ec8 arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1
4d8ba5c6332e arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1
4f0e7332fa91 ARM: dts: imx6-display5: Replace license text comment with SPDX identifier
080aba113579 arm64: dts: freescale: imx93-phyboard-nash: Add current sense amplifier
f8f107089640 arm64: dts: imx8mp: Add initial support for Ultratronik imx8mp-ultra-mach-sbc board
a4e23bf7f0a8 dt-bindings: arm: imx8mp: Add Ultratronik Ultra-MACH SBC
14a3b543e328 arm64: dts: freescale: imx93-phycore-som: Delay the phy reset by a gpio
b4e73596622f riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1
44819f77e60c riscv: dts: microchip: Minor whitespace cleanup
a0f6fb2e8eb6 Handle shared reset GPIO for WSA883x speakers
835fafa4e93e dt-bindings: PCI: mediatek-gen3: Add support for MT6991/MT8196
a398da8881bd dt-bindings: power: mediatek: Document access-controllers property
587aceb20cce dt-bindings: pinctrl: Document Tegra186 pin controllers
1ea86d756ef9 dt-bindings: eeprom: Add ST M24LR support
708120963ee7 dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible
517af8eff4bc arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support
f04027c2c146 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag3' into renesas-dts-for-v6.18
877e4b1ee9c5 arm64: dts: renesas: r9a09g077: Add pinctrl node
c01e3229b4b1 arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5
51a69a2c0792 arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5
815abeca1d6e arm64: dts: renesas: r9a09g047: Add I3C node
6fb4e21dc0f2 arm64: dts: renesas: r9a08g045: Add I3C node
cd9bb98c6f23 dt-bindings: power: qcom-rpmpd: add generic bindings for RPM power domains
1769530e1c99 dt-bindings: power: qcom-rpmpd: sort out entries
13294badf3c4 dt-bindings: power: qcom-rpmpd: split RPMh domains definitions
54bc5d8497f2 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the SM8750 QMP PCIe PHY Gen3 x2
e811ad1c43a9 dt-bindings: net: realtek,rtl82xx: document wakeup-source property
d7cf92385c21 Merge tag 'drm-misc-next-2025-08-14' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
1018374c4ab4 dt-bindings: iio: adc: Add BD7910[0,1,2,3]
c48f4415c147 spi: offload-trigger: followup
a4afd86f8d1a ASoC: dt-bindings: qcom,wsa8830: Add reset-gpios for shared line
b50380526a4a dt-bindings: pinctrl: mediatek: mt8183: Allow gpio-line-names
9e4d5ef0d66d ARM: sti: drop B2120 board support
0ef7c7116ca7 dt-bindings: arm: sti: drop B2120 board support
870d218b1153 ARM: dts: sti: rename SATA phy-names
824a1a0a9ced dt-bindings: mmc: fsl,esdhc: Add explicit reference to mmc-controller-common
0f0a58b0b75e dt-bindings: clock: Add CAM_CSI clock macro for FSD
1fe1603e14a6 arm64: dts: renesas: sparrow-hawk: Update thermal trip points
fe6da1077227 arm64: dts: renesas: rzg2: Increase CANFD clock rates
bdc773471947 arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates
ec237308203f ARM: dts: renesas: porter: Fix CAN pin group
d772a38ac88d dt-bindings: iio: Replace bouncing Analog emails
17270a37ac7e dt-bindings: iio: adc: ad7476: Add ROHM bd79105
0aa5a6003818 dt-bindings: iio: adc: ad7476: Drop redundant prop: true
a28e0d32a873 dt-bindings: iio: light: veml6046x00: add color sensor
708a0e938447 dt-bindings: iio: pressure: add invensense,icp10100
97dd18e7b7b7 dt-bindings: iio: light: Simplify interrupts property in the example
68f7d3f838f5 dt-bindings: iio: adc: samsung,exynos-adc: Use correct IRQ level in example
f8daf6098797 dt-bindings: iio: adc: Replace hard-coded GPIO/IRQ flag with a define
3aea09bd7424 dt-bindings: iio: Drop unused header includes in examples
f4d93c76eb66 dt-bindings: iio: adc: rockchip-saradc: Allow use of a power-domain
af62b1730cc7 dt-bindings: powerpc: Drop duplicate fsl/mpic.txt
db979e458e90 dt-bindings: perf: Convert apm,xgene-pmu to DT schema
348b1243c291 dt-bindings: arm: Convert marvell,berlin to DT schema
b994fe37d775 dt-bindings: arm: cpus: Add edac-enabled property
88b6c33eaf64 arm64: dts: qcom: qcm2290: Disable USB SS bus instances in park mode
e97ad0cbe542 Revert "arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22"
ee4f5c87fe01 scsi: ufs: qcom: dt-bindings: Split SM8650 and similar
f4b8ce903610 scsi: ufs: qcom: dt-bindings: Split SC7180 and similar
e4fdbdeacda6 scsi: ufs: qcom: dt-bindings: Split common part to qcom,ufs-common.yaml
773922a00a3f riscv: dts: spacemit: Add OrangePi RV2 board device tree
77d3071b19a4 dt-bindings: riscv: spacemit: Add OrangePi RV2 board
0ff25c60b468 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Glymur SoC
7188e445e554 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
24028c644cd4 dt-bindings: interrupt-controller: Convert hisilicon,mbigen-v2 to DT schema
551fba82674c dt-bindings: arm/cpus: Add missing Applied Micro CPU compatibles
35957b070f5f dt-bindings: arm: Drop obsolete cavium-thunder2.txt
099e5062a89e dt-bindings: arm: Convert cavium,thunder-88xx to DT schema
ecd72699432a dt-bindings: display: Drop duplicate ti,opa362 binding
61be15f398a7 dt-bindings: reset: thead,th1520-reset: add more VOSYS resets
ef4e70ef7b59 dt-bindings: reset: add compatible for bcm63xx ephy control
3638a1012e7c dt-bindings: clock: adi,axi-clkgen: add clock-output-names property
a2e27b94c2b1 dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding
5ebc9a098019 dt-bindings: clock: Convert silabs,si570 to DT schema
34831941d50e dt-bindings: clock: Convert silabs,si5341 to DT schema
7a97a3fc2d11 dt-bindings: clock: Convert silabs,si514/544 to DT schema
a5a1c02268ee dt-bindings: usb: Drop duplicate nvidia,tegra20-ehci.txt
2ac8316b8828 dt-bindings: usb: renesas,usbhs: Add RZ/T2H and RZ/N2H support
7ac10c3a3f66 dt-bindings: arm: Convert ti,keystone to DT schema
af0b95b8caa3 arm64: dts: ti: k3-j722s-main: Add E5010 JPEG Encoder
67f89aff8c4e arm64: dts: ti: k3-am62a-main: Add CSI2 interrupts property
804e4f1a8c76 arm64: dts: ti: k3-am62-main: Add CSI2 interrupts property
918605eeafbe arm64: dts: ti: k3-j722s-main: Add CSI2 interrupts property
f5ab11ee490e arm64: dts: ti: k3-am62p-j722s-common-main: Add CSI2 interrupts property
f395c9e473ff arm64: dts: ti: k3-j784s4-j742s2-main-common: Add CSI2 interrupts property
7688cd113009 arm64: dts: ti: k3-j721e-main: Add CSI2 interrupts property
39ac8af8b7aa arm64: dts: ti: k3-j721s2-main: Add CSI2 interrupts property
19d6c9d128cc arm64: dts: ti: k3-am62a-phycore-som: Add 1.4GHz opp entry
783f64c6d595 arm64: dts: ti: k3-am642-phyboard-electra: Add ti,pa-stats property
f01485872f7a arm64: dts: ti: k3-am68-sk: Enable DSI on DisplayPort-0
c48e09d171bb arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1
f781b893d7b5 arm64: dts: ti: k3-j721s2-som-p0: Add DSI to eDP
ce710a88bb5f arm64: dts: ti: k3-j721s2-common-proc-board: Add main_i2c4 instance
085d16d3e75a arm64: dts: ti: k3-j721s2-main: Add DSI & DSI PHY
b48b14587468 arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable DisplayPort-1
d461e4529f45 arm64: dts: ti: k3-j784s4-j742s2-main-common: Add DSI & DSI PHY
01310ba67fe0 regulator: dt-bindings: Add Richtek RT5133 Support
88e21a5ddd47 arm64: dts: exynos990-r8s: Enable USB
89e83ef82c61 arm64: dts: exynos990-c1s: Enable USB
aad1fc339e95 arm64: dts: exynos990-x1s-common: Enable USB
d0a614c4ef5a arm64: dts: exynos990: Add USB nodes
0c232be41075 arm64: dts: exynos990: Enable watchdog timer
568c8ba46b12 dt-bindings: memory: Update brcmstb-memc-ddr binding with older chips
fa7d8e931304 arm64: dts: exynos: Add Ethernet node for E850-96 board
71c29092ee0c dt-bindings: phy: qcom,snps-eusb2-repeater: Add compatible for PMIV0104
5b8c917b03d1 dt-bindings: phy: qcom,snps-eusb2-repeater: Document qcom,tune-res-fsdif
8d723a834886 dt-bindings: phy: rockchip: naneng-combphy: Add RK3528 variant
3c2056f3de94 dt-bindings: phy: rockchip: naneng-combphy: Add power-domains property
cb4a7be44d46 dt-bindings: soc: rockchip: Add RK3528 pipe-phy GRF syscon
81575c8dee9b dt-bindings: net: airoha: npu: Add memory regions used for wlan offload
68995c0b6180 ASoC: dt-bindings: Convert brcm,bcm2835-i2s to DT schema
24ad993f59c0 dt-bindings: nfc: ti,trf7970a: Drop 'db' suffix duplicating dtschema
2750ab288cc0 arm64: dts: qcom: ipq5424: Enable cpufreq
ec25f9478849 Merge branch '[email protected]' into HEAD
7c40abb8949b arm64: dts: qcom: x1e80100: Add videocc
bd98789e4e9c arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP
44a6435ecc14 arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22
6cae84b9d86b dt-bindings: arm: qcom: document r0q board binding
d045d0620272 arm64: dts: qcom: sdm632-fairphone-fp3: Enable display and GPU
c04f8b9e0791 arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE
206276c046a1 ASoC: codecs: Add support for FourSemi FS2104/5S
c7758c3ddb0d arm64: dts: qcom: sc7280: Add support for two additional DDR frequencies
4790ee8de14e arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss
465738596768 Merge branch '[email protected]' into arm64-for-6.18
326f40a04325 Merge branch '[email protected]' into clk-for-6.18
2ab574cd9e05 dt-bindings: clock: dispcc-sc7280: Add display resets
75f87d6ba891 arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY
be3a291067c0 regulator: add new PMIC PF0900 support
55a3baa2dedb ASoC: dt-bindings: realtek,alc5623: convert to DT schema
f967d51b17cc dt-bindings: phy: fsl,imx8mq-usb: Drop 'db' suffix duplicating dtschema
ce21be5d2955 ARM: dts: renesas: r7s72100: Add boot phase tags
90b801be50ba arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support
d581babf921f arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0
b9a5b30faf64 arm64: dts: renesas: r9a09g047: Add DMAC nodes
125dfecfeaf5 arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article
509e7492588c arm64: dts: renesas: r9a09g087: Add SDHI nodes
4e5a7123dc68 arm64: dts: renesas: r9a09g077: Add SDHI nodes
70cd0bde48d7 arm64: dts: renesas: r9a09g087: Add I2C controller nodes
ef54f3fcad15 arm64: dts: renesas: r9a09g077: Add I2C controller nodes
deae5359a8ca dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS615 compatible
62bb6e50c9c4 dt-bindings: clock: qcom,videocc: Add sc8180x compatible
2f3e2b41a8ca arm64: dts: qcom: sm6350: Add rpmh-stats node
5fca5b1ec497 arm64: dts: qcom: qcm6490-fairphone-fp5: Enable USB audio offload support
900894b4e20a arm64: dts: qcom: sc7280: Add q6usbdai node
5aaa0ead07f8 arm64: dts: qcom: sc7180-acer-aspire1: drop deprecated DP supplies
35e5222e8392 arm64: dts: qcom: move data-lanes to the DP-out endpoint
7c50d75e5122 arm64: dts: qcom: x1e80100: add empty mdss_dp3_out endpoint
f34105c29291 arm64: dts: qcom: sc8280xp: add empty mdss*_dp*_out endpoints
64ea31de6cb8 arm64: dts: qcom: sc8180x: add empty mdss_edp_out endpoint
8f2af792251d arm64: dts: qcom: sa8775p: add link_down reset for pcie
c3fc3b1c07f7 arm64: dts: qcom: sa8775p: remove aux clock from pcie phy
060e0dbc7199 arm64: dts: qcom: sc7280: Flatten usb controller nodes
c74f49e3c38c arm64: dts: qcom: sc7280-chrome-common: Remove duplicate node
54056f7edd82 arm64: dts: qcom: qcm2290: Enable HS eMMC timing modes
c6bbe42d6f51 arm64: dts: qcom: sm6150: Add ADSP and CDSP fastrpc nodes
3ea27a8c6021 arm64: dts: qcom: sm8650: Add ACD levels for GPU
70f0c6b881d6 arm64: dts: qcom: qcm2290: Add TCSR download mode address
df1349f399fd arm64: dts: qcom: sdm845-oneplus: Deduplicate shared entries
35bda99c14dc arm64: dts: qcom: sdm845*: Use definition for msm-id
53d2c800a434 arm64: dts: qcom: sdm670-google-sargo: enable charger
1d6ba6b86fdf arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable HBR3 on external DPs
7aaa0a210ac6 arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs
18d4192600ed ARM: dts: qcom: msm8974-samsung-hlte: Add touchkey support
fabdf8a4c26e ARM: dts: qcom: pm8921: add vibrator device node
bd38f7fc5432 ARM: dts: qcom: add device tree for Sony Xperia SP
5b9e501e86b8 dt-bindings: arm: qcom: add Sony Xperia SP
cc84592a8d8b arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Replace clock-frequency in camera sensor node
b906829f1850 arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader
baf30ed51d22 arm64: dts: qcom: sm8450: Flatten usb controller node
1a70fd8d2f2e arm64: dts: qcom: sm8450-qrd: add pmic glink node
f81dd52f0b74 arm64: dts: qcom: qcs8300-ride: Enable SDHC1 node
a36c203e9486 arm64: dts: qcom: qcs8300: Add eMMC support
896bfff642df dt-bindings: arm: qcom: Remove sdm845-cheza
9040cee49f74 arm64: dts: qcom: Remove sdm845-cheza boards
23df44c7e56a arm64: dts: qcom: sm8750: Add BWMONs
56602ac4f962 arm64: dts: sm8250-xiaomi-pipa: Update battery info
64fe4da1e682 arm64: dts: qcom: sm8250-xiaomi-pipa: Drop unused bq27z561
21b3e9da4d01 arm64: dts: qcom: sm8250-xiaomi-pipa: Drop nonexistent pm8009 pmic
a139470d431d dt-bindings: arm: qcom-soc: Document new Milos and Glymur SoCs
f15ca1b141c7 dt-bindings: soc: qcom,rpmh-rsc: Remove double colon from description
4c1f46dba31d arm64: dts: qcom: qcs615: Set LDO12A regulator to HPM to avoid boot hang
a4305e6ed40f arm64: dts: qcom: qcs6490-rb3gen2: Add missing clkreq pinctrl property
0fdde347c41b arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
26e61171a8ab arm64: dts: ipq5018: Add CMN PLL node
f76708b763c2 arm64: dts: qcom: ipq5018: Add crypto nodes
2d5b71fdad5f arm64: dts: qcom: ipq5018: add PRNG node
2890c6716df1 arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3
b5314949f370 arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP
82ae4275b903 arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
f12185691617 dt-bindings: arm: qcom: Drop redundant free-form SoC list
7b6ed1eab05b dt-bindings: riscv: Add SiFive vendor extensions description
62c84970cd6b arm64: dts: qcom: sm8650: Sort nodes by unit address
a8567af89b00 dt-bindings: arm: qcom: Add Dell Latitude 7455
d58ecb878eb9 arm64: dts: qcom: ipq5018: Add SPI nand support
288cbedb0f46 arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c SDA and SCL
792aa671906e arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCL
e3b57684b98a arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCL
41806bdb4e72 arm64: dts: qcom: pmk8550: Correct gpio node name
e4e08c4523ea arm64: dts: qcom: qcs615-ride: Enable WiFi/BT nodes
3aa869260c7a arm64: dts: qcom: qcs615: add a PCIe port for WLAN
d9143f06344c arm64: dts: qcom: qcs615-ride: Enable PCIe interface
adcea9a4dc02 arm64: dts: qcom: qcs615: enable pcie
2670b05200ab arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
e35d7b0c6936 arm64: dts: qcom: ipq5018: Add MDIO buses
73aa83326c79 arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock
1f21edc5a7bd arm64: dts: qcom: ipq5424: Add CMN PLL node
fe308939ff14 arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB audio offload support
b3abceea09f5 arm64: dts: qcom: sm6350: Add q6usbdai node
b0571de6544d arm64: dts: qcom: qcs615: add missing dt property in QUP SEs
27c4061463bc arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Bluetooth support
48a786f8acf0 arm64: dts: qcom: x1p42100: Add GPU support
765a3f8b321b arm64: dts: qcom: sm8250: Drop venus-enc/decoder node
e90e204d54e9 arm64: dts: qcom: sdm845: Drop venus-enc/decoder node
6372cc8e2b57 arm64: dts: qcom: sc7180: Drop venus-enc/decoder node
a80646398b30 arm64: dts: qcom: msm8916: Drop venus-enc/decoder node
91516cae1e43 arm64: dts: qcom: rename qcs615.dtsi to sm6150.dtsi
f748afb2b28c dt-bindings: arm: qcom: add qcom,sm6150 fallback compatible to QCS615
68c12f308e1d arm64: dts: qcom: sa8775p: rename bus clock to follow the bindings
960dbc6de359 arm64: dts: qcom: sdm850-lenovo-yoga-c630: add routing for second USB connector
e3b73612d98d arm64: dts: qcom: sar2130p: use defines for DSI PHY clocks
e2a620328c37 arm64: dts: qcom: sar2130p: correct VBIF region size for MDSS
3e183540dbf7 arm64: dts: qcom: sar2130p: use TAG_ALWAYS for MDSS's mdp0-mem path
c677d30a34fa arm64: dts: qcom: sdm845: rename DisplayPort labels
f7c964a61304 arm64: dts: qcom: ipq5018: Add tsens node
c0822dcdd7ca dt-bindings: sram: qcom,imem: Document IPQ5424 compatible
91e07bd84403 ARM: dts: qcom: msm8960: disable gsbi1 and gsbi5 nodes in msm8960 dtsi
924093f6b6af ARM: dts: qcom: msm8960: add gsbi8 and its serial configuration
e20ef02de346 ARM: dts: qcom: msm8960: add sdcc3 pinctrl states
d2ef604b4449 dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller
a4525b7117e5 arm64: dts: qcom: sm8650: Flatten the USB nodes
a218770b479b arm64: dts: qcom: sm8550: Flatten the USB nodes
23626812c64f dt-bindings: pinctrl: renesas: Document RZ/T2H and RZ/N2H SoCs
ad829cf16f22 dt-bindings: clock: renesas,r9a09g077/87: Add USB_CLK clock ID
a68464b14b53 dt-bindings: arm: Spell out acronym
26652d979b7f dt-bindings: fsi: Convert aspeed,ast2400-cf-fsi-master to DT schema
0bea5427654c dt-bindings: fsi: Convert fsi-master-gpio to DT schema
73ef7eabc82c regulator: dt-bindings: Clean-up active-semi,act8945a duplication
c264e834008a Merge drm/drm-next into drm-misc-n
af6ffb08184f ASoC: dt-bindings: Add FS2104/5S audio amplifiers
13f7f188e41c dt-bindings: vendor-prefixes: Add Shanghai FourSemi Semiconductor Co.,Ltd
02c015a7c356 dt-bindings: PCI: amd-mdb: Add example usage of reset-gpios for PCIe RP PERST#
aa431b07c8c0 arm64: dts: renesas: r9a09g057: Add RSPI nodes
47f75350b9fa arm64: dts: renesas: Add initial support for the RZ/N2H EVK
ba9b9caaa763 arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H
03b9eb1cfeba arm64: dts: renesas: Refactor RZ/T2H EVK device tree
7b75e0ee9759 arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoC
894531ae9c25 arm64: dts: renesas: Add initial support for the Renesas RZ/T2H eval board
657d39db96a2 arm64: dts: renesas: Add initial support for the Renesas RZ/T2H SoC
834a86800ba9 dt-bindings: soc: samsung: usi: add samsung,exynos2200-usi compatible
49eca61230f2 arm64: dts: rockchip: convert rk3528 power-domains to dt-binding constants
66fe66db502e arm64: dts: rockchip: enable NPU on ROCK 5B
b631f5021a3d arm64: dts: rockchip: Enable the NPU on quartzpro64
c0ccb9bf6100 arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base
e3c892b9d1c9 arm64: dts: rockchip: add pd_npu label for RK3588 power domains
a798fd1ed54e arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes
bac072bdf63d arm64: dts: rockchip: Add thermal nodes to RK3576
c8f033f2bff6 arm64: dts: rockchip: Enable eMMC on rk3576-evb1-v10
af3871f5b62f arm64: dts: rockchip: set LAN LEDs to default-off on Radxa E52C
3a7cfe9ce4a1 arm64: dts: rockchip: Enable HDMI audio output for NanoPi R6C/R6S
cc7e1782a430 dt-bindings: cpufreq: Add mediatek,mt8196-cpufreq-hw binding
4d514e3bf175 dt-bindings: PCI: Add missing "#address-cells" to interrupt controllers
cf02b576c930 arm64: dts: qcom: Add lemans evaluation kit (EVK) initial board support
1096b3e54079 dt-bindings: arm: qcom: lemans: Add bindings for Lemans Evaluation Kit (EVK)
a5a10f55ca6f arm64: dts: qcom: lemans: Fix dts inclusion for IoT boards and update memory map
f70302ff6020 arm64: dts: qcom: lemans: Rename sa8775p-pmics.dtsi to lemans-pmics.dtsi
1895b135ce57 arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards
32faf896f88c arm64: dts: qcom: lemans: Separate out ethernet card for ride & ride-r3
f4f5379130d0 arm64: dts: qcom: lemans: Update memory-map for IoT platforms
bbc9fb3bd353 arm64: dts: qcom: Rename sa8775p SoC to "lemans"
487f7b81f42b arm64: dts: qcom: sm8550: stop using SoC-specific genpd indices
704d2384abd0 arm64: dts: qcom: sm8250: stop using SoC-specific genpd indices
4fff99bb3ad9 arm64: dts: qcom: sm8150: use correct PD for DisplayPort controller
ccf2509e704c arm64: dts: qcom: sa8775p: fix RPMh power domain indices
f2fec46e054b arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845
81bbfa59954a arm64: dts: nuvoton: combine NPCM845 reset and clk nodes
4eb9b08fcd67 arm64: dts: nuvoton: npcm845: Add pinctrl groups
a6d1382343ae ARM: dts: nuvoton: Use generic "ethernet" as node name
2b0af24a508d ARM: dts: aspeed: x570d4u: convert NVMEM content to layout syntax
d7acb9a9fd5d ARM: dts: aspeed: romed8hm3: convert NVMEM content to layout syntax
391ef505affb ARM: dts: aspeed: e3c256d4i: convert NVMEM content to layout syntax
702300ef0669 ARM: dts: aspeed: e3c246d4i: convert NVMEM content to layout syntax
3daaa59c29da ARM: dts: aspeed: Add missing "ibm,spi-fsi" compatibles
1e89ac922a9a ARM: dts: aspeed: Drop "fsi-master" compatibles
855e8c0c664d ARM: dts: aspeed: Drop "no-gpio-delays"
e595eeec948e ARM: dts: aspeed: Add Facebook Darwin (AST2600) BMC
e70625e36b3d dt-bindings: arm: aspeed: add Facebook Darwin board
888574ce0da4 ARM: dts: aspeed: facebook-fuji: Include facebook-fuji-data64.dts
3a416a08dd7b ARM: dts: aspeed: Add Facebook Fuji-data64 (AST2600) Board
5e839485c4a4 dt-bindings: arm: aspeed: add Facebook Fuji-data64 board
4418e1950ab2 ARM: dts: aspeed: wedge400: Include wedge400-data64.dts
ec0580396b8e ARM: dts: aspeed: Add Facebook Wedge400-data64 (AST2500) BMC
4f68c3d06c4c dt-bindings: arm: aspeed: add Facebook Wedge400-data64 board
9ae0b1e74bff ARM: dts: aspeed: Add facebook-bmc-flash-layout-128-data64.dtsi
a1b83c91219b ARM: dts: aspeed: Move eMMC out of ast2600-facebook-netbmc-common.dtsi
be24a9c60773 ARM: dts: aspeed: Fix DTB warnings in ast2600-facebook-netbmc-common.dtsi
4fdec24d7310 ARM: dts: aspeed: fuji: Fix DTB warnings
7b6b7ab82a8f ARM: dts: aspeed: wedge400: Fix DTB warnings
b9634e81fb0b ARM: dts: aspeed: nvidia: gb200nvl: Enable MAC0 for BMC network
14745ba1bbe1 ARM: dts: aspeed: nvidia: gb200nvl: Repurpose the HMC gpio pin
788cbf3d2a4b ARM: dts: aspeed: nvidia: gb200nvl: Enable i2c3 bus
c8e29d77e2f2 ARM: dts: aspeed: nvidia: gb200nvl: Add VCC Supply
9c1aeee260f5 spi: dt-bindings: atmel,at91rm9200-spi: Add support for optional 'spi_gclk' clock
26c278496eb9 dt-bindings: regulator: add PF0900 regulator yaml
ed71d5a9f7a5 ASoC: dt-bindings: Drop imx-audio-sgtl5000.txt
87b631bc8961 arm64: dts: apple: t600x: Add SMC node
0cc0c3fa9b0c arm64: dts: apple: t8112: Add SMC node
41c05a3e96e1 arm64: dts: apple: t8103: Add SMC node
470be74b51b7 arm64: dts: apple: t8015: Add I2C nodes
5f1783181b49 arm64: dts: apple: t8011: Add I2C nodes
0a3661715901 arm64: dts: apple: t8010: Add I2C nodes
42c03e668d3a arm64: dts: apple: s8001: Add I2C nodes
237cd20f2b0e arm64: dts: apple: s800-0-3: Add I2C nodes
786e40a5eb22 arm64: dts: apple: t7001: Add I2C nodes
db434c6f3e2a arm64: dts: apple: t7000: Add I2C nodes
c7b74e8c24fd arm64: dts: apple: s5l8960x: Add I2C nodes
ebe66019a953 dt-bindings: display: panel: Add waveshare DPI panel support
ca487f722076 dt-bindings: display: bridge: Add waveshare DSI2DPI unit support
950b8e44ee1a dt-bindings: display: panel: Document Hydis HV101HD1 DSI panel
d1fecc297abb dt-bindings: display: panel: document Samsung AMS561RA01 panel with S6E8AA5X01 controller
00fe34c42551 dt-bindings: display: simple: Add Olimex LCD-OLinuXino-5CTS
2234fad7fa70 dt-bindings: display: panel: samsung,atna40ct06: document ATNA40CT06
a5ae2fea341c dt-bindings: display: panel: samsung,atna40cu11: document ATNA40CU11
b691760932a5 dt-bindings: display: bridge: Document Solomon SSD2825
ad4143f2b0d4 dt-bindings: npu: rockchip,rknn: Add bindings

git-subtree-dir: dts/upstream
git-subtree-split: 08831944f4e7c612801d082000064e4fb0ccd2aa

45 files changed, 3511 insertions, 300 deletions

diff --git a/include/dt-bindings/clock/aspeed,ast2700-scu.h b/include/dt-bindings/clock/aspeed,ast2700-scu.h
index 63021af3caf..bacf712e8e0 100644
--- a/include/dt-bindings/clock/aspeed,ast2700-scu.h
+++ b/include/dt-bindings/clock/aspeed,ast2700-scu.h
@@ -68,6 +68,9 @@
 #define SCU0_CLK_GATE_UFSCLK	53
 #define SCU0_CLK_GATE_EMMCCLK	54
 #define SCU0_CLK_GATE_RVAS1CLK	55
+#define SCU0_CLK_U2PHY_REFCLKSRC 56
+#define SCU0_CLK_AHBMUX			57
+#define SCU0_CLK_MPHYSRC		58
 
 /* SOC1 clk */
 #define SCU1_CLKIN		0
@@ -159,5 +162,6 @@
 #define SCU1_CLK_GATE_PORTCUSB2CLK	84
 #define SCU1_CLK_GATE_PORTDUSB2CLK	85
 #define SCU1_CLK_GATE_LTPI1TXCLK	86
+#define SCU1_CLK_I3C				87
 
 #endif
diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bindings/clock/axis,artpec8-clk.h
new file mode 100644
index 00000000000..1e6e1409dd9
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec8-clk.h
@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025 Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-8 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
+#define _DT_BINDINGS_CLOCK_ARTPEC8_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL					1
+#define CLK_DOUT_SHARED0_DIV2					2
+#define CLK_DOUT_SHARED0_DIV3					3
+#define CLK_DOUT_SHARED0_DIV4					4
+#define CLK_FOUT_SHARED1_PLL					5
+#define CLK_DOUT_SHARED1_DIV2					6
+#define CLK_DOUT_SHARED1_DIV3					7
+#define CLK_DOUT_SHARED1_DIV4					8
+#define CLK_FOUT_AUDIO_PLL					9
+#define CLK_DOUT_CMU_BUS					10
+#define CLK_DOUT_CMU_BUS_DLP					11
+#define CLK_DOUT_CMU_CDC_CORE					12
+#define CLK_DOUT_CMU_OTP					13
+#define CLK_DOUT_CMU_CORE_MAIN					14
+#define CLK_DOUT_CMU_CORE_DLP					15
+#define CLK_DOUT_CMU_CPUCL_SWITCH				16
+#define CLK_DOUT_CMU_DLP_CORE					17
+#define CLK_DOUT_CMU_FSYS_BUS					18
+#define CLK_DOUT_CMU_FSYS_IP					19
+#define CLK_DOUT_CMU_FSYS_SCAN0					20
+#define CLK_DOUT_CMU_FSYS_SCAN1					21
+#define CLK_DOUT_CMU_GPU_3D					22
+#define CLK_DOUT_CMU_GPU_2D					23
+#define CLK_DOUT_CMU_IMEM_ACLK					24
+#define CLK_DOUT_CMU_IMEM_JPEG					25
+#define CLK_DOUT_CMU_MIF_SWITCH					26
+#define CLK_DOUT_CMU_MIF_BUSP					27
+#define CLK_DOUT_CMU_PERI_DISP					28
+#define CLK_DOUT_CMU_PERI_IP					29
+#define CLK_DOUT_CMU_PERI_AUDIO					30
+#define CLK_DOUT_CMU_RSP_CORE					31
+#define CLK_DOUT_CMU_TRFM_CORE					32
+#define CLK_DOUT_CMU_VCA_ACE					33
+#define CLK_DOUT_CMU_VCA_OD					34
+#define CLK_DOUT_CMU_VIO_CORE					35
+#define CLK_DOUT_CMU_VIO_AUDIO					36
+#define CLK_DOUT_CMU_VIP0_CORE					37
+#define CLK_DOUT_CMU_VIP1_CORE					38
+#define CLK_DOUT_CMU_VPP_CORE					39
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER					1
+#define CLK_MOUT_BUS_DLP_USER					2
+#define CLK_DOUT_BUS_PCLK					3
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER					1
+#define CLK_MOUT_CORE_DLP_USER					2
+#define CLK_DOUT_CORE_PCLK					3
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL					1
+#define CLK_MOUT_CPUCL_PLL					2
+#define CLK_MOUT_CPUCL_SWITCH_USER				3
+#define CLK_DOUT_CPUCL_CPU					4
+#define CLK_DOUT_CPUCL_CLUSTER_ACLK				5
+#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG				6
+#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK				7
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK				8
+#define CLK_DOUT_CPUCL_PCLK					9
+#define CLK_DOUT_CPUCL_CMUREF					10
+#define CLK_DOUT_CPUCL_DBG					11
+#define CLK_DOUT_CPUCL_PCLKDBG					12
+#define CLK_GOUT_CPUCL_CLUSTER_CPU				13
+#define CLK_GOUT_CPUCL_SHORTSTOP				14
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG			15
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK			16
+
+/* CMU_FSYS */
+#define CLK_FOUT_FSYS_PLL					1
+#define CLK_MOUT_FSYS_SCAN0_USER				2
+#define CLK_MOUT_FSYS_SCAN1_USER				3
+#define CLK_MOUT_FSYS_BUS_USER					4
+#define CLK_MOUT_FSYS_MMC_USER					5
+#define CLK_DOUT_FSYS_PCIE_PIPE					6
+#define CLK_DOUT_FSYS_ADC					7
+#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL			8
+#define CLK_DOUT_FSYS_EQOS_INT125				9
+#define CLK_DOUT_FSYS_OTP_MEM					10
+#define CLK_DOUT_FSYS_SCLK_UART					11
+#define CLK_DOUT_FSYS_EQOS_25					12
+#define CLK_DOUT_FSYS_EQOS_2p5					13
+#define CLK_DOUT_FSYS_BUS300					14
+#define CLK_DOUT_FSYS_BUS_QSPI					15
+#define CLK_DOUT_FSYS_MMC_CARD0					16
+#define CLK_DOUT_FSYS_MMC_CARD1					17
+#define CLK_DOUT_SCAN_CLK_FSYS_125				18
+#define CLK_DOUT_FSYS_QSPI					19
+#define CLK_DOUT_FSYS_SFMC_NAND					20
+#define CLK_DOUT_FSYS_SCAN_CLK_MMC				21
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20	22
+#define CLK_GOUT_FSYS_USB20DRD_IPCLKPORT_BUS_CLK_EARLY		23
+#define CLK_GOUT_FSYS_XHB_USB_IPCLKPORT_CLK			24
+#define CLK_GOUT_FSYS_XHB_AHBBR_IPCLKPORT_CLK			25
+#define CLK_GOUT_FSYS_I2C0_IPCLKPORT_I_PCLK			26
+#define CLK_GOUT_FSYS_I2C1_IPCLKPORT_I_PCLK			27
+#define CLK_GOUT_FSYS_PWM_IPCLKPORT_I_PCLK_S0			28
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG		29
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INXT_0_SLV_ACLK_UG		30
+#define CLK_GOUT_FSYS_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG		31
+#define CLK_GOUT_FSYS_PIPE_PAL_INST_0_I_APB_PCLK		32
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_ACLK_I			33
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_CLK_CSR_I		34
+#define CLK_GOUT_FSYS_EQOS_TOP_IPCLKPORT_I_RGMII_TXCLK_2P5	35
+#define CLK_GOUT_FSYS_SFMC_IPCLKPORT_I_ACLK_NAND		36
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_SDCLKIN			37
+#define CLK_GOUT_FSYS_MMC0_IPCLKPORT_I_ACLK			38
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_SDCLKIN			39
+#define CLK_GOUT_FSYS_MMC1_IPCLKPORT_I_ACLK			40
+#define CLK_GOUT_FSYS_PCIE_PHY_REFCLK_IN			41
+#define CLK_GOUT_FSYS_UART0_PCLK				42
+#define CLK_GOUT_FSYS_UART0_SCLK_UART				43
+#define CLK_GOUT_FSYS_BUS_QSPI					44
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_HCLK			45
+#define CLK_GOUT_FSYS_QSPI_IPCLKPORT_SSI_CLK			46
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER					1
+#define CLK_MOUT_IMEM_GIC_CA53					2
+#define CLK_MOUT_IMEM_GIC_CA5					3
+#define CLK_MOUT_IMEM_JPEG_USER					4
+#define CLK_GOUT_IMEM_MCT_PCLK					5
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF				6
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER					1
+#define CLK_MOUT_PERI_AUDIO_USER				2
+#define CLK_MOUT_PERI_I2S0					3
+#define CLK_MOUT_PERI_I2S1					4
+#define CLK_MOUT_PERI_DISP_USER					5
+#define CLK_DOUT_PERI_SPI					6
+#define CLK_DOUT_PERI_UART1					7
+#define CLK_DOUT_PERI_UART2					8
+#define CLK_DOUT_PERI_PCLK					9
+#define CLK_DOUT_PERI_I2S0					10
+#define CLK_DOUT_PERI_I2S1					11
+#define CLK_DOUT_PERI_DSIM					12
+#define CLK_GOUT_PERI_UART1_PCLK				13
+#define CLK_GOUT_PERI_UART1_SCLK_UART				14
+#define CLK_GOUT_PERI_UART2_PCLK				15
+#define CLK_GOUT_PERI_UART2_SCLK_UART				16
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK			17
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK			18
+#define CLK_GOUT_PERI_SPI0_PCLK					19
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI				20
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS		21
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK_HST			22
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK_HST			23
+#define CLK_GOUT_PERI_AUDIO_OUT_IPCLKPORT_CLK			24
+#define CLK_GOUT_PERI_I2SSC0_IPCLKPORT_CLK			25
+#define CLK_GOUT_PERI_I2SSC1_IPCLKPORT_CLK			26
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK		27
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK		28
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */
diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h
index 3f7b64d9355..58fdec8f4c2 100644
--- a/include/dt-bindings/clock/fsd-clk.h
+++ b/include/dt-bindings/clock/fsd-clk.h
@@ -139,5 +139,18 @@
 #define CAM_CSI2_1_IPCLKPORT_I_ACLK		10
 #define CAM_CSI2_2_IPCLKPORT_I_ACLK		11
 #define CAM_CSI2_3_IPCLKPORT_I_ACLK		12
+#define CAM_CSI_PLL				13
+#define CAM_CSI0_0_IPCLKPORT_I_PCLK		14
+#define CAM_CSI0_1_IPCLKPORT_I_PCLK		15
+#define CAM_CSI0_2_IPCLKPORT_I_PCLK		16
+#define CAM_CSI0_3_IPCLKPORT_I_PCLK		17
+#define CAM_CSI1_0_IPCLKPORT_I_PCLK		18
+#define CAM_CSI1_1_IPCLKPORT_I_PCLK		19
+#define CAM_CSI1_2_IPCLKPORT_I_PCLK		20
+#define CAM_CSI1_3_IPCLKPORT_I_PCLK		21
+#define CAM_CSI2_0_IPCLKPORT_I_PCLK		22
+#define CAM_CSI2_1_IPCLKPORT_I_PCLK		23
+#define CAM_CSI2_2_IPCLKPORT_I_PCLK		24
+#define CAM_CSI2_3_IPCLKPORT_I_PCLK		25
 
 #endif /*_DT_BINDINGS_CLOCK_FSD_H */
diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h
index 4279ba595f1..8cbb86b2cf1 100644
--- a/include/dt-bindings/clock/loongson,ls2k-clk.h
+++ b/include/dt-bindings/clock/loongson,ls2k-clk.h
@@ -43,4 +43,40 @@
 #define LOONGSON2_I2S_CLK	33
 #define LOONGSON2_MISC_CLK	34
 
+#define LS2K0300_CLK_STABLE		0
+#define LS2K0300_NODE_PLL		1
+#define LS2K0300_DDR_PLL		2
+#define LS2K0300_PIX_PLL		3
+#define LS2K0300_CLK_THSENS		4
+#define LS2K0300_CLK_NODE_DIV		5
+#define LS2K0300_CLK_NODE_PLL_GATE	6
+#define LS2K0300_CLK_NODE_SCALE		7
+#define LS2K0300_CLK_NODE_GATE		8
+#define LS2K0300_CLK_GMAC_DIV		9
+#define LS2K0300_CLK_GMAC_GATE		10
+#define LS2K0300_CLK_I2S_DIV		11
+#define LS2K0300_CLK_I2S_SCALE		12
+#define LS2K0300_CLK_I2S_GATE		13
+#define LS2K0300_CLK_DDR_DIV		14
+#define LS2K0300_CLK_DDR_GATE		15
+#define LS2K0300_CLK_NET_DIV		16
+#define LS2K0300_CLK_NET_GATE		17
+#define LS2K0300_CLK_DEV_DIV		18
+#define LS2K0300_CLK_DEV_GATE		19
+#define LS2K0300_CLK_PIX_DIV		20
+#define LS2K0300_CLK_PIX_PLL_GATE	21
+#define LS2K0300_CLK_PIX_SCALE		22
+#define LS2K0300_CLK_PIX_GATE		23
+#define LS2K0300_CLK_GMACBP_DIV		24
+#define LS2K0300_CLK_GMACBP_GATE	25
+#define LS2K0300_CLK_USB_SCALE		26
+#define LS2K0300_CLK_USB_GATE		27
+#define LS2K0300_CLK_APB_SCALE		28
+#define LS2K0300_CLK_APB_GATE		29
+#define LS2K0300_CLK_BOOT_SCALE		30
+#define LS2K0300_CLK_BOOT_GATE		31
+#define LS2K0300_CLK_SDIO_SCALE		32
+#define LS2K0300_CLK_SDIO_GATE		33
+#define LS2K0300_CLK_GMAC_IN		34
+
 #endif
diff --git a/include/dt-bindings/clock/mediatek,mt8196-clock.h b/include/dt-bindings/clock/mediatek,mt8196-clock.h
new file mode 100644
index 00000000000..ae0946ab762
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt8196-clock.h
@@ -0,0 +1,803 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ *                    Guangjie Song <[email protected]>
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    Laura Nao <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8196_H
+#define _DT_BINDINGS_CLK_MT8196_H
+
+/* CKSYS */
+#define CLK_TOP_AXI					0
+#define CLK_TOP_MEM_SUB					1
+#define CLK_TOP_IO_NOC					2
+#define CLK_TOP_P_AXI					3
+#define CLK_TOP_UFS_PEXTP0_AXI				4
+#define CLK_TOP_PEXTP1_USB_AXI				5
+#define CLK_TOP_P_FMEM_SUB				6
+#define CLK_TOP_PEXPT0_MEM_SUB				7
+#define CLK_TOP_PEXTP1_USB_MEM_SUB			8
+#define CLK_TOP_P_NOC					9
+#define CLK_TOP_EMI_N					10
+#define CLK_TOP_EMI_S					11
+#define CLK_TOP_AP2CONN_HOST				12
+#define CLK_TOP_ATB					13
+#define CLK_TOP_CIRQ					14
+#define CLK_TOP_PBUS_156M				15
+#define CLK_TOP_EFUSE					16
+#define CLK_TOP_MCL3GIC					17
+#define CLK_TOP_MCINFRA					18
+#define CLK_TOP_DSP					19
+#define CLK_TOP_MFG_REF					20
+#define CLK_TOP_MFG_EB					21
+#define CLK_TOP_UART					22
+#define CLK_TOP_SPI0_BCLK				23
+#define CLK_TOP_SPI1_BCLK				24
+#define CLK_TOP_SPI2_BCLK				25
+#define CLK_TOP_SPI3_BCLK				26
+#define CLK_TOP_SPI4_BCLK				27
+#define CLK_TOP_SPI5_BCLK				28
+#define CLK_TOP_SPI6_BCLK				29
+#define CLK_TOP_SPI7_BCLK				30
+#define CLK_TOP_MSDC30_1				31
+#define CLK_TOP_MSDC30_2				32
+#define CLK_TOP_DISP_PWM				33
+#define CLK_TOP_USB_TOP_1P				34
+#define CLK_TOP_USB_XHCI_1P				35
+#define CLK_TOP_USB_FMCNT_P1				36
+#define CLK_TOP_I2C_P					37
+#define CLK_TOP_I2C_EAST				38
+#define CLK_TOP_I2C_WEST				39
+#define CLK_TOP_I2C_NORTH				40
+#define CLK_TOP_AES_UFSFDE				41
+#define CLK_TOP_UFS					42
+#define CLK_TOP_AUD_1					43
+#define CLK_TOP_AUD_2					44
+#define CLK_TOP_ADSP					45
+#define CLK_TOP_ADSP_UARTHUB_B				46
+#define CLK_TOP_DPMAIF_MAIN				47
+#define CLK_TOP_PWM					48
+#define CLK_TOP_MCUPM					49
+#define CLK_TOP_IPSEAST					50
+#define CLK_TOP_TL					51
+#define CLK_TOP_TL_P1					52
+#define CLK_TOP_TL_P2					53
+#define CLK_TOP_EMI_INTERFACE_546			54
+#define CLK_TOP_SDF					55
+#define CLK_TOP_UARTHUB_BCLK				56
+#define CLK_TOP_DPSW_CMP_26M				57
+#define CLK_TOP_SMAP					58
+#define CLK_TOP_SSR_PKA					59
+#define CLK_TOP_SSR_DMA					60
+#define CLK_TOP_SSR_KDF					61
+#define CLK_TOP_SSR_RNG					62
+#define CLK_TOP_SPU0					63
+#define CLK_TOP_SPU1					64
+#define CLK_TOP_DXCC					65
+#define CLK_TOP_APLL_I2SIN0				66
+#define CLK_TOP_APLL_I2SIN1				67
+#define CLK_TOP_APLL_I2SIN2				68
+#define CLK_TOP_APLL_I2SIN3				69
+#define CLK_TOP_APLL_I2SIN4				70
+#define CLK_TOP_APLL_I2SIN6				71
+#define CLK_TOP_APLL_I2SOUT0				72
+#define CLK_TOP_APLL_I2SOUT1				73
+#define CLK_TOP_APLL_I2SOUT2				74
+#define CLK_TOP_APLL_I2SOUT3				75
+#define CLK_TOP_APLL_I2SOUT4				76
+#define CLK_TOP_APLL_I2SOUT6				77
+#define CLK_TOP_APLL_FMI2S				78
+#define CLK_TOP_APLL_TDMOUT				79
+#define CLK_TOP_APLL12_DIV_TDMOUT_M			80
+#define CLK_TOP_APLL12_DIV_TDMOUT_B			81
+#define CLK_TOP_MAINPLL_D3				82
+#define CLK_TOP_MAINPLL_D4				83
+#define CLK_TOP_MAINPLL_D4_D2				84
+#define CLK_TOP_MAINPLL_D4_D4				85
+#define CLK_TOP_MAINPLL_D4_D8				86
+#define CLK_TOP_MAINPLL_D5				87
+#define CLK_TOP_MAINPLL_D5_D2				88
+#define CLK_TOP_MAINPLL_D5_D4				89
+#define CLK_TOP_MAINPLL_D5_D8				90
+#define CLK_TOP_MAINPLL_D6				91
+#define CLK_TOP_MAINPLL_D6_D2				92
+#define CLK_TOP_MAINPLL_D7				93
+#define CLK_TOP_MAINPLL_D7_D2				94
+#define CLK_TOP_MAINPLL_D7_D4				95
+#define CLK_TOP_MAINPLL_D7_D8				96
+#define CLK_TOP_MAINPLL_D9				97
+#define CLK_TOP_UNIVPLL_D4				98
+#define CLK_TOP_UNIVPLL_D4_D2				99
+#define CLK_TOP_UNIVPLL_D4_D4				100
+#define CLK_TOP_UNIVPLL_D4_D8				101
+#define CLK_TOP_UNIVPLL_D5				102
+#define CLK_TOP_UNIVPLL_D5_D2				103
+#define CLK_TOP_UNIVPLL_D5_D4				104
+#define CLK_TOP_UNIVPLL_D6				105
+#define CLK_TOP_UNIVPLL_D6_D2				106
+#define CLK_TOP_UNIVPLL_D6_D4				107
+#define CLK_TOP_UNIVPLL_D6_D8				108
+#define CLK_TOP_UNIVPLL_D6_D16				109
+#define CLK_TOP_UNIVPLL_192M				110
+#define CLK_TOP_UNIVPLL_192M_D4				111
+#define CLK_TOP_UNIVPLL_192M_D8				112
+#define CLK_TOP_UNIVPLL_192M_D16			113
+#define CLK_TOP_UNIVPLL_192M_D32			114
+#define CLK_TOP_UNIVPLL_192M_D10			115
+#define CLK_TOP_TVDPLL1_D2				116
+#define CLK_TOP_MSDCPLL_D2				117
+#define CLK_TOP_OSC_D2					118
+#define CLK_TOP_OSC_D3					119
+#define CLK_TOP_OSC_D4					120
+#define CLK_TOP_OSC_D5					121
+#define CLK_TOP_OSC_D7					122
+#define CLK_TOP_OSC_D8					123
+#define CLK_TOP_OSC_D10					124
+#define CLK_TOP_OSC_D14					125
+#define CLK_TOP_OSC_D20					126
+#define CLK_TOP_OSC_D32					127
+#define CLK_TOP_OSC_D40					128
+#define CLK_TOP_SFLASH					129
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_MAINPLL				0
+#define CLK_APMIXED_UNIVPLL				1
+#define CLK_APMIXED_MSDCPLL				2
+#define CLK_APMIXED_ADSPPLL				3
+#define CLK_APMIXED_EMIPLL				4
+#define CLK_APMIXED_EMIPLL2				5
+#define CLK_APMIXED_NET1PLL				6
+#define CLK_APMIXED_SGMIIPLL				7
+
+/* CKSYS_GP2 */
+#define CLK_TOP2_SENINF0				0
+#define CLK_TOP2_SENINF1				1
+#define CLK_TOP2_SENINF2				2
+#define CLK_TOP2_SENINF3				3
+#define CLK_TOP2_SENINF4				4
+#define CLK_TOP2_SENINF5				5
+#define CLK_TOP2_IMG1					6
+#define CLK_TOP2_IPE					7
+#define CLK_TOP2_CAM					8
+#define CLK_TOP2_CAMTM					9
+#define CLK_TOP2_DPE					10
+#define CLK_TOP2_VDEC					11
+#define CLK_TOP2_CCUSYS					12
+#define CLK_TOP2_CCUTM					13
+#define CLK_TOP2_VENC					14
+#define CLK_TOP2_DP1					15
+#define CLK_TOP2_DP0					16
+#define CLK_TOP2_DISP					17
+#define CLK_TOP2_MDP					18
+#define CLK_TOP2_MMINFRA				19
+#define CLK_TOP2_MMINFRA_SNOC				20
+#define CLK_TOP2_MMUP					21
+#define CLK_TOP2_MMINFRA_AO				22
+#define CLK_TOP2_MAINPLL2_D2				23
+#define CLK_TOP2_MAINPLL2_D3				24
+#define CLK_TOP2_MAINPLL2_D4				25
+#define CLK_TOP2_MAINPLL2_D4_D2				26
+#define CLK_TOP2_MAINPLL2_D4_D4				27
+#define CLK_TOP2_MAINPLL2_D5				28
+#define CLK_TOP2_MAINPLL2_D5_D2				29
+#define CLK_TOP2_MAINPLL2_D6				30
+#define CLK_TOP2_MAINPLL2_D6_D2				31
+#define CLK_TOP2_MAINPLL2_D7				32
+#define CLK_TOP2_MAINPLL2_D7_D2				33
+#define CLK_TOP2_MAINPLL2_D9				34
+#define CLK_TOP2_UNIVPLL2_D3				35
+#define CLK_TOP2_UNIVPLL2_D4				36
+#define CLK_TOP2_UNIVPLL2_D4_D2				37
+#define CLK_TOP2_UNIVPLL2_D5				38
+#define CLK_TOP2_UNIVPLL2_D5_D2				39
+#define CLK_TOP2_UNIVPLL2_D6				40
+#define CLK_TOP2_UNIVPLL2_D6_D2				41
+#define CLK_TOP2_UNIVPLL2_D6_D4				42
+#define CLK_TOP2_UNIVPLL2_D7				43
+#define CLK_TOP2_IMGPLL_D2				44
+#define CLK_TOP2_IMGPLL_D4				45
+#define CLK_TOP2_IMGPLL_D5				46
+#define CLK_TOP2_IMGPLL_D5_D2				47
+#define CLK_TOP2_MMPLL2_D3				48
+#define CLK_TOP2_MMPLL2_D4				49
+#define CLK_TOP2_MMPLL2_D4_D2				50
+#define CLK_TOP2_MMPLL2_D5				51
+#define CLK_TOP2_MMPLL2_D5_D2				52
+#define CLK_TOP2_MMPLL2_D6				53
+#define CLK_TOP2_MMPLL2_D6_D2				54
+#define CLK_TOP2_MMPLL2_D7				55
+#define CLK_TOP2_MMPLL2_D9				56
+#define CLK_TOP2_TVDPLL1_D4				57
+#define CLK_TOP2_TVDPLL1_D8				58
+#define CLK_TOP2_TVDPLL1_D16				59
+#define CLK_TOP2_TVDPLL2_D2				60
+#define CLK_TOP2_TVDPLL2_D4				61
+#define CLK_TOP2_TVDPLL2_D8				62
+#define CLK_TOP2_TVDPLL2_D16				63
+#define CLK_TOP2_DVO					64
+#define CLK_TOP2_DVO_FAVT				65
+#define CLK_TOP2_TVDPLL3_D2				66
+#define CLK_TOP2_TVDPLL3_D4				67
+#define CLK_TOP2_TVDPLL3_D8				68
+#define CLK_TOP2_TVDPLL3_D16				69
+
+/* APMIXEDSYS_GP2 */
+#define CLK_APMIXED2_MAINPLL2				0
+#define CLK_APMIXED2_UNIVPLL2				1
+#define CLK_APMIXED2_MMPLL2				2
+#define CLK_APMIXED2_IMGPLL				3
+#define CLK_APMIXED2_TVDPLL1				4
+#define CLK_APMIXED2_TVDPLL2				5
+#define CLK_APMIXED2_TVDPLL3				6
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_I2C5					0
+
+/* IMP_IIC_WRAP_W */
+#define CLK_IMPW_I2C0					0
+#define CLK_IMPW_I2C3					1
+#define CLK_IMPW_I2C6					2
+#define CLK_IMPW_I2C10					3
+
+/* IMP_IIC_WRAP_N */
+#define CLK_IMPN_I2C1					0
+#define CLK_IMPN_I2C2					1
+#define CLK_IMPN_I2C4					2
+#define CLK_IMPN_I2C7					3
+#define CLK_IMPN_I2C8					4
+#define CLK_IMPN_I2C9					5
+
+/* IMP_IIC_WRAP_C */
+#define CLK_IMPC_I2C11					0
+#define CLK_IMPC_I2C12					1
+#define CLK_IMPC_I2C13					2
+#define CLK_IMPC_I2C14					3
+
+/* PERICFG_AO */
+#define CLK_PERI_AO_UART0_BCLK				0
+#define CLK_PERI_AO_UART1_BCLK				1
+#define CLK_PERI_AO_UART2_BCLK				2
+#define CLK_PERI_AO_UART3_BCLK				3
+#define CLK_PERI_AO_UART4_BCLK				4
+#define CLK_PERI_AO_UART5_BCLK				5
+#define CLK_PERI_AO_PWM_X16W_HCLK			6
+#define CLK_PERI_AO_PWM_X16W_BCLK			7
+#define CLK_PERI_AO_PWM_PWM_BCLK0			8
+#define CLK_PERI_AO_PWM_PWM_BCLK1			9
+#define CLK_PERI_AO_PWM_PWM_BCLK2			10
+#define CLK_PERI_AO_PWM_PWM_BCLK3			11
+#define CLK_PERI_AO_SPI0_BCLK				12
+#define CLK_PERI_AO_SPI1_BCLK				13
+#define CLK_PERI_AO_SPI2_BCLK				14
+#define CLK_PERI_AO_SPI3_BCLK				15
+#define CLK_PERI_AO_SPI4_BCLK				16
+#define CLK_PERI_AO_SPI5_BCLK				17
+#define CLK_PERI_AO_SPI6_BCLK				18
+#define CLK_PERI_AO_SPI7_BCLK				19
+#define CLK_PERI_AO_AP_DMA_X32W_BCLK			20
+#define CLK_PERI_AO_MSDC1_MSDC_SRC			21
+#define CLK_PERI_AO_MSDC1_HCLK				22
+#define CLK_PERI_AO_MSDC1_AXI				23
+#define CLK_PERI_AO_MSDC1_HCLK_WRAP			24
+#define CLK_PERI_AO_MSDC2_MSDC_SRC			25
+#define CLK_PERI_AO_MSDC2_HCLK				26
+#define CLK_PERI_AO_MSDC2_AXI				27
+#define CLK_PERI_AO_MSDC2_HCLK_WRAP			28
+#define CLK_PERI_AO_FLASHIF_FLASH			29
+#define CLK_PERI_AO_FLASHIF_27M				30
+#define CLK_PERI_AO_FLASHIF_DRAM			31
+#define CLK_PERI_AO_FLASHIF_AXI				32
+#define CLK_PERI_AO_FLASHIF_BCLK			33
+
+/* UFSCFG_AO */
+#define CLK_UFSAO_UNIPRO_TX_SYM				0
+#define CLK_UFSAO_UNIPRO_RX_SYM0			1
+#define CLK_UFSAO_UNIPRO_RX_SYM1			2
+#define CLK_UFSAO_UNIPRO_SYS				3
+#define CLK_UFSAO_UNIPRO_SAP				4
+#define CLK_UFSAO_PHY_SAP				5
+#define CLK_UFSAO_UFSHCI_UFS				6
+#define CLK_UFSAO_UFSHCI_AES				7
+
+/* PEXTP0CFG_AO */
+#define CLK_PEXT_PEXTP_MAC_P0_TL			0
+#define CLK_PEXT_PEXTP_MAC_P0_REF			1
+#define CLK_PEXT_PEXTP_PHY_P0_MCU_BUS			2
+#define CLK_PEXT_PEXTP_PHY_P0_PEXTP_REF			3
+#define CLK_PEXT_PEXTP_MAC_P0_AXI_250			4
+#define CLK_PEXT_PEXTP_MAC_P0_AHB_APB			5
+#define CLK_PEXT_PEXTP_MAC_P0_PL_P			6
+#define CLK_PEXT_PEXTP_VLP_AO_P0_LP			7
+
+/* PEXTP1CFG_AO */
+#define CLK_PEXT1_PEXTP_MAC_P1_TL			0
+#define CLK_PEXT1_PEXTP_MAC_P1_REF			1
+#define CLK_PEXT1_PEXTP_MAC_P2_TL			2
+#define CLK_PEXT1_PEXTP_MAC_P2_REF			3
+#define CLK_PEXT1_PEXTP_PHY_P1_MCU_BUS			4
+#define CLK_PEXT1_PEXTP_PHY_P1_PEXTP_REF		5
+#define CLK_PEXT1_PEXTP_PHY_P2_MCU_BUS			6
+#define CLK_PEXT1_PEXTP_PHY_P2_PEXTP_REF		7
+#define CLK_PEXT1_PEXTP_MAC_P1_AXI_250			8
+#define CLK_PEXT1_PEXTP_MAC_P1_AHB_APB			9
+#define CLK_PEXT1_PEXTP_MAC_P1_PL_P			10
+#define CLK_PEXT1_PEXTP_MAC_P2_AXI_250			11
+#define CLK_PEXT1_PEXTP_MAC_P2_AHB_APB			12
+#define CLK_PEXT1_PEXTP_MAC_P2_PL_P			13
+#define CLK_PEXT1_PEXTP_VLP_AO_P1_LP			14
+#define CLK_PEXT1_PEXTP_VLP_AO_P2_LP			15
+
+/* VLP_CKSYS */
+#define CLK_VLP_APLL1					0
+#define CLK_VLP_APLL2					1
+#define CLK_VLP_SCP					2
+#define CLK_VLP_SCP_SPI					3
+#define CLK_VLP_SCP_IIC					4
+#define CLK_VLP_SCP_IIC_HS				5
+#define CLK_VLP_PWRAP_ULPOSC				6
+#define CLK_VLP_SPMI_M_TIA_32K				7
+#define CLK_VLP_APXGPT_26M_B				8
+#define CLK_VLP_DPSW					9
+#define CLK_VLP_DPSW_CENTRAL				10
+#define CLK_VLP_SPMI_M_MST				11
+#define CLK_VLP_DVFSRC					12
+#define CLK_VLP_PWM_VLP					13
+#define CLK_VLP_AXI_VLP					14
+#define CLK_VLP_SYSTIMER_26M				15
+#define CLK_VLP_SSPM					16
+#define CLK_VLP_SRCK					17
+#define CLK_VLP_CAMTG0					18
+#define CLK_VLP_CAMTG1					19
+#define CLK_VLP_CAMTG2					20
+#define CLK_VLP_CAMTG3					21
+#define CLK_VLP_CAMTG4					22
+#define CLK_VLP_CAMTG5					23
+#define CLK_VLP_CAMTG6					24
+#define CLK_VLP_CAMTG7					25
+#define CLK_VLP_SSPM_26M				26
+#define CLK_VLP_ULPOSC_SSPM				27
+#define CLK_VLP_VLP_PBUS_26M				28
+#define CLK_VLP_DEBUG_ERR_FLAG				29
+#define CLK_VLP_DPMSRDMA				30
+#define CLK_VLP_VLP_PBUS_156M				31
+#define CLK_VLP_SPM					32
+#define CLK_VLP_MMINFRA					33
+#define CLK_VLP_USB_TOP					34
+#define CLK_VLP_USB_XHCI				35
+#define CLK_VLP_NOC_VLP					36
+#define CLK_VLP_AUDIO_H					37
+#define CLK_VLP_AUD_ENGEN1				38
+#define CLK_VLP_AUD_ENGEN2				39
+#define CLK_VLP_AUD_INTBUS				40
+#define CLK_VLP_SPVLP_26M				41
+#define CLK_VLP_SPU0_VLP				42
+#define CLK_VLP_SPU1_VLP				43
+#define CLK_VLP_CLK26M                                  44
+#define CLK_VLP_APLL1_D4				45
+#define CLK_VLP_APLL1_D8				46
+#define CLK_VLP_APLL2_D4				47
+#define CLK_VLP_APLL2_D8				48
+
+/* DISPSYS_CONFIG */
+#define CLK_MM_CONFIG					0
+#define CLK_MM_DISP_MUTEX0				1
+#define CLK_MM_DISP_AAL0				2
+#define CLK_MM_DISP_AAL1				3
+#define CLK_MM_DISP_C3D0				4
+#define CLK_MM_DISP_C3D1				5
+#define CLK_MM_DISP_C3D2				6
+#define CLK_MM_DISP_C3D3				7
+#define CLK_MM_DISP_CCORR0				8
+#define CLK_MM_DISP_CCORR1				9
+#define CLK_MM_DISP_CCORR2				10
+#define CLK_MM_DISP_CCORR3				11
+#define CLK_MM_DISP_CHIST0				12
+#define CLK_MM_DISP_CHIST1				13
+#define CLK_MM_DISP_COLOR0				14
+#define CLK_MM_DISP_COLOR1				15
+#define CLK_MM_DISP_DITHER0				16
+#define CLK_MM_DISP_DITHER1				17
+#define CLK_MM_DISP_DLI_ASYNC0				18
+#define CLK_MM_DISP_DLI_ASYNC1				19
+#define CLK_MM_DISP_DLI_ASYNC2				20
+#define CLK_MM_DISP_DLI_ASYNC3				21
+#define CLK_MM_DISP_DLI_ASYNC4				22
+#define CLK_MM_DISP_DLI_ASYNC5				23
+#define CLK_MM_DISP_DLI_ASYNC6				24
+#define CLK_MM_DISP_DLI_ASYNC7				25
+#define CLK_MM_DISP_DLI_ASYNC8				26
+#define CLK_MM_DISP_DLI_ASYNC9				27
+#define CLK_MM_DISP_DLI_ASYNC10				28
+#define CLK_MM_DISP_DLI_ASYNC11				29
+#define CLK_MM_DISP_DLI_ASYNC12				30
+#define CLK_MM_DISP_DLI_ASYNC13				31
+#define CLK_MM_DISP_DLI_ASYNC14				32
+#define CLK_MM_DISP_DLI_ASYNC15				33
+#define CLK_MM_DISP_DLO_ASYNC0				34
+#define CLK_MM_DISP_DLO_ASYNC1				35
+#define CLK_MM_DISP_DLO_ASYNC2				36
+#define CLK_MM_DISP_DLO_ASYNC3				37
+#define CLK_MM_DISP_DLO_ASYNC4				38
+#define CLK_MM_DISP_DLO_ASYNC5				39
+#define CLK_MM_DISP_DLO_ASYNC6				40
+#define CLK_MM_DISP_DLO_ASYNC7				41
+#define CLK_MM_DISP_DLO_ASYNC8				42
+#define CLK_MM_DISP_GAMMA0				43
+#define CLK_MM_DISP_GAMMA1				44
+#define CLK_MM_MDP_AAL0					45
+#define CLK_MM_MDP_AAL1					46
+#define CLK_MM_MDP_RDMA0				47
+#define CLK_MM_DISP_POSTMASK0				48
+#define CLK_MM_DISP_POSTMASK1				49
+#define CLK_MM_MDP_RSZ0					50
+#define CLK_MM_MDP_RSZ1					51
+#define CLK_MM_DISP_SPR0				52
+#define CLK_MM_DISP_TDSHP0				53
+#define CLK_MM_DISP_TDSHP1				54
+#define CLK_MM_DISP_WDMA0				55
+#define CLK_MM_DISP_Y2R0				56
+#define CLK_MM_SMI_SUB_COMM0				57
+#define CLK_MM_DISP_FAKE_ENG0				58
+
+/* DISPSYS1_CONFIG */
+#define CLK_MM1_DISPSYS1_CONFIG				0
+#define CLK_MM1_DISPSYS1_S_CONFIG			1
+#define CLK_MM1_DISP_MUTEX0				2
+#define CLK_MM1_DISP_DLI_ASYNC20			3
+#define CLK_MM1_DISP_DLI_ASYNC21			4
+#define CLK_MM1_DISP_DLI_ASYNC22			5
+#define CLK_MM1_DISP_DLI_ASYNC23			6
+#define CLK_MM1_DISP_DLI_ASYNC24			7
+#define CLK_MM1_DISP_DLI_ASYNC25			8
+#define CLK_MM1_DISP_DLI_ASYNC26			9
+#define CLK_MM1_DISP_DLI_ASYNC27			10
+#define CLK_MM1_DISP_DLI_ASYNC28			11
+#define CLK_MM1_DISP_RELAY0				12
+#define CLK_MM1_DISP_RELAY1				13
+#define CLK_MM1_DISP_RELAY2				14
+#define CLK_MM1_DISP_RELAY3				15
+#define CLK_MM1_DISP_DP_INTF0				16
+#define CLK_MM1_DISP_DP_INTF1				17
+#define CLK_MM1_DISP_DSC_WRAP0				18
+#define CLK_MM1_DISP_DSC_WRAP1				19
+#define CLK_MM1_DISP_DSC_WRAP2				20
+#define CLK_MM1_DISP_DSC_WRAP3				21
+#define CLK_MM1_DISP_DSI0				22
+#define CLK_MM1_DISP_DSI1				23
+#define CLK_MM1_DISP_DSI2				24
+#define CLK_MM1_DISP_DVO0				25
+#define CLK_MM1_DISP_GDMA0				26
+#define CLK_MM1_DISP_MERGE0				27
+#define CLK_MM1_DISP_MERGE1				28
+#define CLK_MM1_DISP_MERGE2				29
+#define CLK_MM1_DISP_ODDMR0				30
+#define CLK_MM1_DISP_POSTALIGN0				31
+#define CLK_MM1_DISP_DITHER2				32
+#define CLK_MM1_DISP_R2Y0				33
+#define CLK_MM1_DISP_SPLITTER0				34
+#define CLK_MM1_DISP_SPLITTER1				35
+#define CLK_MM1_DISP_SPLITTER2				36
+#define CLK_MM1_DISP_SPLITTER3				37
+#define CLK_MM1_DISP_VDCM0				38
+#define CLK_MM1_DISP_WDMA1				39
+#define CLK_MM1_DISP_WDMA2				40
+#define CLK_MM1_DISP_WDMA3				41
+#define CLK_MM1_DISP_WDMA4				42
+#define CLK_MM1_MDP_RDMA1				43
+#define CLK_MM1_SMI_LARB0				44
+#define CLK_MM1_MOD1					45
+#define CLK_MM1_MOD2					46
+#define CLK_MM1_MOD3					47
+#define CLK_MM1_MOD4					48
+#define CLK_MM1_MOD5					49
+#define CLK_MM1_MOD6					50
+#define CLK_MM1_CG0					51
+#define CLK_MM1_CG1					52
+#define CLK_MM1_CG2					53
+#define CLK_MM1_CG3					54
+#define CLK_MM1_CG4					55
+#define CLK_MM1_CG5					56
+#define CLK_MM1_CG6					57
+#define CLK_MM1_CG7					58
+#define CLK_MM1_F26M					59
+
+/* OVLSYS_CONFIG */
+#define CLK_OVLSYS_CONFIG				0
+#define CLK_OVL_FAKE_ENG0				1
+#define CLK_OVL_FAKE_ENG1				2
+#define CLK_OVL_MUTEX0					3
+#define CLK_OVL_EXDMA0					4
+#define CLK_OVL_EXDMA1					5
+#define CLK_OVL_EXDMA2					6
+#define CLK_OVL_EXDMA3					7
+#define CLK_OVL_EXDMA4					8
+#define CLK_OVL_EXDMA5					9
+#define CLK_OVL_EXDMA6					10
+#define CLK_OVL_EXDMA7					11
+#define CLK_OVL_EXDMA8					12
+#define CLK_OVL_EXDMA9					13
+#define CLK_OVL_BLENDER0				14
+#define CLK_OVL_BLENDER1				15
+#define CLK_OVL_BLENDER2				16
+#define CLK_OVL_BLENDER3				17
+#define CLK_OVL_BLENDER4				18
+#define CLK_OVL_BLENDER5				19
+#define CLK_OVL_BLENDER6				20
+#define CLK_OVL_BLENDER7				21
+#define CLK_OVL_BLENDER8				22
+#define CLK_OVL_BLENDER9				23
+#define CLK_OVL_OUTPROC0				24
+#define CLK_OVL_OUTPROC1				25
+#define CLK_OVL_OUTPROC2				26
+#define CLK_OVL_OUTPROC3				27
+#define CLK_OVL_OUTPROC4				28
+#define CLK_OVL_OUTPROC5				29
+#define CLK_OVL_MDP_RSZ0				30
+#define CLK_OVL_MDP_RSZ1				31
+#define CLK_OVL_DISP_WDMA0				32
+#define CLK_OVL_DISP_WDMA1				33
+#define CLK_OVL_UFBC_WDMA0				34
+#define CLK_OVL_MDP_RDMA0				35
+#define CLK_OVL_MDP_RDMA1				36
+#define CLK_OVL_BWM0					37
+#define CLK_OVL_DLI0					38
+#define CLK_OVL_DLI1					39
+#define CLK_OVL_DLI2					40
+#define CLK_OVL_DLI3					41
+#define CLK_OVL_DLI4					42
+#define CLK_OVL_DLI5					43
+#define CLK_OVL_DLI6					44
+#define CLK_OVL_DLI7					45
+#define CLK_OVL_DLI8					46
+#define CLK_OVL_DLO0					47
+#define CLK_OVL_DLO1					48
+#define CLK_OVL_DLO2					49
+#define CLK_OVL_DLO3					50
+#define CLK_OVL_DLO4					51
+#define CLK_OVL_DLO5					52
+#define CLK_OVL_DLO6					53
+#define CLK_OVL_DLO7					54
+#define CLK_OVL_DLO8					55
+#define CLK_OVL_DLO9					56
+#define CLK_OVL_DLO10					57
+#define CLK_OVL_DLO11					58
+#define CLK_OVL_DLO12					59
+#define CLK_OVLSYS_RELAY0				60
+#define CLK_OVL_INLINEROT0				61
+#define CLK_OVL_SMI					62
+#define CLK_OVL_SMI_SMI					63
+
+
+/* OVLSYS1_CONFIG */
+#define CLK_OVL1_OVLSYS_CONFIG				0
+#define CLK_OVL1_OVL_FAKE_ENG0				1
+#define CLK_OVL1_OVL_FAKE_ENG1				2
+#define CLK_OVL1_OVL_MUTEX0				3
+#define CLK_OVL1_OVL_EXDMA0				4
+#define CLK_OVL1_OVL_EXDMA1				5
+#define CLK_OVL1_OVL_EXDMA2				6
+#define CLK_OVL1_OVL_EXDMA3				7
+#define CLK_OVL1_OVL_EXDMA4				8
+#define CLK_OVL1_OVL_EXDMA5				9
+#define CLK_OVL1_OVL_EXDMA6				10
+#define CLK_OVL1_OVL_EXDMA7				11
+#define CLK_OVL1_OVL_EXDMA8				12
+#define CLK_OVL1_OVL_EXDMA9				13
+#define CLK_OVL1_OVL_BLENDER0				14
+#define CLK_OVL1_OVL_BLENDER1				15
+#define CLK_OVL1_OVL_BLENDER2				16
+#define CLK_OVL1_OVL_BLENDER3				17
+#define CLK_OVL1_OVL_BLENDER4				18
+#define CLK_OVL1_OVL_BLENDER5				19
+#define CLK_OVL1_OVL_BLENDER6				20
+#define CLK_OVL1_OVL_BLENDER7				21
+#define CLK_OVL1_OVL_BLENDER8				22
+#define CLK_OVL1_OVL_BLENDER9				23
+#define CLK_OVL1_OVL_OUTPROC0				24
+#define CLK_OVL1_OVL_OUTPROC1				25
+#define CLK_OVL1_OVL_OUTPROC2				26
+#define CLK_OVL1_OVL_OUTPROC3				27
+#define CLK_OVL1_OVL_OUTPROC4				28
+#define CLK_OVL1_OVL_OUTPROC5				29
+#define CLK_OVL1_OVL_MDP_RSZ0				30
+#define CLK_OVL1_OVL_MDP_RSZ1				31
+#define CLK_OVL1_OVL_DISP_WDMA0				32
+#define CLK_OVL1_OVL_DISP_WDMA1				33
+#define CLK_OVL1_OVL_UFBC_WDMA0				34
+#define CLK_OVL1_OVL_MDP_RDMA0				35
+#define CLK_OVL1_OVL_MDP_RDMA1				36
+#define CLK_OVL1_OVL_BWM0				37
+#define CLK_OVL1_DLI0					38
+#define CLK_OVL1_DLI1					39
+#define CLK_OVL1_DLI2					40
+#define CLK_OVL1_DLI3					41
+#define CLK_OVL1_DLI4					42
+#define CLK_OVL1_DLI5					43
+#define CLK_OVL1_DLI6					44
+#define CLK_OVL1_DLI7					45
+#define CLK_OVL1_DLI8					46
+#define CLK_OVL1_DLO0					47
+#define CLK_OVL1_DLO1					48
+#define CLK_OVL1_DLO2					49
+#define CLK_OVL1_DLO3					50
+#define CLK_OVL1_DLO4					51
+#define CLK_OVL1_DLO5					52
+#define CLK_OVL1_DLO6					53
+#define CLK_OVL1_DLO7					54
+#define CLK_OVL1_DLO8					55
+#define CLK_OVL1_DLO9					56
+#define CLK_OVL1_DLO10					57
+#define CLK_OVL1_DLO11					58
+#define CLK_OVL1_DLO12					59
+#define CLK_OVL1_OVLSYS_RELAY0				60
+#define CLK_OVL1_OVL_INLINEROT0				61
+#define CLK_OVL1_SMI					62
+
+
+/* VDEC_SOC_GCON_BASE */
+#define CLK_VDE1_LARB1_CKEN				0
+#define CLK_VDE1_LAT_CKEN				1
+#define CLK_VDE1_LAT_ACTIVE				2
+#define CLK_VDE1_LAT_CKEN_ENG				3
+#define CLK_VDE1_VDEC_CKEN				4
+#define CLK_VDE1_VDEC_ACTIVE				5
+#define CLK_VDE1_VDEC_CKEN_ENG				6
+#define CLK_VDE1_VDEC_SOC_APTV_EN			7
+#define CLK_VDE1_VDEC_SOC_APTV_TOP_EN			8
+#define CLK_VDE1_VDEC_SOC_IPS_EN			9
+
+/* VDEC_GCON_BASE */
+#define CLK_VDE2_LARB1_CKEN				0
+#define CLK_VDE2_LAT_CKEN				1
+#define CLK_VDE2_LAT_ACTIVE				2
+#define CLK_VDE2_LAT_CKEN_ENG				3
+#define CLK_VDE2_VDEC_CKEN				4
+#define CLK_VDE2_VDEC_ACTIVE				5
+#define CLK_VDE2_VDEC_CKEN_ENG				6
+
+/* VENC_GCON */
+#define CLK_VEN1_CKE0_LARB				0
+#define CLK_VEN1_CKE1_VENC				1
+#define CLK_VEN1_CKE2_JPGENC				2
+#define CLK_VEN1_CKE3_JPGDEC				3
+#define CLK_VEN1_CKE4_JPGDEC_C1				4
+#define CLK_VEN1_CKE5_GALS				5
+#define CLK_VEN1_CKE29_VENC_ADAB_CTRL			6
+#define CLK_VEN1_CKE29_VENC_XPC_CTRL			7
+#define CLK_VEN1_CKE6_GALS_SRAM				8
+#define CLK_VEN1_RES_FLAT				9
+
+/* VENC_GCON_CORE1 */
+#define CLK_VEN2_CKE0_LARB				0
+#define CLK_VEN2_CKE1_VENC				1
+#define CLK_VEN2_CKE2_JPGENC				2
+#define CLK_VEN2_CKE3_JPGDEC				3
+#define CLK_VEN2_CKE5_GALS				4
+#define CLK_VEN2_CKE29_VENC_XPC_CTRL			5
+#define CLK_VEN2_CKE6_GALS_SRAM				6
+#define CLK_VEN2_RES_FLAT				7
+
+/* VENC_GCON_CORE2 */
+#define CLK_VEN_C2_CKE0_LARB				0
+#define CLK_VEN_C2_CKE1_VENC				1
+#define CLK_VEN_C2_CKE5_GALS				2
+#define CLK_VEN_C2_CKE29_VENC_XPC_CTRL			3
+#define CLK_VEN_C2_CKE6_GALS_SRAM			4
+#define CLK_VEN_C2_RES_FLAT				5
+
+/* MDPSYS_CONFIG */
+#define CLK_MDP_MDP_MUTEX0				0
+#define CLK_MDP_SMI0					1
+#define CLK_MDP_SMI0_SMI				2
+#define CLK_MDP_APB_BUS					3
+#define CLK_MDP_MDP_RDMA0				4
+#define CLK_MDP_MDP_RDMA1				5
+#define CLK_MDP_MDP_RDMA2				6
+#define CLK_MDP_MDP_BIRSZ0				7
+#define CLK_MDP_MDP_HDR0				8
+#define CLK_MDP_MDP_AAL0				9
+#define CLK_MDP_MDP_RSZ0				10
+#define CLK_MDP_MDP_RSZ2				11
+#define CLK_MDP_MDP_TDSHP0				12
+#define CLK_MDP_MDP_COLOR0				13
+#define CLK_MDP_MDP_WROT0				14
+#define CLK_MDP_MDP_WROT1				15
+#define CLK_MDP_MDP_WROT2				16
+#define CLK_MDP_MDP_FAKE_ENG0				17
+#define CLK_MDP_APB_DB					18
+#define CLK_MDP_MDP_DLI_ASYNC0				19
+#define CLK_MDP_MDP_DLI_ASYNC1				20
+#define CLK_MDP_MDP_DLO_ASYNC0				21
+#define CLK_MDP_MDP_DLO_ASYNC1				22
+#define CLK_MDP_MDP_DLI_ASYNC2				23
+#define CLK_MDP_MDP_DLO_ASYNC2				24
+#define CLK_MDP_MDP_DLO_ASYNC3				25
+#define CLK_MDP_IMG_DL_ASYNC0				26
+#define CLK_MDP_MDP_RROT0				27
+#define CLK_MDP_MDP_MERGE0				28
+#define CLK_MDP_MDP_C3D0				29
+#define CLK_MDP_MDP_FG0					30
+#define CLK_MDP_MDP_CLA2				31
+#define CLK_MDP_MDP_DLO_ASYNC4				32
+#define CLK_MDP_VPP_RSZ0				33
+#define CLK_MDP_VPP_RSZ1				34
+#define CLK_MDP_MDP_DLO_ASYNC5				35
+#define CLK_MDP_IMG0					36
+#define CLK_MDP_F26M					37
+#define CLK_MDP_IMG_DL_RELAY0				38
+#define CLK_MDP_IMG_DL_RELAY1				39
+
+/* MDPSYS1_CONFIG */
+#define CLK_MDP1_MDP_MUTEX0				0
+#define CLK_MDP1_SMI0					1
+#define CLK_MDP1_SMI0_SMI				2
+#define CLK_MDP1_APB_BUS				3
+#define CLK_MDP1_MDP_RDMA0				4
+#define CLK_MDP1_MDP_RDMA1				5
+#define CLK_MDP1_MDP_RDMA2				6
+#define CLK_MDP1_MDP_BIRSZ0				7
+#define CLK_MDP1_MDP_HDR0				8
+#define CLK_MDP1_MDP_AAL0				9
+#define CLK_MDP1_MDP_RSZ0				10
+#define CLK_MDP1_MDP_RSZ2				11
+#define CLK_MDP1_MDP_TDSHP0				12
+#define CLK_MDP1_MDP_COLOR0				13
+#define CLK_MDP1_MDP_WROT0				14
+#define CLK_MDP1_MDP_WROT1				15
+#define CLK_MDP1_MDP_WROT2				16
+#define CLK_MDP1_MDP_FAKE_ENG0				17
+#define CLK_MDP1_APB_DB					18
+#define CLK_MDP1_MDP_DLI_ASYNC0				19
+#define CLK_MDP1_MDP_DLI_ASYNC1				20
+#define CLK_MDP1_MDP_DLO_ASYNC0				21
+#define CLK_MDP1_MDP_DLO_ASYNC1				22
+#define CLK_MDP1_MDP_DLI_ASYNC2				23
+#define CLK_MDP1_MDP_DLO_ASYNC2				24
+#define CLK_MDP1_MDP_DLO_ASYNC3				25
+#define CLK_MDP1_IMG_DL_ASYNC0				26
+#define CLK_MDP1_MDP_RROT0				27
+#define CLK_MDP1_MDP_MERGE0				28
+#define CLK_MDP1_MDP_C3D0				29
+#define CLK_MDP1_MDP_FG0				30
+#define CLK_MDP1_MDP_CLA2				31
+#define CLK_MDP1_MDP_DLO_ASYNC4				32
+#define CLK_MDP1_VPP_RSZ0				33
+#define CLK_MDP1_VPP_RSZ1				34
+#define CLK_MDP1_MDP_DLO_ASYNC5				35
+#define CLK_MDP1_IMG0					36
+#define CLK_MDP1_F26M					37
+#define CLK_MDP1_IMG_DL_RELAY0				38
+#define CLK_MDP1_IMG_DL_RELAY1				39
+
+/* DISP_VDISP_AO_CONFIG */
+#define CLK_MM_V_DISP_VDISP_AO_CONFIG			0
+#define CLK_MM_V_DISP_DPC				1
+#define CLK_MM_V_SMI_SUB_SOMM0				2
+
+/* MFGPLL_PLL_CTRL */
+#define CLK_MFG_AO_MFGPLL				0
+
+/* MFGPLL_SC0_PLL_CTRL */
+#define CLK_MFGSC0_AO_MFGPLL_SC0			0
+
+/* MFGPLL_SC1_PLL_CTRL */
+#define CLK_MFGSC1_AO_MFGPLL_SC1			0
+
+/* CCIPLL_PLL_CTRL */
+#define CLK_CCIPLL					0
+
+/* ARMPLL_LL_PLL_CTRL */
+#define CLK_CPLL_ARMPLL_LL				0
+
+/* ARMPLL_BL_PLL_CTRL */
+#define CLK_CPBL_ARMPLL_BL				0
+
+/* ARMPLL_B_PLL_CTRL */
+#define CLK_CPB_ARMPLL_B				0
+
+/* PTPPLL_PLL_CTRL */
+#define CLK_PTPPLL					0
+
+#endif /* _DT_BINDINGS_CLK_MT8196_H */
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index c12e7eab078..a173eb13289 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -228,7 +228,7 @@
 #define CLK_AUDIO_MEM_ASRC4		44
 #define CLK_AUDIO_MEM_ASRC5		45
 #define CLK_AUDIO_AFE_CONN		46
-#define CLK_AUDIO_NR_CLK		47
+#define CLK_AUDIO_AFE_MRGIF		47
 
 /* SSUSBSYS */
 
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
index 77b6e05492e..0bb41e5efde 100644
--- a/include/dt-bindings/clock/qcom,apss-ipq.h
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -8,5 +8,11 @@
 
 #define APCS_ALIAS0_CLK_SRC			0
 #define APCS_ALIAS0_CORE_CLK			1
+#define APSS_PLL_EARLY				2
+#define APSS_SILVER_CLK_SRC			3
+#define APSS_SILVER_CORE_CLK			4
+#define L3_PLL					5
+#define L3_CLK_SRC				6
+#define L3_CORE_CLK				7
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
index a4a692c20ac..9f113f346be 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
@@ -52,4 +52,8 @@
 /* DISP_CC power domains */
 #define DISP_CC_MDSS_CORE_GDSC				0
 
+/* DISPCC resets */
+#define DISP_CC_MDSS_CORE_BCR				0
+#define DISP_CC_MDSS_RSCC_BCR				1
+
 #endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h
index 4b421e7414b..4e3897b3669 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8917.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -170,6 +170,23 @@
 #define VFE1_CLK_SRC				163
 #define VSYNC_CLK_SRC				164
 #define GPLL0_SLEEP_CLK_SRC			165
+/* Addtional MSM8937-specific clocks */
+#define MSM8937_BLSP1_QUP1_I2C_APPS_CLK_SRC		166
+#define MSM8937_BLSP1_QUP1_SPI_APPS_CLK_SRC		167
+#define MSM8937_BLSP2_QUP4_I2C_APPS_CLK_SRC		168
+#define MSM8937_BLSP2_QUP4_SPI_APPS_CLK_SRC		169
+#define MSM8937_BYTE1_CLK_SRC				170
+#define MSM8937_ESC1_CLK_SRC				171
+#define MSM8937_PCLK1_CLK_SRC				172
+#define MSM8937_GCC_BLSP1_QUP1_I2C_APPS_CLK		173
+#define MSM8937_GCC_BLSP1_QUP1_SPI_APPS_CLK		174
+#define MSM8937_GCC_BLSP2_QUP4_I2C_APPS_CLK		175
+#define MSM8937_GCC_BLSP2_QUP4_SPI_APPS_CLK		176
+#define MSM8937_GCC_MDSS_BYTE1_CLK			177
+#define MSM8937_GCC_MDSS_ESC1_CLK			178
+#define MSM8937_GCC_MDSS_PCLK1_CLK			179
+#define MSM8937_GCC_OXILI_AON_CLK			180
+#define MSM8937_GCC_OXILI_TIMER_CLK			181
 
 /* GCC block resets */
 #define GCC_CAMSS_MICRO_BCR			0
@@ -187,5 +204,7 @@
 #define VENUS_GDSC				5
 #define VFE0_GDSC				6
 #define VFE1_GDSC				7
+/* Additional MSM8937-specific GDSCs */
+#define MSM8937_OXILI_CX_GDSC				8
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
index 74c22f67da2..f19018b742f 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm660.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -138,10 +138,16 @@
 #define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK		128
 #define GCC_RX0_USB2_CLKREF_CLK			129
 #define GCC_RX1_USB2_CLKREF_CLK			130
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK	131
+#define GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK	132
+#define GCC_HLOS2_VOTE_TURING_ADSP_SMMU_CLK	133
 
 #define PCIE_0_GDSC	0
 #define UFS_GDSC	1
 #define USB_30_GDSC	2
+#define HLOS1_VOTE_TURING_ADSP_GDSC 3
+#define HLOS2_VOTE_TURING_ADSP_GDSC 4
+#define HLOS1_VOTE_LPASS_ADSP_GDSC 5
 
 #define GCC_QUSB2PHY_PRIM_BCR		0
 #define GCC_QUSB2PHY_SEC_BCR		1
diff --git a/include/dt-bindings/clock/qcom,glymur-dispcc.h b/include/dt-bindings/clock/qcom,glymur-dispcc.h
new file mode 100644
index 00000000000..a845d76defe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-dispcc.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_GLYMUR_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK					0
+#define DISP_CC_ESYNC0_CLK_SRC					1
+#define DISP_CC_ESYNC1_CLK					2
+#define DISP_CC_ESYNC1_CLK_SRC					3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK				4
+#define DISP_CC_MDSS_AHB1_CLK					5
+#define DISP_CC_MDSS_AHB_CLK					6
+#define DISP_CC_MDSS_AHB_CLK_SRC				7
+#define DISP_CC_MDSS_BYTE0_CLK					8
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				9
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				10
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				11
+#define DISP_CC_MDSS_BYTE1_CLK					12
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				13
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				14
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				15
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				16
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				17
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				18
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				19
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			20
+#define DISP_CC_MDSS_DPTX0_LINK_DPIN_CLK			21
+#define DISP_CC_MDSS_DPTX0_LINK_DPIN_DIV_CLK_SRC		22
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			23
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				24
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			25
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				26
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			27
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		28
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				29
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				30
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				31
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				32
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			33
+#define DISP_CC_MDSS_DPTX1_LINK_DPIN_CLK			34
+#define DISP_CC_MDSS_DPTX1_LINK_DPIN_DIV_CLK_SRC		35
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			36
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			38
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			40
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		41
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				43
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				44
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				45
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			46
+#define DISP_CC_MDSS_DPTX2_LINK_DPIN_CLK			47
+#define DISP_CC_MDSS_DPTX2_LINK_DPIN_DIV_CLK_SRC		48
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				50
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				52
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			53
+#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK		54
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				55
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				57
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				58
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			59
+#define DISP_CC_MDSS_DPTX3_LINK_DPIN_CLK			60
+#define DISP_CC_MDSS_DPTX3_LINK_DPIN_DIV_CLK_SRC		61
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			62
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				63
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			64
+#define DISP_CC_MDSS_ESC0_CLK					65
+#define DISP_CC_MDSS_ESC0_CLK_SRC				66
+#define DISP_CC_MDSS_ESC1_CLK					67
+#define DISP_CC_MDSS_ESC1_CLK_SRC				68
+#define DISP_CC_MDSS_MDP1_CLK					69
+#define DISP_CC_MDSS_MDP_CLK					70
+#define DISP_CC_MDSS_MDP_CLK_SRC				71
+#define DISP_CC_MDSS_MDP_LUT1_CLK				72
+#define DISP_CC_MDSS_MDP_LUT_CLK				73
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				74
+#define DISP_CC_MDSS_PCLK0_CLK					75
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				76
+#define DISP_CC_MDSS_PCLK1_CLK					77
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				78
+#define DISP_CC_MDSS_PCLK2_CLK					79
+#define DISP_CC_MDSS_PCLK2_CLK_SRC				80
+#define DISP_CC_MDSS_RSCC_AHB_CLK				81
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				82
+#define DISP_CC_MDSS_VSYNC1_CLK					83
+#define DISP_CC_MDSS_VSYNC_CLK					84
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				85
+#define DISP_CC_OSC_CLK						86
+#define DISP_CC_OSC_CLK_SRC					87
+#define DISP_CC_PLL0						88
+#define DISP_CC_PLL1						89
+#define DISP_CC_SLEEP_CLK					90
+#define DISP_CC_SLEEP_CLK_SRC					91
+#define DISP_CC_XO_CLK						92
+#define DISP_CC_XO_CLK_SRC					93
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC					0
+#define DISP_CC_MDSS_CORE_INT2_GDSC				1
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h
new file mode 100644
index 00000000000..10c12b8c51c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-gcc.h
@@ -0,0 +1,578 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H
+
+/* GCC clocks */
+#define GCC_GPLL0						0
+#define GCC_GPLL0_OUT_EVEN					1
+#define GCC_GPLL1						2
+#define GCC_GPLL14						3
+#define GCC_GPLL14_OUT_EVEN					4
+#define GCC_GPLL4						5
+#define GCC_GPLL5						6
+#define GCC_GPLL7						7
+#define GCC_GPLL8						8
+#define GCC_GPLL9						9
+#define GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK			10
+#define GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK			11
+#define GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK			12
+#define GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK			13
+#define GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK			14
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				15
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			16
+#define GCC_AGGRE_USB2_PRIM_AXI_CLK				17
+#define GCC_AGGRE_USB3_MP_AXI_CLK				18
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				19
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				20
+#define GCC_AGGRE_USB3_TERT_AXI_CLK				21
+#define GCC_AGGRE_USB4_0_AXI_CLK				22
+#define GCC_AGGRE_USB4_1_AXI_CLK				23
+#define GCC_AGGRE_USB4_2_AXI_CLK				24
+#define GCC_AV1E_AHB_CLK					25
+#define GCC_AV1E_AXI_CLK					26
+#define GCC_AV1E_XO_CLK						27
+#define GCC_BOOT_ROM_AHB_CLK					28
+#define GCC_CAMERA_AHB_CLK					29
+#define GCC_CAMERA_HF_AXI_CLK					30
+#define GCC_CAMERA_SF_AXI_CLK					31
+#define GCC_CAMERA_XO_CLK					32
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				33
+#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK			34
+#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK				35
+#define GCC_CFG_NOC_USB3_MP_AXI_CLK				36
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				37
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				38
+#define GCC_CFG_NOC_USB3_TERT_AXI_CLK				39
+#define GCC_CFG_NOC_USB_ANOC_AHB_CLK				40
+#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK			41
+#define GCC_DISP_AHB_CLK					42
+#define GCC_DISP_HF_AXI_CLK					43
+#define GCC_EVA_AHB_CLK						44
+#define GCC_EVA_AXI0_CLK					45
+#define GCC_EVA_AXI0C_CLK					46
+#define GCC_EVA_XO_CLK						47
+#define GCC_GP1_CLK						48
+#define GCC_GP1_CLK_SRC						49
+#define GCC_GP2_CLK						50
+#define GCC_GP2_CLK_SRC						51
+#define GCC_GP3_CLK						52
+#define GCC_GP3_CLK_SRC						53
+#define GCC_GPU_CFG_AHB_CLK					54
+#define GCC_GPU_GEMNOC_GFX_CLK					55
+#define GCC_GPU_GPLL0_CLK_SRC					56
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				57
+#define GCC_PCIE_0_AUX_CLK					58
+#define GCC_PCIE_0_AUX_CLK_SRC					59
+#define GCC_PCIE_0_CFG_AHB_CLK					60
+#define GCC_PCIE_0_MSTR_AXI_CLK					61
+#define GCC_PCIE_0_PHY_RCHNG_CLK				62
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				63
+#define GCC_PCIE_0_PIPE_CLK					64
+#define GCC_PCIE_0_SLV_AXI_CLK					65
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				66
+#define GCC_PCIE_1_AUX_CLK					67
+#define GCC_PCIE_1_AUX_CLK_SRC					68
+#define GCC_PCIE_1_CFG_AHB_CLK					69
+#define GCC_PCIE_1_MSTR_AXI_CLK					70
+#define GCC_PCIE_1_PHY_RCHNG_CLK				71
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				72
+#define GCC_PCIE_1_PIPE_CLK					73
+#define GCC_PCIE_1_SLV_AXI_CLK					74
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				75
+#define GCC_PCIE_2_AUX_CLK					76
+#define GCC_PCIE_2_AUX_CLK_SRC					77
+#define GCC_PCIE_2_CFG_AHB_CLK					78
+#define GCC_PCIE_2_MSTR_AXI_CLK					79
+#define GCC_PCIE_2_PHY_RCHNG_CLK				80
+#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC				81
+#define GCC_PCIE_2_PIPE_CLK					82
+#define GCC_PCIE_2_SLV_AXI_CLK					83
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK				84
+#define GCC_PCIE_3A_AUX_CLK					85
+#define GCC_PCIE_3A_AUX_CLK_SRC					86
+#define GCC_PCIE_3A_CFG_AHB_CLK					87
+#define GCC_PCIE_3A_MSTR_AXI_CLK				88
+#define GCC_PCIE_3A_PHY_RCHNG_CLK				89
+#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC				90
+#define GCC_PCIE_3A_PIPE_CLK					91
+#define GCC_PCIE_3A_PIPE_CLK_SRC				92
+#define GCC_PCIE_3A_SLV_AXI_CLK					93
+#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK				94
+#define GCC_PCIE_3B_AUX_CLK					95
+#define GCC_PCIE_3B_AUX_CLK_SRC					96
+#define GCC_PCIE_3B_CFG_AHB_CLK					97
+#define GCC_PCIE_3B_MSTR_AXI_CLK				98
+#define GCC_PCIE_3B_PHY_RCHNG_CLK				99
+#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC				100
+#define GCC_PCIE_3B_PIPE_CLK					101
+#define GCC_PCIE_3B_PIPE_CLK_SRC				102
+#define GCC_PCIE_3B_PIPE_DIV2_CLK				103
+#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC				104
+#define GCC_PCIE_3B_SLV_AXI_CLK					105
+#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK				106
+#define GCC_PCIE_4_AUX_CLK					107
+#define GCC_PCIE_4_AUX_CLK_SRC					108
+#define GCC_PCIE_4_CFG_AHB_CLK					109
+#define GCC_PCIE_4_MSTR_AXI_CLK					110
+#define GCC_PCIE_4_PHY_RCHNG_CLK				111
+#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC				112
+#define GCC_PCIE_4_PIPE_CLK					113
+#define GCC_PCIE_4_PIPE_CLK_SRC					114
+#define GCC_PCIE_4_PIPE_DIV2_CLK				115
+#define GCC_PCIE_4_PIPE_DIV_CLK_SRC				116
+#define GCC_PCIE_4_SLV_AXI_CLK					117
+#define GCC_PCIE_4_SLV_Q2A_AXI_CLK				118
+#define GCC_PCIE_5_AUX_CLK					119
+#define GCC_PCIE_5_AUX_CLK_SRC					120
+#define GCC_PCIE_5_CFG_AHB_CLK					121
+#define GCC_PCIE_5_MSTR_AXI_CLK					122
+#define GCC_PCIE_5_PHY_RCHNG_CLK				123
+#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC				124
+#define GCC_PCIE_5_PIPE_CLK					125
+#define GCC_PCIE_5_PIPE_CLK_SRC					126
+#define GCC_PCIE_5_PIPE_DIV2_CLK				127
+#define GCC_PCIE_5_PIPE_DIV_CLK_SRC				128
+#define GCC_PCIE_5_SLV_AXI_CLK					129
+#define GCC_PCIE_5_SLV_Q2A_AXI_CLK				130
+#define GCC_PCIE_6_AUX_CLK					131
+#define GCC_PCIE_6_AUX_CLK_SRC					132
+#define GCC_PCIE_6_CFG_AHB_CLK					133
+#define GCC_PCIE_6_MSTR_AXI_CLK					134
+#define GCC_PCIE_6_PHY_RCHNG_CLK				135
+#define GCC_PCIE_6_PHY_RCHNG_CLK_SRC				136
+#define GCC_PCIE_6_PIPE_CLK					137
+#define GCC_PCIE_6_PIPE_CLK_SRC					138
+#define GCC_PCIE_6_PIPE_DIV2_CLK				139
+#define GCC_PCIE_6_PIPE_DIV_CLK_SRC				140
+#define GCC_PCIE_6_SLV_AXI_CLK					141
+#define GCC_PCIE_6_SLV_Q2A_AXI_CLK				142
+#define GCC_PCIE_NOC_PWRCTL_CLK					143
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK				144
+#define GCC_PCIE_NOC_SF_CENTER_CLK				145
+#define GCC_PCIE_NOC_SLAVE_SF_EAST_CLK				146
+#define GCC_PCIE_NOC_SLAVE_SF_WEST_CLK				147
+#define GCC_PCIE_NOC_TSCTR_CLK					148
+#define GCC_PCIE_PHY_3A_AUX_CLK					149
+#define GCC_PCIE_PHY_3A_AUX_CLK_SRC				150
+#define GCC_PCIE_PHY_3B_AUX_CLK					151
+#define GCC_PCIE_PHY_3B_AUX_CLK_SRC				152
+#define GCC_PCIE_PHY_4_AUX_CLK					153
+#define GCC_PCIE_PHY_4_AUX_CLK_SRC				154
+#define GCC_PCIE_PHY_5_AUX_CLK					155
+#define GCC_PCIE_PHY_5_AUX_CLK_SRC				156
+#define GCC_PCIE_PHY_6_AUX_CLK					157
+#define GCC_PCIE_PHY_6_AUX_CLK_SRC				158
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				159
+#define GCC_PCIE_RSCC_XO_CLK					160
+#define GCC_PDM2_CLK						161
+#define GCC_PDM2_CLK_SRC					162
+#define GCC_PDM_AHB_CLK						163
+#define GCC_PDM_XO4_CLK						164
+#define GCC_QMIP_AV1E_AHB_CLK					165
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK				166
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				167
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				168
+#define GCC_QMIP_GPU_AHB_CLK					169
+#define GCC_QMIP_PCIE_3A_AHB_CLK				170
+#define GCC_QMIP_PCIE_3B_AHB_CLK				171
+#define GCC_QMIP_PCIE_4_AHB_CLK					172
+#define GCC_QMIP_PCIE_5_AHB_CLK					173
+#define GCC_QMIP_PCIE_6_AHB_CLK					174
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				175
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				176
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				177
+#define GCC_QMIP_VIDEO_VCODEC1_AHB_CLK				178
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				179
+#define GCC_QUPV3_OOB_CORE_2X_CLK				180
+#define GCC_QUPV3_OOB_CORE_CLK					181
+#define GCC_QUPV3_OOB_M_AHB_CLK					182
+#define GCC_QUPV3_OOB_QSPI_S0_CLK				183
+#define GCC_QUPV3_OOB_QSPI_S0_CLK_SRC				184
+#define GCC_QUPV3_OOB_QSPI_S1_CLK				185
+#define GCC_QUPV3_OOB_QSPI_S1_CLK_SRC				186
+#define GCC_QUPV3_OOB_S0_CLK					187
+#define GCC_QUPV3_OOB_S0_CLK_SRC				188
+#define GCC_QUPV3_OOB_S1_CLK					189
+#define GCC_QUPV3_OOB_S1_CLK_SRC				190
+#define GCC_QUPV3_OOB_S_AHB_CLK					191
+#define GCC_QUPV3_OOB_TCXO_CLK					192
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				193
+#define GCC_QUPV3_WRAP0_CORE_CLK				194
+#define GCC_QUPV3_WRAP0_QSPI_S2_CLK				195
+#define GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC				196
+#define GCC_QUPV3_WRAP0_QSPI_S3_CLK				197
+#define GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC				198
+#define GCC_QUPV3_WRAP0_QSPI_S6_CLK				199
+#define GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC				200
+#define GCC_QUPV3_WRAP0_S0_CLK					201
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				202
+#define GCC_QUPV3_WRAP0_S1_CLK					203
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				204
+#define GCC_QUPV3_WRAP0_S2_CLK					205
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				206
+#define GCC_QUPV3_WRAP0_S3_CLK					207
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				208
+#define GCC_QUPV3_WRAP0_S4_CLK					209
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				210
+#define GCC_QUPV3_WRAP0_S5_CLK					211
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				212
+#define GCC_QUPV3_WRAP0_S6_CLK					213
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				214
+#define GCC_QUPV3_WRAP0_S7_CLK					215
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				216
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				217
+#define GCC_QUPV3_WRAP1_CORE_CLK				218
+#define GCC_QUPV3_WRAP1_QSPI_S2_CLK				219
+#define GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC				220
+#define GCC_QUPV3_WRAP1_QSPI_S3_CLK				221
+#define GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC				222
+#define GCC_QUPV3_WRAP1_QSPI_S6_CLK				223
+#define GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC				224
+#define GCC_QUPV3_WRAP1_S0_CLK					225
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				226
+#define GCC_QUPV3_WRAP1_S1_CLK					227
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				228
+#define GCC_QUPV3_WRAP1_S2_CLK					229
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				230
+#define GCC_QUPV3_WRAP1_S3_CLK					231
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				232
+#define GCC_QUPV3_WRAP1_S4_CLK					233
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				234
+#define GCC_QUPV3_WRAP1_S5_CLK					235
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				236
+#define GCC_QUPV3_WRAP1_S6_CLK					237
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				238
+#define GCC_QUPV3_WRAP1_S7_CLK					239
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				240
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				241
+#define GCC_QUPV3_WRAP2_CORE_CLK				242
+#define GCC_QUPV3_WRAP2_QSPI_S2_CLK				243
+#define GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC				244
+#define GCC_QUPV3_WRAP2_QSPI_S3_CLK				245
+#define GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC				246
+#define GCC_QUPV3_WRAP2_QSPI_S6_CLK				247
+#define GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC				248
+#define GCC_QUPV3_WRAP2_S0_CLK					249
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				250
+#define GCC_QUPV3_WRAP2_S1_CLK					251
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				252
+#define GCC_QUPV3_WRAP2_S2_CLK					253
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				254
+#define GCC_QUPV3_WRAP2_S3_CLK					255
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				256
+#define GCC_QUPV3_WRAP2_S4_CLK					257
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				258
+#define GCC_QUPV3_WRAP2_S5_CLK					259
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				260
+#define GCC_QUPV3_WRAP2_S6_CLK					261
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				262
+#define GCC_QUPV3_WRAP2_S7_CLK					263
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				264
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				265
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				266
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				267
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				268
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				269
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				270
+#define GCC_SDCC2_AHB_CLK					271
+#define GCC_SDCC2_APPS_CLK					272
+#define GCC_SDCC2_APPS_CLK_SRC					273
+#define GCC_SDCC4_AHB_CLK					274
+#define GCC_SDCC4_APPS_CLK					275
+#define GCC_SDCC4_APPS_CLK_SRC					276
+#define GCC_UFS_PHY_AHB_CLK					277
+#define GCC_UFS_PHY_AXI_CLK					278
+#define GCC_UFS_PHY_AXI_CLK_SRC					279
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				280
+#define GCC_UFS_PHY_ICE_CORE_CLK				281
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				282
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				283
+#define GCC_UFS_PHY_PHY_AUX_CLK					284
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				285
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				286
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				287
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				288
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				289
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				290
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				291
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				292
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				293
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				294
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			295
+#define GCC_USB20_MASTER_CLK					296
+#define GCC_USB20_MASTER_CLK_SRC				297
+#define GCC_USB20_MOCK_UTMI_CLK					298
+#define GCC_USB20_MOCK_UTMI_CLK_SRC				299
+#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			300
+#define GCC_USB20_SLEEP_CLK					301
+#define GCC_USB30_MP_MASTER_CLK					302
+#define GCC_USB30_MP_MASTER_CLK_SRC				303
+#define GCC_USB30_MP_MOCK_UTMI_CLK				304
+#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC				305
+#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC			306
+#define GCC_USB30_MP_SLEEP_CLK					307
+#define GCC_USB30_PRIM_MASTER_CLK				308
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				309
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				310
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			311
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		312
+#define GCC_USB30_PRIM_SLEEP_CLK				313
+#define GCC_USB30_SEC_MASTER_CLK				314
+#define GCC_USB30_SEC_MASTER_CLK_SRC				315
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				316
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				317
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			318
+#define GCC_USB30_SEC_SLEEP_CLK					319
+#define GCC_USB30_TERT_MASTER_CLK				320
+#define GCC_USB30_TERT_MASTER_CLK_SRC				321
+#define GCC_USB30_TERT_MOCK_UTMI_CLK				322
+#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC			323
+#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC		324
+#define GCC_USB30_TERT_SLEEP_CLK				325
+#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC				326
+#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC				327
+#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC				328
+#define GCC_USB3_MP_PHY_AUX_CLK					329
+#define GCC_USB3_MP_PHY_AUX_CLK_SRC				330
+#define GCC_USB3_MP_PHY_COM_AUX_CLK				331
+#define GCC_USB3_MP_PHY_PIPE_0_CLK				332
+#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC				333
+#define GCC_USB3_MP_PHY_PIPE_1_CLK				334
+#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC				335
+#define GCC_USB3_PRIM_PHY_AUX_CLK				336
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				337
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				338
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				339
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				340
+#define GCC_USB3_SEC_PHY_AUX_CLK				341
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				342
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				343
+#define GCC_USB3_SEC_PHY_PIPE_CLK				344
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				345
+#define GCC_USB3_TERT_PHY_AUX_CLK				346
+#define GCC_USB3_TERT_PHY_AUX_CLK_SRC				347
+#define GCC_USB3_TERT_PHY_COM_AUX_CLK				348
+#define GCC_USB3_TERT_PHY_PIPE_CLK				349
+#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC				350
+#define GCC_USB4_0_CFG_AHB_CLK					351
+#define GCC_USB4_0_DP0_CLK					352
+#define GCC_USB4_0_DP1_CLK					353
+#define GCC_USB4_0_MASTER_CLK					354
+#define GCC_USB4_0_MASTER_CLK_SRC				355
+#define GCC_USB4_0_PHY_DP0_CLK_SRC				356
+#define GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC				357
+#define GCC_USB4_0_PHY_DP1_CLK_SRC				358
+#define GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC				359
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK				360
+#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC			361
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK				362
+#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC			363
+#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC			364
+#define GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC			365
+#define GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC				366
+#define GCC_USB4_0_PHY_RX0_CLK					367
+#define GCC_USB4_0_PHY_RX0_CLK_SRC				368
+#define GCC_USB4_0_PHY_RX1_CLK					369
+#define GCC_USB4_0_PHY_RX1_CLK_SRC				370
+#define GCC_USB4_0_PHY_SYS_CLK_SRC				371
+#define GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC			372
+#define GCC_USB4_0_PHY_USB_PIPE_CLK				373
+#define GCC_USB4_0_SB_IF_CLK					374
+#define GCC_USB4_0_SB_IF_CLK_SRC				375
+#define GCC_USB4_0_SYS_CLK					376
+#define GCC_USB4_0_TMU_CLK					377
+#define GCC_USB4_0_TMU_CLK_SRC					378
+#define GCC_USB4_0_UC_HRR_CLK					379
+#define GCC_USB4_1_CFG_AHB_CLK					380
+#define GCC_USB4_1_DP0_CLK					381
+#define GCC_USB4_1_DP1_CLK					382
+#define GCC_USB4_1_MASTER_CLK					383
+#define GCC_USB4_1_MASTER_CLK_SRC				384
+#define GCC_USB4_1_PHY_DP0_CLK_SRC				385
+#define GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC			386
+#define GCC_USB4_1_PHY_DP1_CLK_SRC				387
+#define GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC			388
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK				389
+#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC			390
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK				391
+#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC			392
+#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC			393
+#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC			394
+#define GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC				395
+#define GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC				396
+#define GCC_USB4_1_PHY_RX0_CLK					397
+#define GCC_USB4_1_PHY_RX0_CLK_SRC				398
+#define GCC_USB4_1_PHY_RX1_CLK					399
+#define GCC_USB4_1_PHY_RX1_CLK_SRC				400
+#define GCC_USB4_1_PHY_SYS_CLK_SRC				401
+#define GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC			402
+#define GCC_USB4_1_PHY_USB_PIPE_CLK				403
+#define GCC_USB4_1_SB_IF_CLK					404
+#define GCC_USB4_1_SB_IF_CLK_SRC				405
+#define GCC_USB4_1_SYS_CLK					406
+#define GCC_USB4_1_TMU_CLK					407
+#define GCC_USB4_1_TMU_CLK_SRC					408
+#define GCC_USB4_1_UC_HRR_CLK					409
+#define GCC_USB4_2_CFG_AHB_CLK					410
+#define GCC_USB4_2_DP0_CLK					411
+#define GCC_USB4_2_DP1_CLK					412
+#define GCC_USB4_2_MASTER_CLK					413
+#define GCC_USB4_2_MASTER_CLK_SRC				414
+#define GCC_USB4_2_PHY_DP0_CLK_SRC				415
+#define GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC				416
+#define GCC_USB4_2_PHY_DP1_CLK_SRC				417
+#define GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC				418
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK				419
+#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC			420
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK				421
+#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC			422
+#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC			423
+#define GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC			424
+#define GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC				425
+#define GCC_USB4_2_PHY_RX0_CLK					426
+#define GCC_USB4_2_PHY_RX0_CLK_SRC				427
+#define GCC_USB4_2_PHY_RX1_CLK					428
+#define GCC_USB4_2_PHY_RX1_CLK_SRC				429
+#define GCC_USB4_2_PHY_SYS_CLK_SRC				430
+#define GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC			431
+#define GCC_USB4_2_PHY_USB_PIPE_CLK				432
+#define GCC_USB4_2_SB_IF_CLK					433
+#define GCC_USB4_2_SB_IF_CLK_SRC				434
+#define GCC_USB4_2_SYS_CLK					435
+#define GCC_USB4_2_TMU_CLK					436
+#define GCC_USB4_2_TMU_CLK_SRC					437
+#define GCC_USB4_2_UC_HRR_CLK					438
+#define GCC_VIDEO_AHB_CLK					439
+#define GCC_VIDEO_AXI0_CLK					440
+#define GCC_VIDEO_AXI0C_CLK					441
+#define GCC_VIDEO_AXI1_CLK					442
+#define GCC_VIDEO_XO_CLK					443
+
+/* GCC power domains */
+#define GCC_PCIE_0_TUNNEL_GDSC					0
+#define GCC_PCIE_1_TUNNEL_GDSC					1
+#define GCC_PCIE_2_TUNNEL_GDSC					2
+#define GCC_PCIE_3A_GDSC					3
+#define GCC_PCIE_3A_PHY_GDSC					4
+#define GCC_PCIE_3B_GDSC					5
+#define GCC_PCIE_3B_PHY_GDSC					6
+#define GCC_PCIE_4_GDSC						7
+#define GCC_PCIE_4_PHY_GDSC					8
+#define GCC_PCIE_5_GDSC						9
+#define GCC_PCIE_5_PHY_GDSC					10
+#define GCC_PCIE_6_GDSC						11
+#define GCC_PCIE_6_PHY_GDSC					12
+#define GCC_UFS_PHY_GDSC					13
+#define GCC_USB20_PRIM_GDSC					14
+#define GCC_USB30_MP_GDSC					15
+#define GCC_USB30_PRIM_GDSC					16
+#define GCC_USB30_SEC_GDSC					17
+#define GCC_USB30_TERT_GDSC					18
+#define GCC_USB3_MP_SS0_PHY_GDSC				19
+#define GCC_USB3_MP_SS1_PHY_GDSC				20
+#define GCC_USB4_0_GDSC						21
+#define GCC_USB4_1_GDSC						22
+#define GCC_USB4_2_GDSC						23
+#define GCC_USB_0_PHY_GDSC					24
+#define GCC_USB_1_PHY_GDSC					25
+#define GCC_USB_2_PHY_GDSC					26
+
+/* GCC resets */
+#define GCC_AV1E_BCR						0
+#define GCC_CAMERA_BCR						1
+#define GCC_DISPLAY_BCR						2
+#define GCC_EVA_BCR						3
+#define GCC_GPU_BCR						4
+#define GCC_PCIE_0_LINK_DOWN_BCR				5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				6
+#define GCC_PCIE_0_PHY_BCR					7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			8
+#define GCC_PCIE_0_TUNNEL_BCR					9
+#define GCC_PCIE_1_LINK_DOWN_BCR				10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				11
+#define GCC_PCIE_1_PHY_BCR					12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			13
+#define GCC_PCIE_1_TUNNEL_BCR					14
+#define GCC_PCIE_2_LINK_DOWN_BCR				15
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR				16
+#define GCC_PCIE_2_PHY_BCR					17
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR			18
+#define GCC_PCIE_2_TUNNEL_BCR					19
+#define GCC_PCIE_3A_BCR						20
+#define GCC_PCIE_3A_LINK_DOWN_BCR				21
+#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR				22
+#define GCC_PCIE_3A_PHY_BCR					23
+#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR			24
+#define GCC_PCIE_3B_BCR						25
+#define GCC_PCIE_3B_LINK_DOWN_BCR				26
+#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR				27
+#define GCC_PCIE_3B_PHY_BCR					28
+#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR			29
+#define GCC_PCIE_4_BCR						30
+#define GCC_PCIE_4_LINK_DOWN_BCR				31
+#define GCC_PCIE_4_NOCSR_COM_PHY_BCR				32
+#define GCC_PCIE_4_PHY_BCR					33
+#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR			34
+#define GCC_PCIE_5_BCR						35
+#define GCC_PCIE_5_LINK_DOWN_BCR				36
+#define GCC_PCIE_5_NOCSR_COM_PHY_BCR				37
+#define GCC_PCIE_5_PHY_BCR					38
+#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR			39
+#define GCC_PCIE_6_BCR						40
+#define GCC_PCIE_6_LINK_DOWN_BCR				41
+#define GCC_PCIE_6_NOCSR_COM_PHY_BCR				42
+#define GCC_PCIE_6_PHY_BCR					43
+#define GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR			44
+#define GCC_PCIE_NOC_BCR					45
+#define GCC_PCIE_PHY_BCR					46
+#define GCC_PCIE_PHY_CFG_AHB_BCR				47
+#define GCC_PCIE_PHY_COM_BCR					48
+#define GCC_PCIE_RSCC_BCR					49
+#define GCC_PDM_BCR						50
+#define GCC_QUPV3_WRAPPER_0_BCR					51
+#define GCC_QUPV3_WRAPPER_1_BCR					52
+#define GCC_QUPV3_WRAPPER_2_BCR					53
+#define GCC_QUPV3_WRAPPER_OOB_BCR				54
+#define GCC_QUSB2PHY_HS0_MP_BCR					55
+#define GCC_QUSB2PHY_HS1_MP_BCR					56
+#define GCC_QUSB2PHY_PRIM_BCR					57
+#define GCC_QUSB2PHY_SEC_BCR					58
+#define GCC_QUSB2PHY_TERT_BCR					59
+#define GCC_QUSB2PHY_USB20_HS_BCR				60
+#define GCC_SDCC2_BCR						61
+#define GCC_SDCC4_BCR						62
+#define GCC_TCSR_PCIE_BCR					63
+#define GCC_UFS_PHY_BCR						64
+#define GCC_USB20_PRIM_BCR					65
+#define GCC_USB30_MP_BCR					66
+#define GCC_USB30_PRIM_BCR					67
+#define GCC_USB30_SEC_BCR					68
+#define GCC_USB30_TERT_BCR					69
+#define GCC_USB3_MP_SS0_PHY_BCR					70
+#define GCC_USB3_MP_SS1_PHY_BCR					71
+#define GCC_USB3_PHY_PRIM_BCR					72
+#define GCC_USB3_PHY_SEC_BCR					73
+#define GCC_USB3_PHY_TERT_BCR					74
+#define GCC_USB3_UNIPHY_MP0_BCR					75
+#define GCC_USB3_UNIPHY_MP1_BCR					76
+#define GCC_USB3PHY_PHY_PRIM_BCR				77
+#define GCC_USB3PHY_PHY_SEC_BCR					78
+#define GCC_USB3PHY_PHY_TERT_BCR				79
+#define GCC_USB3UNIPHY_PHY_MP0_BCR				80
+#define GCC_USB3UNIPHY_PHY_MP1_BCR				81
+#define GCC_USB4_0_BCR						82
+#define GCC_USB4_0_DP0_PHY_PRIM_BCR				83
+#define GCC_USB4_1_BCR						84
+#define GCC_USB4_2_BCR						85
+#define GCC_USB_0_PHY_BCR					86
+#define GCC_USB_1_PHY_BCR					87
+#define GCC_USB_2_PHY_BCR					88
+#define GCC_VIDEO_AXI0_CLK_ARES					89
+#define GCC_VIDEO_AXI1_CLK_ARES					90
+#define GCC_VIDEO_BCR						91
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-tcsr.h b/include/dt-bindings/clock/qcom,glymur-tcsr.h
new file mode 100644
index 00000000000..72614226b11
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-tcsr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_GLYMUR_H
+
+/* TCSR_CC clocks */
+#define TCSR_EDP_CLKREF_EN					0
+#define TCSR_PCIE_1_CLKREF_EN					1
+#define TCSR_PCIE_2_CLKREF_EN					2
+#define TCSR_PCIE_3_CLKREF_EN					3
+#define TCSR_PCIE_4_CLKREF_EN					4
+#define TCSR_USB2_1_CLKREF_EN					5
+#define TCSR_USB2_2_CLKREF_EN					6
+#define TCSR_USB2_3_CLKREF_EN					7
+#define TCSR_USB2_4_CLKREF_EN					8
+#define TCSR_USB3_0_CLKREF_EN					9
+#define TCSR_USB3_1_CLKREF_EN					10
+#define TCSR_USB4_1_CLKREF_EN					11
+#define TCSR_USB4_2_CLKREF_EN					12
+
+#endif
diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
index 248efb895f3..7915fb8197b 100644
--- a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
+++ b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
@@ -58,4 +58,8 @@
 #define RP1_PLL_VIDEO_PRI_PH		43
 #define RP1_PLL_AUDIO_TERN		44
 
+/* MIPI clocks managed by the DSI driver */
+#define RP1_CLK_MIPI0_DSI_BYTECLOCK	45
+#define RP1_CLK_MIPI1_DSI_BYTECLOCK	46
+
 #endif
diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c..f165df8a6f5 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
 #define R9A09G047_SPI_CLK_SPI			9
 #define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
+#define R9A09G047_USB3_0_REF_ALT_CLK_P		12
+#define R9A09G047_USB3_0_CLKCORE		13
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index 7ecc4f0b235..2a805e06487 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -25,5 +25,11 @@
 #define R9A09G077_CLK_PCLKM		13
 #define R9A09G077_CLK_PCLKL		14
 #define R9A09G077_SDHI_CLKHS		15
+#define R9A09G077_USB_CLK		16
+#define R9A09G077_ETCLKA		17
+#define R9A09G077_ETCLKB		18
+#define R9A09G077_ETCLKC		19
+#define R9A09G077_ETCLKD		20
+#define R9A09G077_ETCLKE		21
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index 925e5770392..09da0ad33be 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -25,5 +25,11 @@
 #define R9A09G087_CLK_PCLKM		13
 #define R9A09G087_CLK_PCLKL		14
 #define R9A09G087_SDHI_CLKHS		15
+#define R9A09G087_USB_CLK		16
+#define R9A09G087_ETCLKA		17
+#define R9A09G087_ETCLKB		18
+#define R9A09G087_ETCLKC		19
+#define R9A09G087_ETCLKD		20
+#define R9A09G087_ETCLKE		21
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index ebae3cbf819..b951e290694 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -72,6 +72,7 @@
 #define SCLK_SFC		126
 #define SCLK_MAC		127
 #define SCLK_MACREF_OUT		128
+#define SCLK_MIPIDSI_24M	129
 #define SCLK_TIMER10		133
 #define SCLK_TIMER11		134
 #define SCLK_TIMER12		135
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 6b9df09d282..47540307cb5 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -208,6 +208,10 @@
 #define CLK_GOUT_CMU_SSP_BUS		197
 #define CLK_GOUT_CMU_TNR_BUS		198
 #define CLK_GOUT_CMU_VRA_BUS		199
+#define CLK_MOUT_CMU_CMUREF		200
+#define CLK_MOUT_CMU_DPU_BUS		201
+#define CLK_MOUT_CMU_CLK_CMUREF		202
+#define CLK_DOUT_CMU_CLK_CMUREF		203
 
 /* CMU_HSI0 */
 #define CLK_MOUT_HSI0_BUS_USER				1
@@ -232,6 +236,183 @@
 #define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK		20
 #define CLK_GOUT_HSI0_CMU_HSI0_PCLK			21
 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK			22
+#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK		23
+
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER		1
+#define CLK_MOUT_PERIC0_UART_DBG		2
+#define CLK_MOUT_PERIC0_USI00_USI_USER		3
+#define CLK_MOUT_PERIC0_USI01_USI_USER		4
+#define CLK_MOUT_PERIC0_USI02_USI_USER		5
+#define CLK_MOUT_PERIC0_USI03_USI_USER		6
+#define CLK_MOUT_PERIC0_USI04_USI_USER		7
+#define CLK_MOUT_PERIC0_USI05_USI_USER		8
+#define CLK_MOUT_PERIC0_USI13_USI_USER		9
+#define CLK_MOUT_PERIC0_USI14_USI_USER		10
+#define CLK_MOUT_PERIC0_USI15_USI_USER		11
+#define CLK_MOUT_PERIC0_USI_I2C_USER		12
+#define CLK_DOUT_PERIC0_UART_DBG		13
+#define CLK_DOUT_PERIC0_USI00_USI		14
+#define CLK_DOUT_PERIC0_USI01_USI		15
+#define CLK_DOUT_PERIC0_USI02_USI		16
+#define CLK_DOUT_PERIC0_USI03_USI		17
+#define CLK_DOUT_PERIC0_USI04_USI		18
+#define CLK_DOUT_PERIC0_USI05_USI		19
+#define CLK_DOUT_PERIC0_USI13_USI		20
+#define CLK_DOUT_PERIC0_USI14_USI		21
+#define CLK_DOUT_PERIC0_USI15_USI		22
+#define CLK_DOUT_PERIC0_USI_I2C			23
+#define CLK_GOUT_PERIC0_CMU_PCLK		24
+#define CLK_GOUT_PERIC0_OSCCLK_CLK		25
+#define CLK_GOUT_PERIC0_D_TZPC_PCLK		26
+#define CLK_GOUT_PERIC0_GPIO_PCLK		27
+#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK		28
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_10		29
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_11		30
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_12		31
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_13		32
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_14		33
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_15		34
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_4		35
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_5		36
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_6		37
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_7		38
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_8		39
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_9		40
+#define CLK_GOUT_PERIC0_TOP0_PCLK_10		41
+#define CLK_GOUT_PERIC0_TOP0_PCLK_11		42
+#define CLK_GOUT_PERIC0_TOP0_PCLK_12		43
+#define CLK_GOUT_PERIC0_TOP0_PCLK_13		44
+#define CLK_GOUT_PERIC0_TOP0_PCLK_14		45
+#define CLK_GOUT_PERIC0_TOP0_PCLK_15		46
+#define CLK_GOUT_PERIC0_TOP0_PCLK_4		47
+#define CLK_GOUT_PERIC0_TOP0_PCLK_5		48
+#define CLK_GOUT_PERIC0_TOP0_PCLK_6		49
+#define CLK_GOUT_PERIC0_TOP0_PCLK_7		50
+#define CLK_GOUT_PERIC0_TOP0_PCLK_8		51
+#define CLK_GOUT_PERIC0_TOP0_PCLK_9		52
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_0		53
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_3		54
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_4		55
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_5		56
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_6		57
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_7		58
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_8		59
+#define CLK_GOUT_PERIC0_TOP1_PCLK_0		60
+#define CLK_GOUT_PERIC0_TOP1_PCLK_15		61
+#define CLK_GOUT_PERIC0_TOP1_PCLK_3		62
+#define CLK_GOUT_PERIC0_TOP1_PCLK_4		63
+#define CLK_GOUT_PERIC0_TOP1_PCLK_5		64
+#define CLK_GOUT_PERIC0_TOP1_PCLK_6		65
+#define CLK_GOUT_PERIC0_TOP1_PCLK_7		66
+#define CLK_GOUT_PERIC0_TOP1_PCLK_8		67
+#define CLK_GOUT_PERIC0_BUSP_CLK		68
+#define CLK_GOUT_PERIC0_UART_DBG_CLK		69
+#define CLK_GOUT_PERIC0_USI00_USI_CLK		70
+#define CLK_GOUT_PERIC0_USI01_USI_CLK		71
+#define CLK_GOUT_PERIC0_USI02_USI_CLK		72
+#define CLK_GOUT_PERIC0_USI03_USI_CLK		73
+#define CLK_GOUT_PERIC0_USI04_USI_CLK		74
+#define CLK_GOUT_PERIC0_USI05_USI_CLK		75
+#define CLK_GOUT_PERIC0_USI13_USI_CLK		76
+#define CLK_GOUT_PERIC0_USI14_USI_CLK		77
+#define CLK_GOUT_PERIC0_USI15_USI_CLK		78
+#define CLK_GOUT_PERIC0_USI_I2C_CLK		79
+#define CLK_GOUT_PERIC0_SYSREG_PCLK		80
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER		1
+#define CLK_MOUT_PERIC1_UART_BT_USER		2
+#define CLK_MOUT_PERIC1_USI06_USI_USER		3
+#define CLK_MOUT_PERIC1_USI07_USI_USER		4
+#define CLK_MOUT_PERIC1_USI08_USI_USER		5
+#define CLK_MOUT_PERIC1_USI09_USI_USER		6
+#define CLK_MOUT_PERIC1_USI10_USI_USER		7
+#define CLK_MOUT_PERIC1_USI11_USI_USER		8
+#define CLK_MOUT_PERIC1_USI12_USI_USER		9
+#define CLK_MOUT_PERIC1_USI18_USI_USER		10
+#define CLK_MOUT_PERIC1_USI16_USI_USER		11
+#define CLK_MOUT_PERIC1_USI17_USI_USER		12
+#define CLK_MOUT_PERIC1_USI_I2C_USER            13
+#define CLK_DOUT_PERIC1_UART_BT			14
+#define CLK_DOUT_PERIC1_USI06_USI		15
+#define CLK_DOUT_PERIC1_USI07_USI		16
+#define CLK_DOUT_PERIC1_USI08_USI		17
+#define CLK_DOUT_PERIC1_USI18_USI		18
+#define CLK_DOUT_PERIC1_USI12_USI		19
+#define CLK_DOUT_PERIC1_USI09_USI		20
+#define CLK_DOUT_PERIC1_USI10_USI		21
+#define CLK_DOUT_PERIC1_USI11_USI		22
+#define CLK_DOUT_PERIC1_USI16_USI		23
+#define CLK_DOUT_PERIC1_USI17_USI		24
+#define CLK_DOUT_PERIC1_USI_I2C			25
+#define CLK_GOUT_PERIC1_CMU_PCLK		26
+#define CLK_GOUT_PERIC1_UART_BT_CLK		27
+#define CLK_GOUT_PERIC1_USI12_USI_CLK		28
+#define CLK_GOUT_PERIC1_USI18_USI_CLK		29
+#define CLK_GOUT_PERIC1_D_TZPC_PCLK		30
+#define CLK_GOUT_PERIC1_GPIO_PCLK		31
+#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK	32
+#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK		33
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_10		34
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_11		35
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_12		36
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_13		37
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_14		38
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_15		39
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_4		40
+#define CLK_GOUT_PERIC1_TOP0_PCLK_10		41
+#define CLK_GOUT_PERIC1_TOP0_PCLK_11		42
+#define CLK_GOUT_PERIC1_TOP0_PCLK_12		43
+#define CLK_GOUT_PERIC1_TOP0_PCLK_13		44
+#define CLK_GOUT_PERIC1_TOP0_PCLK_14		45
+#define CLK_GOUT_PERIC1_TOP0_PCLK_15		46
+#define CLK_GOUT_PERIC1_TOP0_PCLK_4		47
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_0		48
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_1		49
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_10		50
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_12		51
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_13		52
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_14		53
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_15		54
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_2		55
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_3		56
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_4		57
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_5		58
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_6		59
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_7		60
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_9		61
+#define CLK_GOUT_PERIC1_TOP1_PCLK_0		62
+#define CLK_GOUT_PERIC1_TOP1_PCLK_1		63
+#define CLK_GOUT_PERIC1_TOP1_PCLK_10		64
+#define CLK_GOUT_PERIC1_TOP1_PCLK_12		65
+#define CLK_GOUT_PERIC1_TOP1_PCLK_13		66
+#define CLK_GOUT_PERIC1_TOP1_PCLK_14		67
+#define CLK_GOUT_PERIC1_TOP1_PCLK_15		68
+#define CLK_GOUT_PERIC1_TOP1_PCLK_2		69
+#define CLK_GOUT_PERIC1_TOP1_PCLK_3		70
+#define CLK_GOUT_PERIC1_TOP1_PCLK_4		71
+#define CLK_GOUT_PERIC1_TOP1_PCLK_5		72
+#define CLK_GOUT_PERIC1_TOP1_PCLK_6		73
+#define CLK_GOUT_PERIC1_TOP1_PCLK_7		74
+#define CLK_GOUT_PERIC1_TOP1_PCLK_9		75
+#define CLK_GOUT_PERIC1_BUSP_CLK		76
+#define CLK_GOUT_PERIC1_OSCCLK_CLK		77
+#define CLK_GOUT_PERIC1_USI06_USI_CLK		78
+#define CLK_GOUT_PERIC1_USI07_USI_CLK		79
+#define CLK_GOUT_PERIC1_USI08_USI_CLK		80
+#define CLK_GOUT_PERIC1_USI09_USI_CLK		81
+#define CLK_GOUT_PERIC1_USI10_USI_CLK		82
+#define CLK_GOUT_PERIC1_USI11_USI_CLK		83
+#define CLK_GOUT_PERIC1_USI16_USI_CLK		84
+#define CLK_GOUT_PERIC1_USI17_USI_CLK		85
+#define CLK_GOUT_PERIC1_USI_I2C_CLK		86
+#define CLK_GOUT_PERIC1_SYSREG_PCLK		87
+#define CLK_GOUT_PERIC1_USI16_I3C_PCLK		88
+#define CLK_GOUT_PERIC1_USI16_I3C_SCLK		89
+#define CLK_GOUT_PERIC1_USI17_I3C_PCLK		90
+#define CLK_GOUT_PERIC1_USI17_I3C_SCLK		91
+#define CLK_GOUT_PERIC1_XIU_P_ACLK		92
 
 /* CMU_PERIS */
 #define CLK_MOUT_PERIS_BUS_USER			1
diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
index 2714c3fe66c..0f8b59d6753 100644
--- a/include/dt-bindings/clock/spacemit,k1-syscon.h
+++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
@@ -77,6 +77,10 @@
 #define CLK_I2S_BCLK		30
 #define CLK_APB			31
 #define CLK_WDT_BUS		32
+#define CLK_I2S_153P6		33
+#define CLK_I2S_153P6_BASE	34
+#define CLK_I2S_SYSCLK_SRC	35
+#define CLK_I2S_BCLK_FACTOR	36
 
 /* MPMU resets */
 #define RESET_WDT		0
@@ -182,6 +186,8 @@
 #define CLK_SSPA1_BUS		97
 #define CLK_TSEN_BUS		98
 #define CLK_IPC_AP2AUD_BUS	99
+#define CLK_SSPA0_I2S_BCLK	100
+#define CLK_SSPA1_I2S_BCLK	101
 
 /* APBC resets */
 #define RESET_UART0		0
diff --git a/include/dt-bindings/clock/st,stm32mp21-rcc.h b/include/dt-bindings/clock/st,stm32mp21-rcc.h
new file mode 100644
index 00000000000..054b785f279
--- /dev/null
+++ b/include/dt-bindings/clock/st,stm32mp21-rcc.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Gabriel Fernandez <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_CLKS_H_
+#define _DT_BINDINGS_STM32MP21_CLKS_H_
+
+/* INTERNAL/EXTERNAL OSCILLATORS */
+#define HSI_CK			0
+#define HSE_CK			1
+#define MSI_CK			2
+#define LSI_CK			3
+#define LSE_CK			4
+#define I2S_CK			5
+#define RTC_CK			6
+#define SPDIF_CK_SYMB		7
+
+/* PLL CLOCKS */
+#define PLL1_CK			8
+#define PLL2_CK			9
+#define PLL4_CK			10
+#define PLL5_CK			11
+#define PLL6_CK			12
+#define PLL7_CK			13
+#define PLL8_CK			14
+
+#define CK_CPU1			15
+
+/* APB DIV CLOCKS */
+#define CK_ICN_APB1		16
+#define CK_ICN_APB2		17
+#define CK_ICN_APB3		18
+#define CK_ICN_APB4		19
+#define CK_ICN_APB5		20
+#define CK_ICN_APBDBG		21
+
+/* GLOBAL TIMER */
+#define TIMG1_CK		22
+#define TIMG2_CK		23
+
+/* FLEXGEN CLOCKS */
+#define CK_ICN_HS_MCU		24
+#define CK_ICN_SDMMC		25
+#define CK_ICN_DDR		26
+#define CK_ICN_DISPLAY		27
+#define CK_ICN_HSL		28
+#define CK_ICN_NIC		29
+#define CK_ICN_VID		30
+#define CK_FLEXGEN_07		31
+#define CK_FLEXGEN_08		32
+#define CK_FLEXGEN_09		33
+#define CK_FLEXGEN_10		34
+#define CK_FLEXGEN_11		35
+#define CK_FLEXGEN_12		36
+#define CK_FLEXGEN_13		37
+#define CK_FLEXGEN_14		38
+#define CK_FLEXGEN_15		39
+#define CK_FLEXGEN_16		40
+#define CK_FLEXGEN_17		41
+#define CK_FLEXGEN_18		42
+#define CK_FLEXGEN_19		43
+#define CK_FLEXGEN_20		44
+#define CK_FLEXGEN_21		45
+#define CK_FLEXGEN_22		46
+#define CK_FLEXGEN_23		47
+#define CK_FLEXGEN_24		48
+#define CK_FLEXGEN_25		49
+#define CK_FLEXGEN_26		50
+#define CK_FLEXGEN_27		51
+#define CK_FLEXGEN_28		52
+#define CK_FLEXGEN_29		53
+#define CK_FLEXGEN_30		54
+#define CK_FLEXGEN_31		55
+#define CK_FLEXGEN_32		56
+#define CK_FLEXGEN_33		57
+#define CK_FLEXGEN_34		58
+#define CK_FLEXGEN_35		59
+#define CK_FLEXGEN_36		60
+#define CK_FLEXGEN_37		61
+#define CK_FLEXGEN_38		62
+#define CK_FLEXGEN_39		63
+#define CK_FLEXGEN_40		64
+#define CK_FLEXGEN_41		65
+#define CK_FLEXGEN_42		66
+#define CK_FLEXGEN_43		67
+#define CK_FLEXGEN_44		68
+#define CK_FLEXGEN_45		69
+#define CK_FLEXGEN_46		70
+#define CK_FLEXGEN_47		71
+#define CK_FLEXGEN_48		72
+#define CK_FLEXGEN_49		73
+#define CK_FLEXGEN_50		74
+#define CK_FLEXGEN_51		75
+#define CK_FLEXGEN_52		76
+#define CK_FLEXGEN_53		77
+#define CK_FLEXGEN_54		78
+#define CK_FLEXGEN_55		79
+#define CK_FLEXGEN_56		80
+#define CK_FLEXGEN_57		81
+#define CK_FLEXGEN_58		82
+#define CK_FLEXGEN_59		83
+#define CK_FLEXGEN_60		84
+#define CK_FLEXGEN_61		85
+#define CK_FLEXGEN_62		86
+#define CK_FLEXGEN_63		87
+
+/* LOW SPEED MCU CLOCK */
+#define CK_ICN_LS_MCU		88
+
+#define CK_BUS_STM		89
+#define CK_BUS_FMC		90
+#define CK_BUS_ETH1		91
+#define CK_BUS_ETH2		92
+#define CK_BUS_DDRPHYC		93
+#define CK_BUS_SYSCPU1		94
+#define CK_BUS_HPDMA1		95
+#define CK_BUS_HPDMA2		96
+#define CK_BUS_HPDMA3		97
+#define CK_BUS_ADC1		98
+#define CK_BUS_ADC2		99
+#define CK_BUS_IPCC1		100
+#define CK_BUS_DCMIPSSI		101
+#define CK_BUS_CRC		102
+#define CK_BUS_MDF1		103
+#define CK_BUS_BKPSRAM		104
+#define CK_BUS_HASH1		105
+#define CK_BUS_HASH2		106
+#define CK_BUS_RNG1		107
+#define CK_BUS_RNG2		108
+#define CK_BUS_CRYP1		109
+#define CK_BUS_CRYP2		110
+#define CK_BUS_SAES		111
+#define CK_BUS_PKA		112
+#define CK_BUS_GPIOA		113
+#define CK_BUS_GPIOB		114
+#define CK_BUS_GPIOC		115
+#define CK_BUS_GPIOD		116
+#define CK_BUS_GPIOE		117
+#define CK_BUS_GPIOF		118
+#define CK_BUS_GPIOG		119
+#define CK_BUS_GPIOH		120
+#define CK_BUS_GPIOI		121
+#define CK_BUS_GPIOZ		122
+#define CK_BUS_RTC		124
+#define CK_BUS_LPUART1		125
+#define CK_BUS_LPTIM3		126
+#define CK_BUS_LPTIM4		127
+#define CK_BUS_LPTIM5		128
+#define CK_BUS_TIM2		129
+#define CK_BUS_TIM3		130
+#define CK_BUS_TIM4		131
+#define CK_BUS_TIM5		132
+#define CK_BUS_TIM6		133
+#define CK_BUS_TIM7		134
+#define CK_BUS_TIM10		135
+#define CK_BUS_TIM11		136
+#define CK_BUS_TIM12		137
+#define CK_BUS_TIM13		138
+#define CK_BUS_TIM14		139
+#define CK_BUS_LPTIM1		140
+#define CK_BUS_LPTIM2		141
+#define CK_BUS_SPI2		142
+#define CK_BUS_SPI3		143
+#define CK_BUS_SPDIFRX		144
+#define CK_BUS_USART2		145
+#define CK_BUS_USART3		146
+#define CK_BUS_UART4		147
+#define CK_BUS_UART5		148
+#define CK_BUS_I2C1		149
+#define CK_BUS_I2C2		150
+#define CK_BUS_I2C3		151
+#define CK_BUS_I3C1		152
+#define CK_BUS_I3C2		153
+#define CK_BUS_I3C3		154
+#define CK_BUS_TIM1		155
+#define CK_BUS_TIM8		156
+#define CK_BUS_TIM15		157
+#define CK_BUS_TIM16		158
+#define CK_BUS_TIM17		159
+#define CK_BUS_SAI1		160
+#define CK_BUS_SAI2		161
+#define CK_BUS_SAI3		162
+#define CK_BUS_SAI4		163
+#define CK_BUS_USART1		164
+#define CK_BUS_USART6		165
+#define CK_BUS_UART7		166
+#define CK_BUS_FDCAN		167
+#define CK_BUS_SPI1		168
+#define CK_BUS_SPI4		169
+#define CK_BUS_SPI5		170
+#define CK_BUS_SPI6		171
+#define CK_BUS_BSEC		172
+#define CK_BUS_IWDG1		173
+#define CK_BUS_IWDG2		174
+#define CK_BUS_IWDG3		175
+#define CK_BUS_IWDG4		176
+#define CK_BUS_WWDG1		177
+#define CK_BUS_VREF		178
+#define CK_BUS_DTS		179
+#define CK_BUS_SERC		180
+#define CK_BUS_HDP		181
+#define CK_BUS_DDRPERFM		182
+#define CK_BUS_OTG		183
+#define CK_BUS_LTDC		184
+#define CK_BUS_CSI		185
+#define CK_BUS_DCMIPP		186
+#define CK_BUS_DDRC		187
+#define CK_BUS_DDRCFG		188
+#define CK_BUS_STGEN		189
+#define CK_SYSDBG		190
+#define CK_KER_TIM2		191
+#define CK_KER_TIM3		192
+#define CK_KER_TIM4		193
+#define CK_KER_TIM5		194
+#define CK_KER_TIM6		195
+#define CK_KER_TIM7		196
+#define CK_KER_TIM10		197
+#define CK_KER_TIM11		198
+#define CK_KER_TIM12		199
+#define CK_KER_TIM13		200
+#define CK_KER_TIM14		201
+#define CK_KER_TIM1		202
+#define CK_KER_TIM8		203
+#define CK_KER_TIM15		204
+#define CK_KER_TIM16		205
+#define CK_KER_TIM17		206
+#define CK_BUS_SYSRAM		207
+#define CK_BUS_RETRAM		208
+#define CK_BUS_OSPI1		209
+#define CK_BUS_OTFD1		210
+#define CK_BUS_SRAM1		211
+#define CK_BUS_SDMMC1		212
+#define CK_BUS_SDMMC2		213
+#define CK_BUS_SDMMC3		214
+#define CK_BUS_DDR		215
+#define CK_BUS_RISAF4		216
+#define CK_BUS_USBHOHCI		217
+#define CK_BUS_USBHEHCI		218
+#define CK_KER_LPTIM1		219
+#define CK_KER_LPTIM2		220
+#define CK_KER_USART2		221
+#define CK_KER_UART4		222
+#define CK_KER_USART3		223
+#define CK_KER_UART5		224
+#define CK_KER_SPI2		225
+#define CK_KER_SPI3		226
+#define CK_KER_SPDIFRX		227
+#define CK_KER_I2C1		228
+#define CK_KER_I2C2		229
+#define CK_KER_I3C1		230
+#define CK_KER_I3C2		231
+#define CK_KER_I2C3		232
+#define CK_KER_I3C3		233
+#define CK_KER_SPI1		234
+#define CK_KER_SPI4		235
+#define CK_KER_SPI5		236
+#define CK_KER_SPI6		237
+#define CK_KER_USART1		238
+#define CK_KER_USART6		239
+#define CK_KER_UART7		240
+#define CK_KER_MDF1		241
+#define CK_KER_SAI1		242
+#define CK_KER_SAI2		243
+#define CK_KER_SAI3		244
+#define CK_KER_SAI4		245
+#define CK_KER_FDCAN		246
+#define CK_KER_CSI		247
+#define CK_KER_CSITXESC		248
+#define CK_KER_CSIPHY		249
+#define CK_KER_STGEN		250
+#define CK_KER_USB2PHY2EN	251
+#define CK_KER_LPUART1		252
+#define CK_KER_LPTIM3		253
+#define CK_KER_LPTIM4		254
+#define CK_KER_LPTIM5		255
+#define CK_KER_TSDBG		256
+#define CK_KER_TPIU		257
+#define CK_BUS_ETR		258
+#define CK_BUS_SYSATB		259
+#define CK_KER_ADC1		260
+#define CK_KER_ADC2		261
+#define CK_KER_OSPI1		262
+#define CK_KER_FMC		263
+#define CK_KER_SDMMC1		264
+#define CK_KER_SDMMC2		265
+#define CK_KER_SDMMC3		266
+#define CK_KER_ETH1		267
+#define CK_KER_ETH2		268
+#define CK_KER_ETH1PTP		269
+#define CK_KER_ETH2PTP		270
+#define CK_KER_USB2PHY1		271
+#define CK_KER_USB2PHY2		272
+#define CK_MCO1			273
+#define CK_MCO2			274
+#define CK_KER_DTS		275
+#define CK_ETH1_RX		276
+#define CK_ETH1_TX		277
+#define CK_ETH1_MAC		278
+#define CK_ETH2_RX		279
+#define CK_ETH2_TX		280
+#define CK_ETH2_MAC		281
+#define CK_ETH1_STP		282
+#define CK_ETH2_STP		283
+#define CK_KER_LTDC		284
+#define HSE_DIV2_CK		285
+#define CK_DBGMCU		286
+#define CK_DAP			287
+#define CK_KER_ETR		288
+#define CK_KER_STM		289
+
+#define CK_SCMI_ICN_HS_MCU	0
+#define CK_SCMI_ICN_SDMMC	1
+#define CK_SCMI_ICN_DDR		2
+#define CK_SCMI_ICN_DISPLAY	3
+#define CK_SCMI_ICN_HSL		4
+#define CK_SCMI_ICN_NIC		5
+#define CK_SCMI_FLEXGEN_07	7
+#define CK_SCMI_FLEXGEN_08	8
+#define CK_SCMI_FLEXGEN_09	9
+#define CK_SCMI_FLEXGEN_10	10
+#define CK_SCMI_FLEXGEN_11	11
+#define CK_SCMI_FLEXGEN_12	12
+#define CK_SCMI_FLEXGEN_13	13
+#define CK_SCMI_FLEXGEN_14	14
+#define CK_SCMI_FLEXGEN_15	15
+#define CK_SCMI_FLEXGEN_16	16
+#define CK_SCMI_FLEXGEN_17	17
+#define CK_SCMI_FLEXGEN_18	18
+#define CK_SCMI_FLEXGEN_19	19
+#define CK_SCMI_FLEXGEN_20	20
+#define CK_SCMI_FLEXGEN_21	21
+#define CK_SCMI_FLEXGEN_22	22
+#define CK_SCMI_FLEXGEN_23	23
+#define CK_SCMI_FLEXGEN_24	24
+#define CK_SCMI_FLEXGEN_25	25
+#define CK_SCMI_FLEXGEN_26	26
+#define CK_SCMI_FLEXGEN_27	27
+#define CK_SCMI_FLEXGEN_28	28
+#define CK_SCMI_FLEXGEN_29	29
+#define CK_SCMI_FLEXGEN_30	30
+#define CK_SCMI_FLEXGEN_31	31
+#define CK_SCMI_FLEXGEN_32	32
+#define CK_SCMI_FLEXGEN_33	33
+#define CK_SCMI_FLEXGEN_34	34
+#define CK_SCMI_FLEXGEN_35	35
+#define CK_SCMI_FLEXGEN_36	36
+#define CK_SCMI_FLEXGEN_37	37
+#define CK_SCMI_FLEXGEN_38	38
+#define CK_SCMI_FLEXGEN_39	39
+#define CK_SCMI_FLEXGEN_40	40
+#define CK_SCMI_FLEXGEN_41	41
+#define CK_SCMI_FLEXGEN_42	42
+#define CK_SCMI_FLEXGEN_43	43
+#define CK_SCMI_FLEXGEN_44	44
+#define CK_SCMI_FLEXGEN_45	45
+#define CK_SCMI_FLEXGEN_46	46
+#define CK_SCMI_FLEXGEN_47	47
+#define CK_SCMI_FLEXGEN_48	48
+#define CK_SCMI_FLEXGEN_49	49
+#define CK_SCMI_FLEXGEN_50	50
+#define CK_SCMI_FLEXGEN_51	51
+#define CK_SCMI_FLEXGEN_52	52
+#define CK_SCMI_FLEXGEN_53	53
+#define CK_SCMI_FLEXGEN_54	54
+#define CK_SCMI_FLEXGEN_55	55
+#define CK_SCMI_FLEXGEN_56	56
+#define CK_SCMI_FLEXGEN_57	57
+#define CK_SCMI_FLEXGEN_58	58
+#define CK_SCMI_FLEXGEN_59	59
+#define CK_SCMI_FLEXGEN_60	60
+#define CK_SCMI_FLEXGEN_61	61
+#define CK_SCMI_FLEXGEN_62	62
+#define CK_SCMI_FLEXGEN_63	63
+#define CK_SCMI_ICN_LS_MCU	64
+#define CK_SCMI_HSE		65
+#define CK_SCMI_LSE		66
+#define CK_SCMI_HSI		67
+#define CK_SCMI_LSI		68
+#define CK_SCMI_MSI		69
+#define CK_SCMI_HSE_DIV2	70
+#define CK_SCMI_CPU1		71
+#define CK_SCMI_SYSCPU1		72
+#define CK_SCMI_PLL2		73
+#define CK_SCMI_RTC		74
+#define CK_SCMI_RTCCK		75
+#define CK_SCMI_ICN_APB1	76
+#define CK_SCMI_ICN_APB2	77
+#define CK_SCMI_ICN_APB3	78
+#define CK_SCMI_ICN_APB4	79
+#define CK_SCMI_ICN_APB5	80
+#define CK_SCMI_ICN_APBDBG	81
+#define CK_SCMI_TIMG1		82
+#define CK_SCMI_TIMG2		83
+#define CK_SCMI_BKPSRAM		84
+#define CK_SCMI_BSEC		85
+#define CK_SCMI_BUS_ETR		86
+#define CK_SCMI_FMC		87
+#define CK_SCMI_GPIOA		88
+#define CK_SCMI_GPIOB		89
+#define CK_SCMI_GPIOC		90
+#define CK_SCMI_GPIOD		91
+#define CK_SCMI_GPIOE		92
+#define CK_SCMI_GPIOF		93
+#define CK_SCMI_GPIOG		94
+#define CK_SCMI_GPIOH		95
+#define CK_SCMI_GPIOI		96
+#define CK_SCMI_GPIOZ		97
+#define CK_SCMI_HPDMA1		98
+#define CK_SCMI_HPDMA2		99
+#define CK_SCMI_HPDMA3		100
+#define CK_SCMI_IPCC1		101
+#define CK_SCMI_RETRAM		102
+#define CK_SCMI_SRAM1		103
+#define CK_SCMI_SYSRAM		104
+#define CK_SCMI_OSPI1		105
+#define CK_SCMI_TPIU		106
+#define CK_SCMI_SYSDBG		107
+#define CK_SCMI_SYSATB		108
+#define CK_SCMI_TSDBG		109
+#define CK_SCMI_BUS_STM		110
+#define CK_SCMI_KER_STM		111
+#define CK_SCMI_KER_ETR		112
+
+#endif /* _DT_BINDINGS_STM32MP21_CLKS_H_ */
diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h
index c8259ac5ada..54808fcfd55 100644
--- a/include/dt-bindings/clock/sun55i-a523-ccu.h
+++ b/include/dt-bindings/clock/sun55i-a523-ccu.h
@@ -185,5 +185,6 @@
 #define CLK_FANOUT0		176
 #define CLK_FANOUT1		177
 #define CLK_FANOUT2		178
+#define CLK_NPU			179
 
 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */
diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h
new file mode 100644
index 00000000000..6efc6bc7e11
--- /dev/null
+++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Chen-Yu Tsai <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
+#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_
+
+#define CLK_MCU_PLL_AUDIO1	0
+#define CLK_MCU_PLL_AUDIO1_DIV2	1
+#define CLK_MCU_PLL_AUDIO1_DIV5	2
+#define CLK_MCU_AUDIO_OUT	3
+#define CLK_MCU_DSP		4
+#define CLK_MCU_I2S0		5
+#define CLK_MCU_I2S1		6
+#define CLK_MCU_I2S2		7
+#define CLK_MCU_I2S3		8
+#define CLK_MCU_I2S3_ASRC	9
+#define CLK_BUS_MCU_I2S0	10
+#define CLK_BUS_MCU_I2S1	11
+#define CLK_BUS_MCU_I2S2	12
+#define CLK_BUS_MCU_I2S3	13
+#define CLK_MCU_SPDIF_TX	14
+#define CLK_MCU_SPDIF_RX	15
+#define CLK_BUS_MCU_SPDIF	16
+#define CLK_MCU_DMIC		17
+#define CLK_BUS_MCU_DMIC	18
+#define CLK_MCU_AUDIO_CODEC_DAC	19
+#define CLK_MCU_AUDIO_CODEC_ADC	20
+#define CLK_BUS_MCU_AUDIO_CODEC	21
+#define CLK_BUS_MCU_DSP_MSGBOX	22
+#define CLK_BUS_MCU_DSP_CFG	23
+#define CLK_BUS_MCU_NPU_HCLK	24
+#define CLK_BUS_MCU_NPU_ACLK	25
+#define CLK_MCU_TIMER0		26
+#define CLK_MCU_TIMER1		27
+#define CLK_MCU_TIMER2		28
+#define CLK_MCU_TIMER3		29
+#define CLK_MCU_TIMER4		30
+#define CLK_MCU_TIMER5		31
+#define CLK_BUS_MCU_TIMER	32
+#define CLK_BUS_MCU_DMA		33
+#define CLK_MCU_TZMA0		34
+#define CLK_MCU_TZMA1		35
+#define CLK_BUS_MCU_PUBSRAM	36
+#define CLK_MCU_MBUS_DMA	37
+#define CLK_MCU_MBUS		38
+#define CLK_MCU_RISCV		39
+#define CLK_BUS_MCU_RISCV_CFG	40
+#define CLK_BUS_MCU_RISCV_MSGBOX	41
+#define CLK_MCU_PWM0		42
+#define CLK_BUS_MCU_PWM0	43
+
+#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index f193663e6f2..763b81f8090 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -271,6 +271,7 @@
 #define TEGRA30_CLK_AUDIO3_MUX 306
 #define TEGRA30_CLK_AUDIO4_MUX 307
 #define TEGRA30_CLK_SPDIF_MUX 308
-#define TEGRA30_CLK_CLK_MAX 309
+#define TEGRA30_CLK_CSIA_PAD 309
+#define TEGRA30_CLK_CSIB_PAD 310
 
 #endif	/* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/gpio/tegra256-gpio.h b/include/dt-bindings/gpio/tegra256-gpio.h
new file mode 100644
index 00000000000..a0353a302ae
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra256-gpio.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
+
+/*
+ * This header provides constants for the nvidia,tegra256-gpio DT binding.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID.
+ * The macros below provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA256_MAIN_GPIO_PORT_A 0
+#define TEGRA256_MAIN_GPIO_PORT_B 1
+#define TEGRA256_MAIN_GPIO_PORT_C 2
+#define TEGRA256_MAIN_GPIO_PORT_D 3
+
+#define TEGRA256_MAIN_GPIO(port, offset) \
+		((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset))
+
+#endif
+
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index ca5851e97fa..30f3c9eaafa 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -27,6 +27,7 @@
 #define INPUT_PROP_TOPBUTTONPAD		0x04	/* softbuttons at top of pad */
 #define INPUT_PROP_POINTING_STICK	0x05	/* is a pointing stick */
 #define INPUT_PROP_ACCELEROMETER	0x06	/* has accelerometer */
+#define INPUT_PROP_PRESSUREPAD		0x07	/* pressure triggers clicks */
 
 #define INPUT_PROP_MAX			0x1f
 #define INPUT_PROP_CNT			(INPUT_PROP_MAX + 1)
@@ -630,6 +631,18 @@
 #define KEY_BRIGHTNESS_MIN		0x250	/* Set Brightness to Minimum */
 #define KEY_BRIGHTNESS_MAX		0x251	/* Set Brightness to Maximum */
 
+/*
+ * Keycodes for hotkeys toggling the electronic privacy screen found on some
+ * laptops on/off. Note when the embedded-controller turns on/off the eprivacy
+ * screen itself then the state should be reported through drm connecter props:
+ * https://www.kernel.org/doc/html/latest/gpu/drm-kms.html#standard-connector-properties
+ * Except when implementing the drm connecter properties API is not possible
+ * because e.g. the firmware does not allow querying the presence and/or status
+ * of the eprivacy screen at boot.
+ */
+#define KEY_EPRIVACY_SCREEN_ON		0x252
+#define KEY_EPRIVACY_SCREEN_OFF		0x253
+
 #define KEY_KBDINPUTASSIST_PREV		0x260
 #define KEY_KBDINPUTASSIST_NEXT		0x261
 #define KEY_KBDINPUTASSIST_PREVGROUP		0x262
diff --git a/include/dt-bindings/interconnect/qcom,glymur-rpmh.h b/include/dt-bindings/interconnect/qcom,glymur-rpmh.h
new file mode 100644
index 00000000000..6a0e754345e
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,glymur-rpmh.h
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_GLYMUR_H
+
+#define MASTER_CRYPTO				0
+#define MASTER_SOCCP_PROC			1
+#define MASTER_QDSS_ETR				2
+#define MASTER_QDSS_ETR_1			3
+#define SLAVE_A1NOC_SNOC			4
+
+#define MASTER_UFS_MEM				0
+#define MASTER_USB3_2				1
+#define MASTER_USB4_2				2
+#define SLAVE_A2NOC_SNOC			3
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_0				1
+#define MASTER_QUP_1				2
+#define MASTER_QUP_2				3
+#define MASTER_SP				4
+#define MASTER_SDCC_2				5
+#define MASTER_SDCC_4				6
+#define MASTER_USB2				7
+#define MASTER_USB3_MP				8
+#define SLAVE_A3NOC_SNOC			9
+
+#define MASTER_USB3_0				0
+#define MASTER_USB3_1				1
+#define MASTER_USB4_0				2
+#define MASTER_USB4_1				3
+#define SLAVE_A4NOC_HSCNOC			4
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define MASTER_QUP_CORE_2			2
+#define SLAVE_QUP_CORE_0			3
+#define SLAVE_QUP_CORE_1			4
+#define SLAVE_QUP_CORE_2			5
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_AHB2PHY_2				3
+#define SLAVE_AHB2PHY_3				4
+#define SLAVE_AV1_ENC_CFG			5
+#define SLAVE_CAMERA_CFG			6
+#define SLAVE_CLK_CTL				7
+#define SLAVE_CRYPTO_0_CFG			8
+#define SLAVE_DISPLAY_CFG			9
+#define SLAVE_GFX3D_CFG				10
+#define SLAVE_IMEM_CFG				11
+#define SLAVE_PCIE_0_CFG			12
+#define SLAVE_PCIE_1_CFG			13
+#define SLAVE_PCIE_2_CFG			14
+#define SLAVE_PCIE_3A_CFG			15
+#define SLAVE_PCIE_3B_CFG			16
+#define SLAVE_PCIE_4_CFG			17
+#define SLAVE_PCIE_5_CFG			18
+#define SLAVE_PCIE_6_CFG			19
+#define SLAVE_PCIE_RSCC				20
+#define SLAVE_PDM				21
+#define SLAVE_PRNG				22
+#define SLAVE_QDSS_CFG				23
+#define SLAVE_QSPI_0				24
+#define SLAVE_QUP_0				25
+#define SLAVE_QUP_1				26
+#define SLAVE_QUP_2				27
+#define SLAVE_SDCC_2				28
+#define SLAVE_SDCC_4				29
+#define SLAVE_SMMUV3_CFG			30
+#define SLAVE_TCSR				31
+#define SLAVE_TLMM				32
+#define SLAVE_UFS_MEM_CFG			33
+#define SLAVE_USB2				34
+#define SLAVE_USB3_0				35
+#define SLAVE_USB3_1				36
+#define SLAVE_USB3_2				37
+#define SLAVE_USB3_MP				38
+#define SLAVE_USB4_0				39
+#define SLAVE_USB4_1				40
+#define SLAVE_USB4_2				41
+#define SLAVE_VENUS_CFG				42
+#define SLAVE_CNOC_PCIE_SLAVE_EAST_CFG		43
+#define SLAVE_CNOC_PCIE_SLAVE_WEST_CFG		44
+#define SLAVE_LPASS_QTB_CFG			45
+#define SLAVE_CNOC_MNOC_CFG			46
+#define SLAVE_NSP_QTB_CFG			47
+#define SLAVE_PCIE_EAST_ANOC_CFG		48
+#define SLAVE_PCIE_WEST_ANOC_CFG		49
+#define SLAVE_QDSS_STM				50
+#define SLAVE_TCU				51
+
+#define MASTER_HSCNOC_CNOC			0
+#define SLAVE_AOSS				1
+#define SLAVE_IPC_ROUTER_CFG			2
+#define SLAVE_SOCCP				3
+#define SLAVE_TME_CFG				4
+#define SLAVE_APPSS				5
+#define SLAVE_CNOC_CFG				6
+#define SLAVE_BOOT_IMEM				7
+#define SLAVE_IMEM				8
+
+#define MASTER_GPU_TCU				0
+#define MASTER_PCIE_TCU				1
+#define MASTER_SYS_TCU				2
+#define MASTER_APPSS_PROC			3
+#define MASTER_AGGRE_NOC_EAST			4
+#define MASTER_GFX3D				5
+#define MASTER_LPASS_GEM_NOC			6
+#define MASTER_MNOC_HF_MEM_NOC			7
+#define MASTER_MNOC_SF_MEM_NOC			8
+#define MASTER_COMPUTE_NOC			9
+#define MASTER_PCIE_EAST			10
+#define MASTER_PCIE_WEST			11
+#define MASTER_SNOC_SF_MEM_NOC			12
+#define MASTER_WLAN_Q6				13
+#define MASTER_GIC				14
+#define SLAVE_HSCNOC_CNOC			15
+#define SLAVE_LLCC				16
+#define SLAVE_PCIE_EAST				17
+#define SLAVE_PCIE_WEST				18
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_AV1_ENC				0
+#define MASTER_CAMNOC_HF			1
+#define MASTER_CAMNOC_ICP			2
+#define MASTER_CAMNOC_SF			3
+#define MASTER_EVA				4
+#define MASTER_MDP				5
+#define MASTER_CDSP_HCP				6
+#define MASTER_VIDEO				7
+#define MASTER_VIDEO_CV_PROC			8
+#define MASTER_VIDEO_V_PROC			9
+#define MASTER_CNOC_MNOC_CFG			10
+#define SLAVE_MNOC_HF_MEM_NOC			11
+#define SLAVE_MNOC_SF_MEM_NOC			12
+#define SLAVE_SERVICE_MNOC			13
+
+#define MASTER_CPUCP				0
+#define SLAVE_NSINOC_SYSTEM_NOC			1
+#define SLAVE_SERVICE_NSINOC			2
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_NSP0_HSC_NOC			1
+
+#define MASTER_OOBMSS_SP_PROC			0
+#define SLAVE_OOBMSS_SNOC			1
+
+#define MASTER_PCIE_EAST_ANOC_CFG		0
+#define MASTER_PCIE_0				1
+#define MASTER_PCIE_1				2
+#define MASTER_PCIE_5				3
+#define SLAVE_PCIE_EAST_MEM_NOC			4
+#define SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC	5
+
+#define MASTER_HSCNOC_PCIE_EAST			0
+#define MASTER_CNOC_PCIE_EAST_SLAVE_CFG		1
+#define SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG	2
+#define SLAVE_SERVICE_PCIE_EAST			3
+#define SLAVE_PCIE_0				4
+#define SLAVE_PCIE_1				5
+#define SLAVE_PCIE_5				6
+
+#define MASTER_PCIE_WEST_ANOC_CFG		0
+#define MASTER_PCIE_2				1
+#define MASTER_PCIE_3A				2
+#define MASTER_PCIE_3B				3
+#define MASTER_PCIE_4				4
+#define MASTER_PCIE_6				5
+#define SLAVE_PCIE_WEST_MEM_NOC			6
+#define SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC	7
+
+#define MASTER_HSCNOC_PCIE_WEST			0
+#define MASTER_CNOC_PCIE_WEST_SLAVE_CFG		1
+#define SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG	2
+#define SLAVE_SERVICE_PCIE_WEST			3
+#define SLAVE_PCIE_2				4
+#define SLAVE_PCIE_3A				5
+#define SLAVE_PCIE_3B				6
+#define SLAVE_PCIE_4				7
+#define SLAVE_PCIE_6				8
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define MASTER_A3NOC_SNOC			2
+#define MASTER_NSINOC_SNOC			3
+#define MASTER_OOBMSS				4
+#define SLAVE_SNOC_GEM_NOC_SF			5
+
+#endif
diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h
index a770356112e..afd7e0683a2 100644
--- a/include/dt-bindings/interconnect/qcom,ipq5424.h
+++ b/include/dt-bindings/interconnect/qcom,ipq5424.h
@@ -21,4 +21,7 @@
 #define MASTER_CNOC_USB			16
 #define SLAVE_CNOC_USB			17
 
+#define MASTER_CPU			0
+#define SLAVE_L3			1
+
 #endif /* INTERCONNECT_QCOM_IPQ5424_H */
diff --git a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
index f315d5a7f5e..7dd04424afc 100644
--- a/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
+++ b/include/dt-bindings/interrupt-controller/aspeed-scu-ic.h
@@ -20,4 +20,18 @@
 #define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI	0
 #define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO	1
 
+#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_LO_TO_HI	3
+#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_HI_TO_LO	2
+
+#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_LO_TO_HI	3
+#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_HI_TO_LO	2
+
+#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_LO_TO_HI	3
+#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_HI_TO_LO	2
+#define ASPEED_AST2700_SCU_IC2_LPC_RESET_LO_TO_HI	1
+#define ASPEED_AST2700_SCU_IC2_LPC_RESET_HI_TO_LO	0
+
+#define ASPEED_AST2700_SCU_IC3_LPC_RESET_LO_TO_HI	1
+#define ASPEED_AST2700_SCU_IC3_LPC_RESET_HI_TO_LO	0
+
 #endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */
diff --git a/include/dt-bindings/media/tvp5150.h b/include/dt-bindings/media/tvp5150.h
index dda00c03853..ba34c420c30 100644
--- a/include/dt-bindings/media/tvp5150.h
+++ b/include/dt-bindings/media/tvp5150.h
@@ -2,7 +2,7 @@
 /*
     tvp5150.h - definition for tvp5150 inputs
 
-    Copyright (C) 2006 Hans Verkuil ([email protected])
+    Copyright (C) 2006 Hans Verkuil ([email protected])
 
 */
 
diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
index 5e082547f17..881bf78aa8b 100644
--- a/include/dt-bindings/memory/tegra210-mc.h
+++ b/include/dt-bindings/memory/tegra210-mc.h
@@ -75,4 +75,78 @@
 #define TEGRA210_MC_RESET_ETR		28
 #define TEGRA210_MC_RESET_TSECB		29
 
+#define TEGRA210_MC_PTCR		0
+#define TEGRA210_MC_DISPLAY0A		1
+#define TEGRA210_MC_DISPLAY0AB		2
+#define TEGRA210_MC_DISPLAY0B		3
+#define TEGRA210_MC_DISPLAY0BB		4
+#define TEGRA210_MC_DISPLAY0C		5
+#define TEGRA210_MC_DISPLAY0CB		6
+#define TEGRA210_MC_AFIR		14
+#define TEGRA210_MC_AVPCARM7R		15
+#define TEGRA210_MC_DISPLAYHC		16
+#define TEGRA210_MC_DISPLAYHCB		17
+#define TEGRA210_MC_HDAR		21
+#define TEGRA210_MC_HOST1XDMAR		22
+#define TEGRA210_MC_HOST1XR		23
+#define TEGRA210_MC_NVENCSRD		28
+#define TEGRA210_MC_PPCSAHBDMAR		29
+#define TEGRA210_MC_PPCSAHBSLVR		30
+#define TEGRA210_MC_SATAR		31
+#define TEGRA210_MC_MPCORER		39
+#define TEGRA210_MC_NVENCSWR		43
+#define TEGRA210_MC_AFIW		49
+#define TEGRA210_MC_AVPCARM7W		50
+#define TEGRA210_MC_HDAW		53
+#define TEGRA210_MC_HOST1XW		54
+#define TEGRA210_MC_MPCOREW		57
+#define TEGRA210_MC_PPCSAHBDMAW		59
+#define TEGRA210_MC_PPCSAHBSLVW		60
+#define TEGRA210_MC_SATAW		61
+#define TEGRA210_MC_ISPRA		68
+#define TEGRA210_MC_ISPWA		70
+#define TEGRA210_MC_ISPWB		71
+#define TEGRA210_MC_XUSB_HOSTR		74
+#define TEGRA210_MC_XUSB_HOSTW		75
+#define TEGRA210_MC_XUSB_DEVR		76
+#define TEGRA210_MC_XUSB_DEVW		77
+#define TEGRA210_MC_ISPRAB		78
+#define TEGRA210_MC_ISPWAB		80
+#define TEGRA210_MC_ISPWBB		81
+#define TEGRA210_MC_TSECSRD		84
+#define TEGRA210_MC_TSECSWR		85
+#define TEGRA210_MC_A9AVPSCR		86
+#define TEGRA210_MC_A9AVPSCW		87
+#define TEGRA210_MC_GPUSRD		88
+#define TEGRA210_MC_GPUSWR		89
+#define TEGRA210_MC_DISPLAYT		90
+#define TEGRA210_MC_SDMMCRA		96
+#define TEGRA210_MC_SDMMCRAA		97
+#define TEGRA210_MC_SDMMCR		98
+#define TEGRA210_MC_SDMMCRAB		99
+#define TEGRA210_MC_SDMMCWA		100
+#define TEGRA210_MC_SDMMCWAA		101
+#define TEGRA210_MC_SDMMCW		102
+#define TEGRA210_MC_SDMMCWAB		103
+#define TEGRA210_MC_VICSRD		108
+#define TEGRA210_MC_VICSWR		109
+#define TEGRA210_MC_VIW			114
+#define TEGRA210_MC_DISPLAYD		115
+#define TEGRA210_MC_NVDECSRD		120
+#define TEGRA210_MC_NVDECSWR		121
+#define TEGRA210_MC_APER		122
+#define TEGRA210_MC_APEW		123
+#define TEGRA210_MC_NVJPGRD		126
+#define TEGRA210_MC_NVJPGWR		127
+#define TEGRA210_MC_SESRD		128
+#define TEGRA210_MC_SESWR		129
+#define TEGRA210_MC_AXIAPR		130
+#define TEGRA210_MC_AXIAPW		131
+#define TEGRA210_MC_ETRR		132
+#define TEGRA210_MC_ETRW		133
+#define TEGRA210_MC_TSECSRDB		134
+#define TEGRA210_MC_TSECSWRB		135
+#define TEGRA210_MC_GPUSRD2		136
+#define TEGRA210_MC_GPUSWR2		137
+
 #endif
diff --git a/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h
new file mode 100644
index 00000000000..43a2b5743a6
--- /dev/null
+++ b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corporation.
+ */
+
+#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
+#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H
+
+/*
+ * Media Interface Connection Matrix
+ * ===========================================================
+ *
+ * Selects the function of the Media interface of the MAC to be used
+ *
+ * SW_MODE[2:0] | Port 0      | Port 1      | Port 2      | Port 3
+ * -------------|-------------|-------------|-------------|-------------
+ * 000b         | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1
+ * 001b         | ESC Port0   | ESC Port1   | GMAC2       | GMAC1
+ * 010b         | ESC Port0   | ESC Port1   | ETHSW Port2 | GMAC1
+ * 011b         | ESC Port0   | ESC Port1   | ESC Port2   | GMAC1
+ * 100b         | ETHSW Port0 | ESC Port1   | ESC Port2   | GMAC1
+ * 101b         | ETHSW Port0 | ESC Port1   | ETHSW Port2 | GMAC1
+ * 110b         | ETHSW Port0 | ETHSW Port1 | GMAC2       | GMAC1
+ * 111b         | GMAC0       | GMAC1       | GMAC2       | -
+ */
+#define ETHSS_GMAC0_PORT		0
+#define ETHSS_GMAC1_PORT		1
+#define ETHSS_GMAC2_PORT		2
+#define ETHSS_ESC_PORT0			3
+#define ETHSS_ESC_PORT1			4
+#define ETHSS_ESC_PORT2			5
+#define ETHSS_ETHSW_PORT0		6
+#define ETHSS_ETHSW_PORT1		7
+#define ETHSS_ETHSW_PORT2		8
+
+#endif
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
new file mode 100644
index 00000000000..f088793f23e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/T2H family pinctrl bindings.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__
+
+#define RZT2H_PINS_PER_PORT	8
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZT2H_PORT_PINMUX(b, p, f)	((b) * RZT2H_PINS_PER_PORT + (p) | ((f) << 16))
+
+/* Convert a port and pin label to its global pin index */
+#define RZT2H_GPIO(port, pin)	((port) * RZT2H_PINS_PER_PORT + (pin))
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G077_PINCTRL_H__ */
diff --git a/include/dt-bindings/power/amlogic,s6-pwrc.h b/include/dt-bindings/power/amlogic,s6-pwrc.h
new file mode 100644
index 00000000000..2c005864ae7
--- /dev/null
+++ b/include/dt-bindings/power/amlogic,s6-pwrc.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Amlogic, Inc. All rights reserved
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_S6_POWER_H
+#define _DT_BINDINGS_AMLOGIC_S6_POWER_H
+
+#define PWRC_S6_DSPA_ID				0
+#define PWRC_S6_DOS_HEVC_ID			1
+#define PWRC_S6_DOS_VDEC_ID			2
+#define PWRC_S6_VPU_HDMI_ID			3
+#define PWRC_S6_U2DRD_ID			4
+#define PWRC_S6_U3DRD_ID			5
+#define PWRC_S6_SD_EMMC_C_ID			6
+#define PWRC_S6_GE2D_ID				7
+#define PWRC_S6_AMFC_ID				8
+#define PWRC_S6_VC9000E_ID			9
+#define PWRC_S6_DEWARP_ID			10
+#define PWRC_S6_VICP_ID				11
+#define PWRC_S6_SD_EMMC_A_ID			12
+#define PWRC_S6_SD_EMMC_B_ID			13
+#define PWRC_S6_ETH_ID				14
+#define PWRC_S6_PCIE_ID				15
+#define PWRC_S6_NNA_4T_ID			16
+#define PWRC_S6_AUDIO_ID			17
+#define PWRC_S6_AUCPU_ID			18
+#define PWRC_S6_ADAPT_ID			19
+
+#endif
diff --git a/include/dt-bindings/power/amlogic,s7-pwrc.h b/include/dt-bindings/power/amlogic,s7-pwrc.h
new file mode 100644
index 00000000000..3f21d095f78
--- /dev/null
+++ b/include/dt-bindings/power/amlogic,s7-pwrc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Amlogic, Inc. All rights reserved
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_S7_POWER_H
+#define _DT_BINDINGS_AMLOGIC_S7_POWER_H
+
+#define PWRC_S7_DOS_HEVC_ID			0
+#define PWRC_S7_DOS_VDEC_ID		        1
+#define PWRC_S7_VPU_HDMI_ID		        2
+#define PWRC_S7_USB_COMB_ID		        3
+#define PWRC_S7_SD_EMMC_C_ID			4
+#define PWRC_S7_GE2D_ID				5
+#define PWRC_S7_SD_EMMC_A_ID			6
+#define PWRC_S7_SD_EMMC_B_ID			7
+#define PWRC_S7_ETH_ID				8
+#define PWRC_S7_AUCPU_ID			9
+#define PWRC_S7_AUDIO_ID			10
+
+#endif
diff --git a/include/dt-bindings/power/amlogic,s7d-pwrc.h b/include/dt-bindings/power/amlogic,s7d-pwrc.h
new file mode 100644
index 00000000000..c6998553670
--- /dev/null
+++ b/include/dt-bindings/power/amlogic,s7d-pwrc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Amlogic, Inc. All rights reserved
+ */
+#ifndef _DT_BINDINGS_AMLOGIC_S7D_POWER_H
+#define _DT_BINDINGS_AMLOGIC_S7D_POWER_H
+
+#define PWRC_S7D_DOS_HCODEC_ID			0
+#define PWRC_S7D_DOS_HEVC_ID			1
+#define PWRC_S7D_DOS_VDEC_ID			2
+#define PWRC_S7D_VPU_HDMI_ID			3
+#define PWRC_S7D_USB_U2DRD_ID			4
+#define PWRC_S7D_USB_U2H_ID			5
+#define PWRC_S7D_SSD_EMMC_C_ID			6
+#define PWRC_S7D_GE2D_ID			7
+#define PWRC_S7D_AMFC_ID			8
+#define PWRC_S7D_EMMC_A_ID			9
+#define PWRC_S7D_EMMC_B_ID			10
+#define PWRC_S7D_ETH_ID				11
+#define PWRC_S7D_AUCPU_ID			12
+#define PWRC_S7D_AUDIO_ID			13
+#define PWRC_S7D_SRAMA_ID			14
+#define PWRC_S7D_DMC0_ID			15
+#define PWRC_S7D_DMC1_ID			16
+#define PWRC_S7D_DDR_ID				17
+
+#endif
diff --git a/include/dt-bindings/power/marvell,pxa1908-power.h b/include/dt-bindings/power/marvell,pxa1908-power.h
new file mode 100644
index 00000000000..19b088351af
--- /dev/null
+++ b/include/dt-bindings/power/marvell,pxa1908-power.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Marvell PXA1908 power domains
+ *
+ * Copyright 2025, Duje Mihanović <[email protected]>
+ */
+
+#ifndef __DTS_MARVELL_PXA1908_POWER_H
+#define __DTS_MARVELL_PXA1908_POWER_H
+
+#define PXA1908_POWER_DOMAIN_VPU	0
+#define PXA1908_POWER_DOMAIN_GPU	1
+#define PXA1908_POWER_DOMAIN_GPU2D	2
+#define PXA1908_POWER_DOMAIN_DSI	3
+#define PXA1908_POWER_DOMAIN_ISP	4
+
+#endif
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index e54ffa36145..73cceb88953 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -29,4 +29,237 @@
 #define RPMHPD_NSP2             19
 #define RPMHPD_GMXC		20
 
+/* RPMh Power Domain performance levels */
+#define RPMH_REGULATOR_LEVEL_RETENTION		16
+#define RPMH_REGULATOR_LEVEL_MIN_SVS		48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3		50
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
+#define RPMH_REGULATOR_LEVEL_LOW_SVS		64
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1		80
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2		96
+#define RPMH_REGULATOR_LEVEL_SVS		128
+#define RPMH_REGULATOR_LEVEL_SVS_L0		144
+#define RPMH_REGULATOR_LEVEL_SVS_L1		192
+#define RPMH_REGULATOR_LEVEL_SVS_L2		224
+#define RPMH_REGULATOR_LEVEL_NOM		256
+#define RPMH_REGULATOR_LEVEL_NOM_L0		288
+#define RPMH_REGULATOR_LEVEL_NOM_L1		320
+#define RPMH_REGULATOR_LEVEL_NOM_L2		336
+#define RPMH_REGULATOR_LEVEL_TURBO		384
+#define RPMH_REGULATOR_LEVEL_TURBO_L0		400
+#define RPMH_REGULATOR_LEVEL_TURBO_L1		416
+#define RPMH_REGULATOR_LEVEL_TURBO_L2		432
+#define RPMH_REGULATOR_LEVEL_TURBO_L3		448
+#define RPMH_REGULATOR_LEVEL_TURBO_L4		452
+#define RPMH_REGULATOR_LEVEL_TURBO_L5		456
+#define RPMH_REGULATOR_LEVEL_SUPER_TURBO	464
+#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
+
+/*
+ * Platform-specific power domain bindings. Don't add new entries here, use
+ * RPMHPD_* above.
+ */
+
+/* SA8775P Power Domain Indexes */
+#define SA8775P_CX	0
+#define SA8775P_CX_AO	1
+#define SA8775P_DDR	2
+#define SA8775P_EBI	3
+#define SA8775P_GFX	4
+#define SA8775P_LCX	5
+#define SA8775P_LMX	6
+#define SA8775P_MMCX	7
+#define SA8775P_MMCX_AO	8
+#define SA8775P_MSS	9
+#define SA8775P_MX	10
+#define SA8775P_MX_AO	11
+#define SA8775P_MXC	12
+#define SA8775P_MXC_AO	13
+#define SA8775P_NSP0	14
+#define SA8775P_NSP1	15
+#define SA8775P_XO	16
+
+/* SDM670 Power Domain Indexes */
+#define SDM670_MX	0
+#define SDM670_MX_AO	1
+#define SDM670_CX	2
+#define SDM670_CX_AO	3
+#define SDM670_LMX	4
+#define SDM670_LCX	5
+#define SDM670_GFX	6
+#define SDM670_MSS	7
+
+/* SDM845 Power Domain Indexes */
+#define SDM845_EBI	0
+#define SDM845_MX	1
+#define SDM845_MX_AO	2
+#define SDM845_CX	3
+#define SDM845_CX_AO	4
+#define SDM845_LMX	5
+#define SDM845_LCX	6
+#define SDM845_GFX	7
+#define SDM845_MSS	8
+
+/* SDX55 Power Domain Indexes */
+#define SDX55_MSS	0
+#define SDX55_MX	1
+#define SDX55_CX	2
+
+/* SDX65 Power Domain Indexes */
+#define SDX65_MSS	0
+#define SDX65_MX	1
+#define SDX65_MX_AO	2
+#define SDX65_CX	3
+#define SDX65_CX_AO	4
+#define SDX65_MXC	5
+
+/* SM6350 Power Domain Indexes */
+#define SM6350_CX	0
+#define SM6350_GFX	1
+#define SM6350_LCX	2
+#define SM6350_LMX	3
+#define SM6350_MSS	4
+#define SM6350_MX	5
+
+/* SM8150 Power Domain Indexes */
+#define SM8150_MSS	0
+#define SM8150_EBI	1
+#define SM8150_LMX	2
+#define SM8150_LCX	3
+#define SM8150_GFX	4
+#define SM8150_MX	5
+#define SM8150_MX_AO	6
+#define SM8150_CX	7
+#define SM8150_CX_AO	8
+#define SM8150_MMCX	9
+#define SM8150_MMCX_AO	10
+
+/* SA8155P is a special case, kept for backwards compatibility */
+#define SA8155P_CX	SM8150_CX
+#define SA8155P_CX_AO	SM8150_CX_AO
+#define SA8155P_EBI	SM8150_EBI
+#define SA8155P_GFX	SM8150_GFX
+#define SA8155P_MSS	SM8150_MSS
+#define SA8155P_MX	SM8150_MX
+#define SA8155P_MX_AO	SM8150_MX_AO
+
+/* SM8250 Power Domain Indexes */
+#define SM8250_CX	0
+#define SM8250_CX_AO	1
+#define SM8250_EBI	2
+#define SM8250_GFX	3
+#define SM8250_LCX	4
+#define SM8250_LMX	5
+#define SM8250_MMCX	6
+#define SM8250_MMCX_AO	7
+#define SM8250_MX	8
+#define SM8250_MX_AO	9
+
+/* SM8350 Power Domain Indexes */
+#define SM8350_CX	0
+#define SM8350_CX_AO	1
+#define SM8350_EBI	2
+#define SM8350_GFX	3
+#define SM8350_LCX	4
+#define SM8350_LMX	5
+#define SM8350_MMCX	6
+#define SM8350_MMCX_AO	7
+#define SM8350_MX	8
+#define SM8350_MX_AO	9
+#define SM8350_MXC	10
+#define SM8350_MXC_AO	11
+#define SM8350_MSS	12
+
+/* SM8450 Power Domain Indexes */
+#define SM8450_CX	0
+#define SM8450_CX_AO	1
+#define SM8450_EBI	2
+#define SM8450_GFX	3
+#define SM8450_LCX	4
+#define SM8450_LMX	5
+#define SM8450_MMCX	6
+#define SM8450_MMCX_AO	7
+#define SM8450_MX	8
+#define SM8450_MX_AO	9
+#define SM8450_MXC	10
+#define SM8450_MXC_AO	11
+#define SM8450_MSS	12
+
+/* SM8550 Power Domain Indexes */
+#define SM8550_CX	0
+#define SM8550_CX_AO	1
+#define SM8550_EBI	2
+#define SM8550_GFX	3
+#define SM8550_LCX	4
+#define SM8550_LMX	5
+#define SM8550_MMCX	6
+#define SM8550_MMCX_AO	7
+#define SM8550_MX	8
+#define SM8550_MX_AO	9
+#define SM8550_MXC	10
+#define SM8550_MXC_AO	11
+#define SM8550_MSS	12
+#define SM8550_NSP	13
+
+/* QDU1000/QRU1000 Power Domain Indexes */
+#define QDU1000_EBI	0
+#define QDU1000_MSS	1
+#define QDU1000_CX	2
+#define QDU1000_MX	3
+
+/* SC7180 Power Domain Indexes */
+#define SC7180_CX	0
+#define SC7180_CX_AO	1
+#define SC7180_GFX	2
+#define SC7180_MX	3
+#define SC7180_MX_AO	4
+#define SC7180_LMX	5
+#define SC7180_LCX	6
+#define SC7180_MSS	7
+
+/* SC7280 Power Domain Indexes */
+#define SC7280_CX	0
+#define SC7280_CX_AO	1
+#define SC7280_EBI	2
+#define SC7280_GFX	3
+#define SC7280_MX	4
+#define SC7280_MX_AO	5
+#define SC7280_LMX	6
+#define SC7280_LCX	7
+#define SC7280_MSS	8
+
+/* SC8180X Power Domain Indexes */
+#define SC8180X_CX	0
+#define SC8180X_CX_AO	1
+#define SC8180X_EBI	2
+#define SC8180X_GFX	3
+#define SC8180X_LCX	4
+#define SC8180X_LMX	5
+#define SC8180X_MMCX	6
+#define SC8180X_MMCX_AO	7
+#define SC8180X_MSS	8
+#define SC8180X_MX	9
+#define SC8180X_MX_AO	10
+
+/* SC8280XP Power Domain Indexes */
+#define SC8280XP_CX		0
+#define SC8280XP_CX_AO		1
+#define SC8280XP_DDR		2
+#define SC8280XP_EBI		3
+#define SC8280XP_GFX		4
+#define SC8280XP_LCX		5
+#define SC8280XP_LMX		6
+#define SC8280XP_MMCX		7
+#define SC8280XP_MMCX_AO	8
+#define SC8280XP_MSS		9
+#define SC8280XP_MX		10
+#define SC8280XP_MXC		12
+#define SC8280XP_MX_AO		11
+#define SC8280XP_NSP		13
+#define SC8280XP_QPHY		14
+#define SC8280XP_XO		15
+
 #endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index f15bcee7c92..4371ac941f2 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -4,258 +4,39 @@
 #ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
 #define _DT_BINDINGS_POWER_QCOM_RPMPD_H
 
-/* SA8775P Power Domain Indexes */
-#define SA8775P_CX	0
-#define SA8775P_CX_AO	1
-#define SA8775P_DDR	2
-#define SA8775P_EBI	3
-#define SA8775P_GFX	4
-#define SA8775P_LCX	5
-#define SA8775P_LMX	6
-#define SA8775P_MMCX	7
-#define SA8775P_MMCX_AO	8
-#define SA8775P_MSS	9
-#define SA8775P_MX	10
-#define SA8775P_MX_AO	11
-#define SA8775P_MXC	12
-#define SA8775P_MXC_AO	13
-#define SA8775P_NSP0	14
-#define SA8775P_NSP1	15
-#define SA8775P_XO	16
+#include <dt-bindings/power/qcom,rpmhpd.h>
 
-/* SDM670 Power Domain Indexes */
-#define SDM670_MX	0
-#define SDM670_MX_AO	1
-#define SDM670_CX	2
-#define SDM670_CX_AO	3
-#define SDM670_LMX	4
-#define SDM670_LCX	5
-#define SDM670_GFX	6
-#define SDM670_MSS	7
+/* Generic RPM Power Domain Indexes */
+#define RPMPD_VDDCX		0
+#define RPMPD_VDDCX_AO		1
+/* VFC and VFL are mutually exclusive and can not be present on the same platform */
+#define RPMPD_VDDCX_VFC		2
+#define RPMPD_VDDCX_VFL		2
+#define RPMPD_VDDMX		3
+#define RPMPD_VDDMX_AO		4
+#define RPMPD_VDDMX_VFL		5
+#define RPMPD_SSCCX		6
+#define RPMPD_SSCCX_VFL		7
+#define RPMPD_SSCMX		8
+#define RPMPD_SSCMX_VFL		9
 
-/* SDM845 Power Domain Indexes */
-#define SDM845_EBI	0
-#define SDM845_MX	1
-#define SDM845_MX_AO	2
-#define SDM845_CX	3
-#define SDM845_CX_AO	4
-#define SDM845_LMX	5
-#define SDM845_LCX	6
-#define SDM845_GFX	7
-#define SDM845_MSS	8
-
-/* SDX55 Power Domain Indexes */
-#define SDX55_MSS	0
-#define SDX55_MX	1
-#define SDX55_CX	2
-
-/* SDX65 Power Domain Indexes */
-#define SDX65_MSS	0
-#define SDX65_MX	1
-#define SDX65_MX_AO	2
-#define SDX65_CX	3
-#define SDX65_CX_AO	4
-#define SDX65_MXC	5
-
-/* SM6350 Power Domain Indexes */
-#define SM6350_CX	0
-#define SM6350_GFX	1
-#define SM6350_LCX	2
-#define SM6350_LMX	3
-#define SM6350_MSS	4
-#define SM6350_MX	5
-
-/* SM6375 Power Domain Indexes */
-#define SM6375_VDDCX		0
-#define SM6375_VDDCX_AO	1
-#define SM6375_VDDCX_VFL	2
-#define SM6375_VDDMX		3
-#define SM6375_VDDMX_AO	4
-#define SM6375_VDDMX_VFL	5
-#define SM6375_VDDGX		6
-#define SM6375_VDDGX_AO	7
-#define SM6375_VDD_LPI_CX	8
-#define SM6375_VDD_LPI_MX	9
-
-/* SM8150 Power Domain Indexes */
-#define SM8150_MSS	0
-#define SM8150_EBI	1
-#define SM8150_LMX	2
-#define SM8150_LCX	3
-#define SM8150_GFX	4
-#define SM8150_MX	5
-#define SM8150_MX_AO	6
-#define SM8150_CX	7
-#define SM8150_CX_AO	8
-#define SM8150_MMCX	9
-#define SM8150_MMCX_AO	10
-
-/* SA8155P is a special case, kept for backwards compatibility */
-#define SA8155P_CX	SM8150_CX
-#define SA8155P_CX_AO	SM8150_CX_AO
-#define SA8155P_EBI	SM8150_EBI
-#define SA8155P_GFX	SM8150_GFX
-#define SA8155P_MSS	SM8150_MSS
-#define SA8155P_MX	SM8150_MX
-#define SA8155P_MX_AO	SM8150_MX_AO
-
-/* SM8250 Power Domain Indexes */
-#define SM8250_CX	0
-#define SM8250_CX_AO	1
-#define SM8250_EBI	2
-#define SM8250_GFX	3
-#define SM8250_LCX	4
-#define SM8250_LMX	5
-#define SM8250_MMCX	6
-#define SM8250_MMCX_AO	7
-#define SM8250_MX	8
-#define SM8250_MX_AO	9
-
-/* SM8350 Power Domain Indexes */
-#define SM8350_CX	0
-#define SM8350_CX_AO	1
-#define SM8350_EBI	2
-#define SM8350_GFX	3
-#define SM8350_LCX	4
-#define SM8350_LMX	5
-#define SM8350_MMCX	6
-#define SM8350_MMCX_AO	7
-#define SM8350_MX	8
-#define SM8350_MX_AO	9
-#define SM8350_MXC	10
-#define SM8350_MXC_AO	11
-#define SM8350_MSS	12
-
-/* SM8450 Power Domain Indexes */
-#define SM8450_CX	0
-#define SM8450_CX_AO	1
-#define SM8450_EBI	2
-#define SM8450_GFX	3
-#define SM8450_LCX	4
-#define SM8450_LMX	5
-#define SM8450_MMCX	6
-#define SM8450_MMCX_AO	7
-#define SM8450_MX	8
-#define SM8450_MX_AO	9
-#define SM8450_MXC	10
-#define SM8450_MXC_AO	11
-#define SM8450_MSS	12
-
-/* SM8550 Power Domain Indexes */
-#define SM8550_CX	0
-#define SM8550_CX_AO	1
-#define SM8550_EBI	2
-#define SM8550_GFX	3
-#define SM8550_LCX	4
-#define SM8550_LMX	5
-#define SM8550_MMCX	6
-#define SM8550_MMCX_AO	7
-#define SM8550_MX	8
-#define SM8550_MX_AO	9
-#define SM8550_MXC	10
-#define SM8550_MXC_AO	11
-#define SM8550_MSS	12
-#define SM8550_NSP	13
-
-/* QDU1000/QRU1000 Power Domain Indexes */
-#define QDU1000_EBI	0
-#define QDU1000_MSS	1
-#define QDU1000_CX	2
-#define QDU1000_MX	3
-
-/* SC7180 Power Domain Indexes */
-#define SC7180_CX	0
-#define SC7180_CX_AO	1
-#define SC7180_GFX	2
-#define SC7180_MX	3
-#define SC7180_MX_AO	4
-#define SC7180_LMX	5
-#define SC7180_LCX	6
-#define SC7180_MSS	7
-
-/* SC7280 Power Domain Indexes */
-#define SC7280_CX	0
-#define SC7280_CX_AO	1
-#define SC7280_EBI	2
-#define SC7280_GFX	3
-#define SC7280_MX	4
-#define SC7280_MX_AO	5
-#define SC7280_LMX	6
-#define SC7280_LCX	7
-#define SC7280_MSS	8
-
-/* SC8180X Power Domain Indexes */
-#define SC8180X_CX	0
-#define SC8180X_CX_AO	1
-#define SC8180X_EBI	2
-#define SC8180X_GFX	3
-#define SC8180X_LCX	4
-#define SC8180X_LMX	5
-#define SC8180X_MMCX	6
-#define SC8180X_MMCX_AO	7
-#define SC8180X_MSS	8
-#define SC8180X_MX	9
-#define SC8180X_MX_AO	10
-
-/* SC8280XP Power Domain Indexes */
-#define SC8280XP_CX		0
-#define SC8280XP_CX_AO		1
-#define SC8280XP_DDR		2
-#define SC8280XP_EBI		3
-#define SC8280XP_GFX		4
-#define SC8280XP_LCX		5
-#define SC8280XP_LMX		6
-#define SC8280XP_MMCX		7
-#define SC8280XP_MMCX_AO	8
-#define SC8280XP_MSS		9
-#define SC8280XP_MX		10
-#define SC8280XP_MXC		12
-#define SC8280XP_MX_AO		11
-#define SC8280XP_NSP		13
-#define SC8280XP_QPHY		14
-#define SC8280XP_XO		15
-
-/* SDM845 Power Domain performance levels */
-#define RPMH_REGULATOR_LEVEL_RETENTION		16
-#define RPMH_REGULATOR_LEVEL_MIN_SVS		48
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3		50
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
-#define RPMH_REGULATOR_LEVEL_LOW_SVS		64
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1		80
-#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2		96
-#define RPMH_REGULATOR_LEVEL_SVS		128
-#define RPMH_REGULATOR_LEVEL_SVS_L0		144
-#define RPMH_REGULATOR_LEVEL_SVS_L1		192
-#define RPMH_REGULATOR_LEVEL_SVS_L2		224
-#define RPMH_REGULATOR_LEVEL_NOM		256
-#define RPMH_REGULATOR_LEVEL_NOM_L0		288
-#define RPMH_REGULATOR_LEVEL_NOM_L1		320
-#define RPMH_REGULATOR_LEVEL_NOM_L2		336
-#define RPMH_REGULATOR_LEVEL_TURBO		384
-#define RPMH_REGULATOR_LEVEL_TURBO_L0		400
-#define RPMH_REGULATOR_LEVEL_TURBO_L1		416
-#define RPMH_REGULATOR_LEVEL_TURBO_L2		432
-#define RPMH_REGULATOR_LEVEL_TURBO_L3		448
-#define RPMH_REGULATOR_LEVEL_TURBO_L4		452
-#define RPMH_REGULATOR_LEVEL_TURBO_L5		456
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
-#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
+/*
+ * Platform-specific power domain bindings. Don't add new entries here, use
+ * RPMPD_* above.
+ */
 
 /* MDM9607 Power Domains */
-#define MDM9607_VDDCX		0
-#define MDM9607_VDDCX_AO	1
-#define MDM9607_VDDCX_VFL	2
-#define MDM9607_VDDMX		3
-#define MDM9607_VDDMX_AO	4
-#define MDM9607_VDDMX_VFL	5
+#define MDM9607_VDDCX		RPMPD_VDDCX
+#define MDM9607_VDDCX_AO	RPMPD_VDDCX_AO
+#define MDM9607_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define MDM9607_VDDMX		RPMPD_VDDMX
+#define MDM9607_VDDMX_AO	RPMPD_VDDMX_AO
+#define MDM9607_VDDMX_VFL	RPMPD_VDDMX_VFL
 
 /* MSM8226 Power Domain Indexes */
-#define MSM8226_VDDCX		0
-#define MSM8226_VDDCX_AO	1
-#define MSM8226_VDDCX_VFC	2
+#define MSM8226_VDDCX		RPMPD_VDDCX
+#define MSM8226_VDDCX_AO	RPMPD_VDDCX_AO
+#define MSM8226_VDDCX_VFC	RPMPD_VDDCX_VFC
 
 /* MSM8939 Power Domains */
 #define MSM8939_VDDMDCX		0
@@ -268,11 +49,11 @@
 #define MSM8939_VDDMX_AO	7
 
 /* MSM8916 Power Domain Indexes */
-#define MSM8916_VDDCX		0
-#define MSM8916_VDDCX_AO	1
-#define MSM8916_VDDCX_VFC	2
-#define MSM8916_VDDMX		3
-#define MSM8916_VDDMX_AO	4
+#define MSM8916_VDDCX		RPMPD_VDDCX
+#define MSM8916_VDDCX_AO	RPMPD_VDDCX_AO
+#define MSM8916_VDDCX_VFC	RPMPD_VDDCX_VFC
+#define MSM8916_VDDMX		RPMPD_VDDMX
+#define MSM8916_VDDMX_AO	RPMPD_VDDMX_AO
 
 /* MSM8909 Power Domain Indexes */
 #define MSM8909_VDDCX		MSM8916_VDDCX
@@ -282,11 +63,11 @@
 #define MSM8909_VDDMX_AO	MSM8916_VDDMX_AO
 
 /* MSM8917 Power Domain Indexes */
-#define MSM8917_VDDCX		0
-#define MSM8917_VDDCX_AO	1
-#define MSM8917_VDDCX_VFL	2
-#define MSM8917_VDDMX		3
-#define MSM8917_VDDMX_AO	4
+#define MSM8917_VDDCX		RPMPD_VDDCX
+#define MSM8917_VDDCX_AO	RPMPD_VDDCX_AO
+#define MSM8917_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define MSM8917_VDDMX		RPMPD_VDDMX
+#define MSM8917_VDDMX_AO	RPMPD_VDDMX_AO
 
 /* MSM8937 Power Domain Indexes */
 #define MSM8937_VDDCX		MSM8917_VDDCX
@@ -319,12 +100,12 @@
 #define MSM8974_VDDGFX_VFC	4
 
 /* MSM8976 Power Domain Indexes */
-#define MSM8976_VDDCX		0
-#define MSM8976_VDDCX_AO	1
-#define MSM8976_VDDCX_VFL	2
-#define MSM8976_VDDMX		3
-#define MSM8976_VDDMX_AO	4
-#define MSM8976_VDDMX_VFL	5
+#define MSM8976_VDDCX		RPMPD_VDDCX
+#define MSM8976_VDDCX_AO	RPMPD_VDDCX_AO
+#define MSM8976_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define MSM8976_VDDMX		RPMPD_VDDMX
+#define MSM8976_VDDMX_AO	RPMPD_VDDMX_AO
+#define MSM8976_VDDMX_VFL	RPMPD_VDDMX_VFL
 
 /* MSM8994 Power Domain Indexes */
 #define MSM8994_VDDCX		0
@@ -345,16 +126,26 @@
 #define MSM8996_VDDSSCX_VFC	6
 
 /* MSM8998 Power Domain Indexes */
-#define MSM8998_VDDCX		0
-#define MSM8998_VDDCX_AO	1
-#define MSM8998_VDDCX_VFL	2
-#define MSM8998_VDDMX		3
-#define MSM8998_VDDMX_AO	4
-#define MSM8998_VDDMX_VFL	5
-#define MSM8998_SSCCX		6
-#define MSM8998_SSCCX_VFL	7
-#define MSM8998_SSCMX		8
-#define MSM8998_SSCMX_VFL	9
+#define MSM8998_VDDCX		RPMPD_VDDCX
+#define MSM8998_VDDCX_AO	RPMPD_VDDCX_AO
+#define MSM8998_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define MSM8998_VDDMX		RPMPD_VDDMX
+#define MSM8998_VDDMX_AO	RPMPD_VDDMX_AO
+#define MSM8998_VDDMX_VFL	RPMPD_VDDMX_VFL
+#define MSM8998_SSCCX		RPMPD_SSCCX
+#define MSM8998_SSCCX_VFL	RPMPD_SSCCX_VFL
+#define MSM8998_SSCMX		RPMPD_SSCMX
+#define MSM8998_SSCMX_VFL	RPMPD_SSCMX_VFL
+
+/* QCM2290 Power Domains */
+#define QCM2290_VDDCX		0
+#define QCM2290_VDDCX_AO	1
+#define QCM2290_VDDCX_VFL	2
+#define QCM2290_VDDMX		3
+#define QCM2290_VDDMX_AO	4
+#define QCM2290_VDDMX_VFL	5
+#define QCM2290_VDD_LPI_CX	6
+#define QCM2290_VDD_LPI_MX	7
 
 /* QCS404 Power Domains */
 #define QCS404_VDDMX		0
@@ -366,16 +157,16 @@
 #define QCS404_LPIMX_VFL	6
 
 /* SDM660 Power Domains */
-#define SDM660_VDDCX		0
-#define SDM660_VDDCX_AO		1
-#define SDM660_VDDCX_VFL	2
-#define SDM660_VDDMX		3
-#define SDM660_VDDMX_AO		4
-#define SDM660_VDDMX_VFL	5
-#define SDM660_SSCCX		6
-#define SDM660_SSCCX_VFL	7
-#define SDM660_SSCMX		8
-#define SDM660_SSCMX_VFL	9
+#define SDM660_VDDCX		RPMPD_VDDCX
+#define SDM660_VDDCX_AO		RPMPD_VDDCX_AO
+#define SDM660_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define SDM660_VDDMX		RPMPD_VDDMX
+#define SDM660_VDDMX_AO		RPMPD_VDDMX_AO
+#define SDM660_VDDMX_VFL	RPMPD_VDDMX_VFL
+#define SDM660_SSCCX		RPMPD_SSCCX
+#define SDM660_SSCCX_VFL	RPMPD_SSCCX_VFL
+#define SDM660_SSCMX		RPMPD_SSCMX
+#define SDM660_SSCMX_VFL	RPMPD_SSCMX_VFL
 
 /* SM6115 Power Domains */
 #define SM6115_VDDCX		0
@@ -388,22 +179,24 @@
 #define SM6115_VDD_LPI_MX	7
 
 /* SM6125 Power Domains */
-#define SM6125_VDDCX		0
-#define SM6125_VDDCX_AO		1
-#define SM6125_VDDCX_VFL	2
-#define SM6125_VDDMX		3
-#define SM6125_VDDMX_AO		4
-#define SM6125_VDDMX_VFL	5
+#define SM6125_VDDCX		RPMPD_VDDCX
+#define SM6125_VDDCX_AO		RPMPD_VDDCX_AO
+#define SM6125_VDDCX_VFL	RPMPD_VDDCX_VFL
+#define SM6125_VDDMX		RPMPD_VDDMX
+#define SM6125_VDDMX_AO		RPMPD_VDDMX_AO
+#define SM6125_VDDMX_VFL	RPMPD_VDDMX_VFL
 
-/* QCM2290 Power Domains */
-#define QCM2290_VDDCX		0
-#define QCM2290_VDDCX_AO	1
-#define QCM2290_VDDCX_VFL	2
-#define QCM2290_VDDMX		3
-#define QCM2290_VDDMX_AO	4
-#define QCM2290_VDDMX_VFL	5
-#define QCM2290_VDD_LPI_CX	6
-#define QCM2290_VDD_LPI_MX	7
+/* SM6375 Power Domain Indexes */
+#define SM6375_VDDCX		0
+#define SM6375_VDDCX_AO	1
+#define SM6375_VDDCX_VFL	2
+#define SM6375_VDDMX		3
+#define SM6375_VDDMX_AO	4
+#define SM6375_VDDMX_VFL	5
+#define SM6375_VDDGX		6
+#define SM6375_VDDGX_AO	7
+#define SM6375_VDD_LPI_CX	8
+#define SM6375_VDD_LPI_MX	9
 
 /* RPM SMD Power Domain performance levels */
 #define RPM_SMD_LEVEL_RETENTION       16
diff --git a/include/dt-bindings/reset/mediatek,mt8196-resets.h b/include/dt-bindings/reset/mediatek,mt8196-resets.h
new file mode 100644
index 00000000000..46ced0850d9
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt8196-resets.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ * Author: AngeloGioacchino Del Regno <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8196
+
+/* PEXTP0 resets */
+#define MT8196_PEXTP0_RST0_PCIE0_MAC		0
+#define MT8196_PEXTP0_RST0_PCIE0_PHY		1
+
+/* PEXTP1 resets */
+#define MT8196_PEXTP1_RST0_PCIE1_MAC		0
+#define MT8196_PEXTP1_RST0_PCIE1_PHY		1
+#define MT8196_PEXTP1_RST0_PCIE2_MAC		2
+#define MT8196_PEXTP1_RST0_PCIE2_PHY		3
+
+/* UFS resets */
+#define MT8196_UFSAO_RST0_UFS_MPHY		0
+#define MT8196_UFSAO_RST1_UFS_UNIPRO		1
+#define MT8196_UFSAO_RST1_UFS_CRYPTO		2
+#define MT8196_UFSAO_RST1_UFSHCI		3
+
+#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */
diff --git a/include/dt-bindings/reset/nvidia,tegra114-car.h b/include/dt-bindings/reset/nvidia,tegra114-car.h
new file mode 100644
index 00000000000..9b8c320402d
--- /dev/null
+++ b/include/dt-bindings/reset/nvidia,tegra114-car.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * This header provides Tegra114-specific constants for binding
+ * nvidia,tegra114-car.
+ */
+
+#ifndef _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
+#define _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H
+
+#define TEGRA114_RESET(x)		(5 * 32 + (x))
+#define TEGRA114_RST_DFLL_DVCO		TEGRA114_RESET(0)
+
+#endif	/* _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/reset/st,stm32mp21-rcc.h b/include/dt-bindings/reset/st,stm32mp21-rcc.h
new file mode 100644
index 00000000000..6463bd73d02
--- /dev/null
+++ b/include/dt-bindings/reset/st,stm32mp21-rcc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author: Gabriel Fernandez <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_STM32MP21_RESET_H_
+#define _DT_BINDINGS_STM32MP21_RESET_H_
+
+#define TIM1_R		0
+#define TIM2_R		1
+#define TIM3_R		2
+#define TIM4_R		3
+#define TIM5_R		4
+#define TIM6_R		5
+#define TIM7_R		6
+#define TIM8_R		7
+#define TIM10_R		8
+#define TIM11_R		9
+#define TIM12_R		10
+#define TIM13_R		11
+#define TIM14_R		12
+#define TIM15_R		13
+#define TIM16_R		14
+#define TIM17_R		15
+#define LPTIM1_R	16
+#define LPTIM2_R	17
+#define LPTIM3_R	18
+#define LPTIM4_R	19
+#define LPTIM5_R	20
+#define SPI1_R		21
+#define SPI2_R		22
+#define SPI3_R		23
+#define SPI4_R		24
+#define SPI5_R		25
+#define SPI6_R		26
+#define SPDIFRX_R	27
+#define USART1_R	28
+#define USART2_R	29
+#define USART3_R	30
+#define UART4_R		31
+#define UART5_R		32
+#define USART6_R	33
+#define UART7_R		34
+#define LPUART1_R	35
+#define I2C1_R		36
+#define I2C2_R		37
+#define I2C3_R		38
+#define SAI1_R		39
+#define SAI2_R		40
+#define SAI3_R		41
+#define SAI4_R		42
+#define MDF1_R		43
+#define FDCAN_R		44
+#define HDP_R		45
+#define ADC1_R		46
+#define ADC2_R		47
+#define ETH1_R		48
+#define ETH2_R		49
+#define USBH_R		50
+#define USB2PHY1_R	51
+#define USB2PHY2_R	52
+#define SDMMC1_R	53
+#define SDMMC1DLL_R	54
+#define SDMMC2_R	55
+#define SDMMC2DLL_R	56
+#define SDMMC3_R	57
+#define SDMMC3DLL_R	58
+#define LTDC_R		59
+#define CSI_R		60
+#define DCMIPP_R	61
+#define DCMIPSSI_R	62
+#define WWDG1_R		63
+#define VREF_R		64
+#define DTS_R		65
+#define CRC_R		66
+#define SERC_R		67
+#define I3C1_R		68
+#define I3C2_R		69
+#define I3C3_R		70
+#define IWDG2_KER_R	71
+#define IWDG4_KER_R	72
+#define RNG1_R		73
+#define RNG2_R		74
+#define PKA_R		75
+#define SAES_R		76
+#define HASH1_R		77
+#define HASH2_R		78
+#define CRYP1_R		79
+#define CRYP2_R		80
+#define OSPI1_R		81
+#define OSPI1DLL_R	82
+#define OTG_R		83
+#define FMC_R		84
+#define DBG_R		85
+#define GPIOA_R		86
+#define GPIOB_R		87
+#define GPIOC_R		88
+#define GPIOD_R		89
+#define GPIOE_R		90
+#define GPIOF_R		91
+#define GPIOG_R		92
+#define GPIOH_R		93
+#define GPIOI_R		94
+#define GPIOZ_R		95
+#define HPDMA1_R	96
+#define HPDMA2_R	97
+#define HPDMA3_R	98
+#define IPCC1_R		99
+#define C2_HOLDBOOT_R	100
+#define C1_HOLDBOOT_R	101
+#define C1_R		102
+#define C1P1POR_R	103
+#define C1P1_R		104
+#define C2_R		105
+#define SYS_R		106
+#define VSW_R		107
+#define C1MS_R		108
+#define DDRCP_R		109
+#define DDRCAPB_R	110
+#define DDRPHYCAPB_R	111
+#define DDRCFG_R	112
+#define DDR_R		113
+#define DDRPERFM_R	114
+#define IWDG1_SYS_R	116
+#define IWDG2_SYS_R	117
+#define IWDG3_SYS_R	118
+#define IWDG4_SYS_R	119
+
+#define RST_SCMI_C1_R		0
+#define RST_SCMI_C2_R		1
+#define RST_SCMI_C1_HOLDBOOT_R	2
+#define RST_SCMI_C2_HOLDBOOT_R	3
+#define RST_SCMI_FMC		4
+#define RST_SCMI_OSPI1		5
+#define RST_SCMI_OSPI1DLL	6
+
+#endif /* _DT_BINDINGS_STM32MP21_RESET_H_ */
diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h
new file mode 100644
index 00000000000..a89a0b44f08
--- /dev/null
+++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2025 Chen-Yu Tsai <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
+#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_
+
+#define RST_BUS_MCU_I2S0		0
+#define RST_BUS_MCU_I2S1		1
+#define RST_BUS_MCU_I2S2		2
+#define RST_BUS_MCU_I2S3		3
+#define RST_BUS_MCU_SPDIF		4
+#define RST_BUS_MCU_DMIC		5
+#define RST_BUS_MCU_AUDIO_CODEC		6
+#define RST_BUS_MCU_DSP_MSGBOX		7
+#define RST_BUS_MCU_DSP_CFG		8
+#define RST_BUS_MCU_NPU			9
+#define RST_BUS_MCU_TIMER		10
+#define RST_BUS_MCU_DSP_DEBUG		11
+#define RST_BUS_MCU_DSP			12
+#define RST_BUS_MCU_DMA			13
+#define RST_BUS_MCU_PUBSRAM		14
+#define RST_BUS_MCU_RISCV_CFG		15
+#define RST_BUS_MCU_RISCV_DEBUG		16
+#define RST_BUS_MCU_RISCV_CORE		17
+#define RST_BUS_MCU_RISCV_MSGBOX	18
+#define RST_BUS_MCU_PWM0		19
+
+#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */
diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h
index 00459f16048..ee799286c17 100644
--- a/include/dt-bindings/reset/thead,th1520-reset.h
+++ b/include/dt-bindings/reset/thead,th1520-reset.h
@@ -12,5 +12,12 @@
 #define TH1520_RESET_ID_NPU		2
 #define TH1520_RESET_ID_WDT0		3
 #define TH1520_RESET_ID_WDT1		4
+#define TH1520_RESET_ID_DPU_AHB		5
+#define TH1520_RESET_ID_DPU_AXI		6
+#define TH1520_RESET_ID_DPU_CORE	7
+#define TH1520_RESET_ID_DSI0_APB	8
+#define TH1520_RESET_ID_DSI1_APB	9
+#define TH1520_RESET_ID_HDMI		10
+#define TH1520_RESET_ID_HDMI_APB	11
 
 #endif /* _DT_BINDINGS_TH1520_RESET_H */
diff --git a/include/dt-bindings/thermal/tegra114-soctherm.h b/include/dt-bindings/thermal/tegra114-soctherm.h
new file mode 100644
index 00000000000..b766a61cd1c
--- /dev/null
+++ b/include/dt-bindings/thermal/tegra114-soctherm.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for binding nvidia,tegra114-soctherm.
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H
+#define _DT_BINDINGS_THERMAL_TEGRA114_SOCTHERM_H
+
+#define TEGRA114_SOCTHERM_SENSOR_CPU 0
+#define TEGRA114_SOCTHERM_SENSOR_MEM 1
+#define TEGRA114_SOCTHERM_SENSOR_GPU 2
+#define TEGRA114_SOCTHERM_SENSOR_PLLX 3
+
+#define TEGRA114_SOCTHERM_THROT_LEVEL_NONE 0
+#define TEGRA114_SOCTHERM_THROT_LEVEL_LOW  1
+#define TEGRA114_SOCTHERM_THROT_LEVEL_MED  2
+#define TEGRA114_SOCTHERM_THROT_LEVEL_HIGH 3
+
+#endif