diff options
| author | Maheedhar Bollapalli <[email protected]> | 2026-02-10 12:02:06 +0100 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-02-11 09:26:17 +0100 |
| commit | 85bbd16750ed7a4907666bfa01effc39ef1f4c0c (patch) | |
| tree | 61105579d8bb95db2c70369d544515e87a1395f6 /include | |
| parent | 6d865c1ee61621e1fc91bc29764c39b7730b57f1 (diff) | |
arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2
Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to
not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR
frames, access out-of-range addresses, and hit a synchronous exception
during early gic init percpu while booting up on alternate core
i.e., non cpu0.
Update Versal Gen 2 headers to the correct Versal Gen 2 bases.
Signed-off-by: Maheedhar Bollapalli <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/amd_versal2.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 05ddd4eabe1..404af2cd4c6 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -16,8 +16,8 @@ /* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ /* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF9000000 -#define GICR_BASE 0xF9060000 +#define GICD_BASE 0xe2000000 +#define GICR_BASE 0xe2060000 /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ |