diff options
| author | Marek Vasut <[email protected]> | 2019-06-27 00:26:34 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2020-02-03 09:26:14 +0100 |
| commit | 8941f8414dc70a161e11ed0f383f322bb31f1054 (patch) | |
| tree | f6337f6c9596ed43c4d48e4a40546bca85067376 /include | |
| parent | 707c36e2af817f66b72561e4652f22b2f8989c8e (diff) | |
watchdog: designware: Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig
Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dalon Westergreen <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Jagan Teki <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Philipp Tomisch <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/socfpga_common.h | 3 | ||||
| -rw-r--r-- | include/configs/socfpga_soc64_common.h | 6 |
2 files changed, 4 insertions, 5 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 05bfef75c0d..8d10469e7c3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -104,11 +104,8 @@ /* * L4 Watchdog */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#endif /* * MMC Driver diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 4afadafd35a..ac7c0050558 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -152,7 +152,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #ifdef CONFIG_SPL_BUILD #define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG +#else +#undef CONFIG_HW_WATCHDOG +#undef CONFIG_DESIGNWARE_WATCHDOG +#endif #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ @@ -162,7 +165,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void); #else #define CONFIG_DW_WDT_CLOCK_KHZ 100000 #endif -#endif /* * SPL memory layout |