diff options
| author | Tom Rini <[email protected]> | 2025-09-19 11:56:24 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-09-19 11:56:24 -0600 |
| commit | 8c4430fc523f60ebeac09a6637deae428a6c0c1a (patch) | |
| tree | cb3129be6f2c0abe8a4dfd9e52cba25746397443 /include | |
| parent | ecced05f679e1920ffd3e1bd57334bd6442194c4 (diff) | |
| parent | edaaedb5dd0fee9fcdfe41d92659914dc9d1d44d (diff) | |
Merge patch series "qemu-sbsa: Fix GIC enablement"
Kunihiko Hayashi <[email protected]> says:
In the qemu-sbsa configuration, the GICv3 definition is disabled due to
a typo. After fixing the typo, GICv3 is enabled, however, the GIC register
base address definitions are missing, resulting in a build failure.
This series enables GICv3 and resolves this build error.
Confirming that U-Boot successfully starts up in QEMU SBSA environment
after the fix.
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/qemu-sbsa.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h index aff78160e12..669d0fe7c58 100644 --- a/include/configs/qemu-sbsa.h +++ b/include/configs/qemu-sbsa.h @@ -86,4 +86,8 @@ #define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE 0x1000000 +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR +#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR + #endif /* __CONFIG_H */ |