diff options
| author | Bernhard Messerklinger <[email protected]> | 2025-04-04 09:28:00 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-04-16 15:39:48 +0200 |
| commit | 8e25e76fff0698c8268b279af3d7859ed2e14ea5 (patch) | |
| tree | 4f20a774e2045f3c53104388c86753ed3064d82e /include | |
| parent | 80e9b279a3253299ad12b386ab90752a6baf1c42 (diff) | |
board/BuR/zynq: initial commit
This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
boards. This boards are based on the Xilinx Zynq SoC.
Signed-off-by: Bernhard Messerklinger <[email protected]>
Acked-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/brzynq.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/configs/brzynq.h b/include/configs/brzynq.h new file mode 100644 index 00000000000..e2ebb2f1004 --- /dev/null +++ b/include/configs/brzynq.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Config file for BR Zynq board + * + * Copyright (C) 2024 + * B&R Industrial Automation GmbH - http://www.br-automation.com/ + */ + +#ifndef __CONFIG_BRZYNQ_H__ +#define __CONFIG_BRZYNQ_H__ + +/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */ +#if IS_ENABLED(CONFIG_SPL_FPGA) +#define PHY_ANEG_TIMEOUT 8000 +#endif + +/* Use top mapped SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 + +#endif /* __CONFIG_BRZYNQ_H__ */ |