Squashed 'dts/upstream/' changes from 0f7b6a4fa8c5..e8613e1cf445

e8613e1cf445 Merge tag 'v7.1-dts-raw'
7d7b25386d0d dt-bindings: i2c: mux-gpio: name correct maintainer
504267e5a417 Merge tag 'v7.1-rc7-dts-raw'
f3a745a3a4ad Merge tag 'net-7.1-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
acccf58ac475 dt-bindings: ethernet: eswin: fix hsp-sp-csr backward compatibility
5603b5a845a6 Merge tag 'soc-fixes-7.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
8bdd093b9a17 Merge tag 'at91-fixes-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
9234c73423a8 Merge tag 'v7.1-rc6-dts-raw'
3a9d5adf2b88 Merge tag 'usb-7.1-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
34fdbf49fba1 ARM: dts: gemini: Fix partition offsets
cf3edfa743ba Merge tag 'qcom-arm64-fixes-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
8046ed0ddc8f Merge tag 'qcom-drivers-fixes-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
1fa60a4ea31d spi: dt-bindings: spi-qpic-snand: Add ipq5210 compatible
13f874376658 Merge tag 'v7.1-rc5-dts-raw'
c286586a7e10 Merge tag 'drm-fixes-2026-05-23' of https://gitlab.freedesktop.org/drm/kernel
e762331c291d Merge tag 'spi-fix-v7.1-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
ba13e8e63c11 Merge tag 'sound-7.1-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
b30ca4dcc44c dt-bindings: usb: Fix EIC7700 USB reset's issue
d5518259c298 dt-bindings: usb: ti,omap4-musb: Drop duplicate 'usb-phy' property constraints
33e749a8bbba Merge tag 'net-7.1-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
08874e59dda6 Merge branch '20260416-qcom_ice_power_and_clk_vote-v5-13-5ccf5d7e2846@oss.qualcomm.com' into arm64-fixes-for-7.1
89fde76ccf55 arm64: dts: qcom: eliza: Add power-domain and iface clk for ice node
27b0f6c5d58d arm64: dts: qcom: milos: Add power-domain and iface clk for ice node
1bd32a2c178b spi: dt-bindings: fsl-qspi: support SpacemiT K3
c80fa8778611 Merge tag 'soc-fixes-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
409463513451 dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets
f5c3a8c44216 Merge tag 'drm-msm-fixes-2026-05-17' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
2bc032c57304 dt-bindings: display/msm: Fix typo in clock-names property
db5740840be6 ARM: dts: microchip: sam9x7: fix GMAC clock configuration
7d7ce06c8f20 dt-bindings: display/msm: qcom,eliza-mdss: Correct DPU and DP ranges in example
30314657c9dd dt-bindings: display/msm: sm8750-mdss: Correct DPU and DP ranges in example
3c3223fcd495 dt-bindings: display/msm: sm8650: Correct VBIF range in example
f8b9e1e3519f dt-bindings: display/msm: dp-controller: Allow DAI on SM8650 and others
2eb0667eba93 dt-bindings: display/msm: dp-controller: Correct SM8650 IO range
d680a66f2e22 arm64: dts: qcom: x1-dell-thena: remove i2c20 (battery SMBus) and reserve its pins
14bd812f65ef arm64: dts: qcom: glymur: Drop RPMh CXO clocks from QMP PHYs
2b901debdeee dt-bindings: crypto: qcom,ice: Fix missing power-domain and iface clk
0a1bc7849ca4 Merge tag 'v7.1-rc3-dts-raw'
666d329106c4 ASoC; dt-bindings: mediatek,mt8173-rt5650-rt5514: Fix mediatek,audio-codec constraints
14e66255adcf Merge tag 'riscv-dt-fixes-for-v7.1-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
7b9455d83578 Merge tag 'renesas-fixes-for-v7.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
414a765b6286 dt-bindings: i2c: apple,i2c: Add t8122 compatible
50d464bac2ae Merge tag 'v7.1-rc2-dts-raw'
6ab87574f769 dt-bindings: i2c: amlogic: Add compatible for T7 SOC
75f8059eac8d Merge tag 'mailbox-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
960ba5328113 riscv: dts: microchip: fix icicle i2c pinctrl configuration
40f8b0178ead riscv: dts: starfive: jh7110: Drop CAMSS node
43def18f34fe arm64: dts: renesas: r9a09g056: Add #mux-state-cells to usb20phyrst
1f176138aa80 arm64: dts: renesas: r9a09g057: Add #mux-state-cells to usb2{0,1}phyrst
7b2f4bbf8bf6 ARM: dts: renesas: rskrza1: Drop superfluous cells
1d9e0dbc238c ARM: dts: renesas: genmai: Drop superfluous cells
017c0a259732 ARM: dts: renesas: r7s72100: Add missing unit address to bus node
ea1b71e07873 ARM: dts: renesas: r8a7792: Add missing unit address to bus node
8de5366ee7ea ARM: dts: renesas: r8a7779: Add missing unit address to bus node
9c64edd80710 ARM: dts: renesas: r8a7778: Add missing unit address to bus node
a71a1da242f3 arm64: dts: renesas: rz-smarc-du-adv7513-smarc: Fix missing cells and reg in DU subnode
a0137ebb2eef arm64: dts: renesas: rz-smarc-cru-csi-ov5645: Fix missing cells and reg in CSI2 subnode
6b9f827a5dd3 arm64: dts: renesas: salvator-panel: Fix missing cells and reg in DTO
4574e35715ad arm64: dts: renesas: draak/ebisu-panel: Fix missing cells and reg in DTO
53a52a8936c7 arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks
29faa9a4aac7 Merge tag 'v7.1-rc1-dts-raw'
3c8b54cc8bb8 Merge tag 'rtc-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
0f0b879ed6b6 Merge tag 'char-misc-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
dec766502d1c Merge tag 'spi-fix-v7.1-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
ecda115b10e3 Merge tag 'sound-fix-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f8fecf83f15c Merge tag 'i2c-for-7.1-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
a7c313e79b3c Merge tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
c631527dbade Merge tag 'amlogic-fixes-v7.1-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/late2
56d2e5c9f677 Merge tag 'input-for-v7.1-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
7cb5e123558a ASoC: dt-bindings: ti,tas2781: Add TAS5832 support
4e020fc4a49f Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
d5c9314c6eb6 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
beac3df556d7 arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number
38efe3b80720 arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0
07e928496fdc arm64: dts: amlogic: t7: khadas-vim4: fix board model name
c828e67ccf0b arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7
220be0c101be arm64: dts: amlogic: t7: khadas-vim4: fix memory layout for 8GB RAM
a06229b324b2 arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
98f6092acebd Merge tag 'leds-next-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
f5a2c75e3a5f Merge tag 'mfd-next-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
279a1fba5075 Merge tag 'apple-soc-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/late2
e9784c8ff00c ARM: dts: bcm4709: fix bus range assignment
18a3d9aa0dde Merge tag 'mvebu-dt64-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/late2
5acc2e2ce8d6 Merge branch 'arm/fixes' into soc/late2
78429b877ad3 spi: fix explicit controller deregistration
f7ac3130cae3 dt-bindings: input: add GPIO charlieplex keypad
8d5d5d159ac8 dt-bindings: input: add settling-time-us common property
b58509496cad dt-bindings: input: add debounce-delay-ms common property
86dee22604ab Merge tag 'i2c-host-7.1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
b1248825bf5b Merge tag 'usb-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
ac6494ba99c1 Merge tag 'tty-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
2a6e4c102682 Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
bb9574141067 Merge tag 'i2c-for-7.1-rc1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
bd7bfe699e0d Merge tag 'mtd/for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
0d2987c58e9e Merge tag 'rproc-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
ab19fe96ca0c Merge tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
a57fa632ff20 Merge tag 'for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux
21e4c2d71d36 Merge tag 'nand/for-7.1' into mtd/next
63ba676c3a52 Merge tag 'for-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
64623f2366d7 Merge tag 'hid-for-linus-2026041601' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
068d16b13b47 Merge tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
def8c67c21c5 Merge tag 'phy-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
f5c769efcd23 Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
f48a88cbba08 Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
69164ce9aa48 Merge tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
a725adedee9a Merge tag 'mm-nonmm-stable-2026-04-15-04-20' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
ac059cf66e92 Merge branch 'for-7.1/winwing' into for-linus
ebba67d240e9 Merge branch 'for-7.1/core-v2' into for-linus
81dd31d81b00 Merge branches 'clk-samsung', 'clk-qcom', 'clk-round', 'clk-sai' and 'clk-cleanup' into clk-next
63dd3374ca84 Merge branches 'clk-tenstorrent', 'clk-rockchip', 'clk-imx' and 'clk-allwinner' into clk-next
134c24ea9735 Merge branches 'clk-fixes', 'clk-renesas', 'clk-rpi', 'clk-eswin' and 'clk-mediatek' into clk-next
b59f32615b94 dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible
785a7287525c dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints
6ce7e903c8cb dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link
ae6d703dd47b dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link
bac91a1a2afa dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes
75f472a7bdd7 Merge tag 'v7.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
febc372ccfe6 Merge tag 'iommu-updates-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
1e80b541f285 Merge tag 'ata-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
b35865b538c0 Merge tag 'pci-v7.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
f473fc1514c5 Merge tag 'hwmon-for-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
ca19299e2835 Merge tag 'spi-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
1f6298fbb0f1 Merge tag 'regulator-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
ec806ea6381b Merge tag 'pmdomain-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
7a964c32ab91 Merge tag 'mmc-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
917aa3291bee Merge tag 'pwm/for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
87bc51a7db62 dt-bindings: qcom,pdc: document the Hawi Power Domain Controller
d3eb4717204e Merge tag 'sound-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f0a247d3c982 Merge tag 'drm-next-2026-04-15' of https://gitlab.freedesktop.org/drm/kernel
e74db5b6d2ca Merge tag 'media/v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
22cda52e7976 update Sean's email address
6dd03e20b8b1 Merge tag 'net-next-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
72a4f7ad5bce Merge tag 'powerpc-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
085503707412 dt-bindings: i2c: cnxt,cx92755-i2c: Convert to DT schema
7db338b248ab arm64: dts: apple: Fix spelling error
c990de46c8b8 dt-bindings: Update Sasha Finkelstein's email address
29ac81b6f5cc Merge tag 'i2c-host-7.1-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
840b9bbbf5a5 Merge tag 'irq-drivers-2026-04-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
2d9d66836ad8 Merge tag 'ti-k3-dt-for-v7.1-part2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
f7f34524d88f spi: dt-bindings: fsl: Correct GPIO flags in the example
c9ff4501b3e7 ASoC: SOF: Intel: NVL/NVL-S: add platform name
1ab94b0b5264 Merge tag 'pwrseq-updates-for-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
b71204c48bd8 Merge tag 'gpio-updates-for-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
1c3e973d824a Merge tag 'thermal-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
c7a6bd4157fc Merge tag 'pm-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
eadf51e63cf6 dt-bindings: ARM: arm,vexpress-scc: convert to DT schema
7a1b55142b2d dt-bindings: sram: Document qcom,hawi-imem compatible
c5de657d33f9 Merge branch 'pci/controller/rzg3s-host'
85e2e8abd845 Merge branch 'pci/controller/dwc-tegra194'
7c3c757b27a6 Merge branch 'pci/controller/dwc-eswin'
b8b036c74397 Merge branch 'pci/controller/dwc-andes-qilai'
c2296648a70c Merge branch 'pci/controller/dwc'
8efda8ef966a MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
65240af9d72d MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
84a9f2555fbd dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
85bced4b10a1 dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC
9b735b21418b dt-bindings: timestamp: Add Tegra264 support
c3320c3597ce dt-bindings: net: qcom,ipa: add Milos compatible
c71ba432a9b8 dt-bindings: net: document Microchip PIC64-HPSC/HX MDIO controller
b22fa850a05c dt-bindings: net: dsa: nxp,sja1105: make spi-cpol optional for sja1110
9753930e4f7e ASoC: dt-bindings: rockchip: convert rk3399-gru-sound to DT Schema
324c4c0a3268 Merge tag 'wireless-next-2026-04-10' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
49a5c0d32f50 dt-bindings: net: ti: k3-am654-cpsw-nuss: Add ti,j722s-cpsw-nuss compatible
f22f59b45ba6 dt-bindings: dpll: add ref-sync-sources property
3dcfe1c66ed3 dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
9f1518a1b6ff dt-bindings: clock: fsl-sai: Document i.MX8M support
9cb7d912bd00 Merge tag 'qcom-clk-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
67e446d2ad6b Merge tag 'samsung-clk-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
8bd24a13336c Merge tag 'clk-imx-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
6a40384a2620 Merge tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
0208eb1fc4b6 Merge tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
97030b8a4970 Merge tag 'tenstorrent-clk-for-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux into clk-tenstorrent
26978929a176 dt-bindings: usb: dwc3: add support for StarFive JHB100
f1d1027d33be dt-bindings: usb: atmel,at91sam9rl-udc: convert to DT schema
9dfa98bd545a dt-bindings: usb: atmel,at91rm9200-udc: convert to DT schema
b07ff7e0d236 dt-bindings: usb: generic-ehci: fix schema structure and add at91sam9g45 constraints
08871f3ea253 dt-bindings: usb: generic-ohci: add AT91RM9200 OHCI binding support
e55a7fb3c6f8 arm: dts: at91: remove unused #address-cells/#size-cells from sam9x60 udc node
117292216644 Merge tag 'mvebu-fixes-7.0-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
f1326cd20e6a Merge tag 'sunxi-dt-for-7.1-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
5b4bc83a7247 Merge tag 'qcom-arm64-for-7.1-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
c6ed1424dba1 Merge tag 'riscv-soc-drivers-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
ae4d5fb36f76 Merge tag 'riscv-dt-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
f2ea6c961fe7 Merge tag 'imx-dt-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt
f852a02a89d1 Merge tag 'imx-fixes-7.0-2nd' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into arm/fixes
3ff983831a46 Merge tag 'v7.1-rockchip-dts32-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
faa011cea013 Merge tag 'v7.1-rockchip-dts32-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
03d689eaf95d dt-bindings: hwmon/pmbus: Add Infineon XDP720
d0f7f4b5aa63 Merge tag 'spacemit-dt-for-7.1-1' of https://github.com/spacemit-com/linux into soc/dt
83aaf82c5acf dt-bindings: hwmon: add support for MCP998X
e6589752e1fc dt-bindings: trivial-devices: Add sony,aps-379
ef39589097d5 dt-bindings: sram: Allow multiple-word prefixes to sram subnode
9fc637876b24 dt-bindings: sram: Document qcom,milos-imem
9b4de39737da Merge tag 'thermal-v7.1-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/thermal/linux
8a99652b10e8 Merge branch 'pm-cpufreq'
907e026f17f8 dt-bindings: net: realtek,rtl82xx: Document realtek,*-ssc-enable property
e919822174b5 dt-bindings: net: realtek,rtl82xx: Keep property list sorted
332a77bc04bf Merge tag 'drm-misc-next-fixes-2026-04-09' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
5b3ed185a262 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
77495e5a964c regulator: fix OF node imbalance on reuse
77c76927fd48 ASoC: Yet another round of SDCA fixes
78acd0a1899e Merge branches 'fixes', 'arm/smmu/updates', 'arm/smmu/bindings', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next
d40127bb0ddd arm64: dts: ti: k3: Use memory-region-names for r5f
cc5410cb9911 dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
fd4aabc43175 dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
b33df534461a dt-bindings: gpio: cavium,thunder-8890: Remove DT binding
22d94fbb1e33 dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
b3c5c3b2d911 dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
48cae9bce69f arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node
1d74c9d54c82 arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names
ce923a101054 dt-bindings: clock: qcom: Add Nord Global Clock Controller
f1d12cab58f0 dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
e4c21e80d44e dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
a381cde95f2a dt-bindings: PCI: tegra194: Add monitor clock support
c56d52c57129 ASoC: dt-bindings: hisilicon: Convert hi6210 I2S to dt-schema
a8853719c449 dt-bindings: wireless: ath10k: Add quirk to skip host cap QMI requests
7baeea04041e Add Renesas RZ/G3L RSPI support
34fa3bb983e5 spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3L SoC
b38f541ad606 pmdomain: Merge branch dt into next
708e56a8f1a6 dt-bindings: power: qcom,rpmhpd: Add RPMh power domain for Hawi SoC
3cfc66e84788 dt-bindings: net: wireless: add ath12k wifi device IPQ5424
29d874b1a513 dt-bindings: arm-smmu: qcom: Add compatible for Hawi SoC
6c0039f76170 dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles
37e55dc0fe16 dt-bindings: display: lt8912b: Drop redundant endpoint properties
79014a7ae4f4 ASoC: Merge up v7.0-rc7
2e02b8461790 dt-bindings: net: wireless: brcm: Add compatible for bcm43752
9baad1daefb4 dt-bindings: chrome: Add cros-ec-ucsi compatibility to typec binding
1b672a7a3adc dt-bindings: opp-v2: Fix example 3 CPU reg value
8857dc8eccef Merge v7.0-rc7 into drm-next
4bcfa14efd80 Merge tag 'icc-7.1-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
e623a8aee9c6 Merge tag 'extcon-next-for-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon into char-misc-next
2c9fe21f3423 dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
bce61840e54d dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
4fbdeafe9fa1 dt-bindings: nfc: nxp,nci: Document PN557 compatible
0ece9e722dc9 dt-bindings: remoteproc: qcom,milos-pas: Document Eliza ADSP
9b25554779d8 dt-bindings: remoteproc: qcom: Drop types for firmware-name
379fbe93e087 Merge tag 'cpufreq-arm-updates-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
f014e33d959a regulator: dt-bindings: qcom,qca6390-pmu: Document WCN6755 PMU
fb7a247d9682 regulator: dt-bindings: regulator-max77620: convert to DT schema
50a980721064 MIPS: dts: loongson64g-package: Switch to Loongson UART driver
c037bc79a0ca mips: dts: Add PCIe to EcoNet EN751221
4184278efe5a MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs
d6757c1bb81d MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers
c1535370dc20 dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider on EyeQ5
bb7adc8b4b1d Merge tag 'v7.0-rc7' into usb-next
d241d0e57f80 Merge tag 'v7.0-rc7' into char-misc-next
4518a2c38b9e ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards
c141e96e46f7 ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif
dfc1e02f2592 ARM: dts: imx25: rename node name tcq to touchscreen
4a164d1285d0 ARM: dts: imx: b850v3: Disable unused usdhc4
a8264cd78f06 ARM: dts: imx: b850v3: Define GPIO line names
65d84f13f612 ARM: dts: imx: b850v3: Use alphabetical sorting
49041b4030f8 ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning
f5bcd3c2e538 ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps
933222513273 ARM: dts: imx7ulp: Add CPU clock and OPP table support
43dcca60406c ARM: dts: imx7-mba7: Deassert BOOT_EN after boot
3ea29158ac9c ARM: dts: tqma7: add boot phase properties
b2e3a0729bb0 ARM: dts: imx7s: add boot phase properties
4b6782af628d ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems
1da9ad4669a1 ARM: dts: mba6ulx: add boot phase properties
4f6e8fd7c671 ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
ab978ad32009 ARM: dts: imx6ul/imx6ull: add boot phase properties
40bc5d55bc39 ARM: dts: imx6qdl-mba6: add boot phase properties
1fc3e0f278e9 ARM: dts: imx6qdl-tqma6: add boot phase properties
a3622193c472 ARM: dts: imx6qdl: add boot phase properties
f233350a91d6 ARM: dts: imx6qdl-tqma6: add missing labels
2be2157f574b ARM: dts: imx: add required clocks and clock-names for ccm
8b0b300bbf2f ARM: dts: imx6qdl: add label for system clocks
9406404092f3 ARM: dts: imx28-tx28: remove undocumented aliases
f633f34749e0 ARM: dts: imx28-tx28: rename compatible to "edt,edt-ft5206"
ed82f59d6def ARM: dts: imx28-sps1: remove undocumented fallback compatible "mr25h256"
de50efe1c7b8 ARM: dts: imx28: rename gpios-reset to reset-gpios of hx8357
92e59af49c67 ARM: dts: imx23/28: add "led-" prefix to LED subnodes
fd34349b54f2 ARM: dts: imx23: fix interrupt names for dma-controller@80024000
1384dd0d3bb1 ARM: dts: imx27: remove fsl,imx-osc26m from fixed-clock node
fcbe5fd5ebd7 ARM: dts: imx27-eukrea-cpuimx27: rename uart8250 to serial
797de836e617 ARM: dts: imx27-eukrea: replace interrupts with interrupts-extended
6e4a0d515afe ARM: dts: imx: remove redundant intermediate node in pinmux hierarchy
f4f9f47b2781 ARM: dts: imx: rename iomuxc to pinmux
76b0f88d3aab ARM: dts: imx6ull-dhcor: Handle both 1DX and 1YN WiFi on i.MX6ULL DHCOR
3f32cb33a613 ARM: dts: imx7s-warp: Remove data-lanes and clock-lanes for ov2680
660216f35628 ARM: dts: imx53-smd: Add power supply node for fsl,sgtl5000
f1f48294e26d ARM: dts: imx6qdl-sr-som-ti: use fixed-clock instead of clock-frequency
3dd9992cffa9 Merge tag 'microchip-dt64-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
1c41be8684c8 Merge tag 'at91-soc-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/drivers
f538f0b50dbe Merge tag 'at91-dt-7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
934577145ad6 Merge tag 'imx-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt
13cfc252c30d Merge tag 'tegra-for-7.1-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
fc7e7e48bee1 Merge tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
04855f43fcd6 Merge tag 'tegra-for-7.1-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
53d0748ab492 dt-bindings: PCI: imx6q-pcie: Add i.MX94 and i.MX943 SoCs
d566e77d0a1d dt-bindings: PCI: imx6q-pcie: Fix maxItems of clocks and clock-names
622db085da89 dt-bindings: rtc: add olpc,xo1-rtc to trivial-rtc
78b95e237576 dt-bindings: rtc: sc2731: Add compatible for SC2730
063e4386c821 Revert "dt-bindings: usb: cdns,usb3: document USBSSP controller support"
26706be99076 Merge tag 'drm-msm-next-2026-04-02' of https://gitlab.freedesktop.org/drm/msm into drm-next
140ea17600e0 arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT
8cf6340354cd arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT
e07939a1b80e arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT
1c3fa7e7ddc9 Merge tag 'qcom-arm64-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
2efa937caeaa Merge tag 'omap-for-v7.1/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/arm
4f48824cfd91 Merge tag 'v7.1-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/arm
a59239316fee Merge tag 'ti-k3-dt-for-v7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/arm
54a3d7e83327 ARM: dts: st: spear: remove undocumented thermal_flags property
b70146f88a4a Merge tag 'qcom-drivers-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
5339f7208547 Merge tag 'reset-for-v7.1' of https://git.pengutronix.de/git/pza/linux into soc/drivers
7f8bf6a294d0 Merge tag 'imx-bindings-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/drivers
d8ee7d21b9f1 arm64: dts: qcom: Add the Lenovo IdeaCentre Mini X
a4e9eff44482 dt-bindings: arm: qcom: Document the Lenovo IdeaCentre Mini X
6044dd5df286 arm64: dts: qcom: sdm845-shift-axolotl: Enable TFA9890 codec
b08152726a23 arm64: dts: qcom: sdm845-shift-axolotl: Set higher touchscreen i2c clock
19783071a29e arm64: dts: qcom: sdm845-shift-axolotl: Enable sdcard
3ea8601a165a arm64: dts: qcom: talos: Add clocks for QoS configuration
cef07a8f45ff arm64: dts: qcom: talos-evk-camera: Add DT overlay
09a2380adb68 arm64: dts: qcom: talos: Add camera MCLK pinctrl
cbfa92962e49 arm64: dts: qcom: talos: Add CCI definitions
101aec7ac902 arm64: dts: qcom: talos: Add camss node
166122819bbc arm64: dts: qcom: talos: Add EL2 overlay
fa4bb8693709 arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board
06026c986a14 arm64: dts: qcom: talos/qcs615-ride: Fix inconsistent USB PHY node naming
70406ac56e92 dt-bindings: arm: qcom: talos-evk: Add QCS615 Talos EVK SMARC platform
b92609dc5d59 arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
31bf51d878b4 arm64: dts: qcom: talos: Add GPU cooling
119629d7f384 arm64: dts: qcom: talos: Add gpu and rgmu nodes
35959bd2e7e6 arm64: dts: qcom: talos: add the GPU SMMU node
a4aad3bc2ed3 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
84bf7a302801 Merge tag 'reset-fixes-for-v7.0-2' into reset/next
418dbcdd277b ASoC: qcom: q6dsp: few fixes and enhancements
ef82307587be ASoC: dt-bindings: qcom: add LPASS LPI MI2S dai ids
6811df401adc dt-bindings: misc: Describe FPC202 LED features
dfc7a851ab39 dt-bindings: nvmem: rockchip,otp: Add compatible for RK3528
d5b917feb776 dt-bindings: nvmem: rockchip,otp: Add support for RK3562 and RK3568
883d48c34727 dt-bindings: nvmem: sl28cpld: Drop sa67mcu compatible
3a91f0ad6b73 dt-bindings: nvmem: qfprom: Add Kaanapali compatible
753631310b23 dt-bindings: misc: qcom,fastrpc: Add compatible for Glymur
b217d8b48bae dt-bindings: i2c: realtek,rtl9301-i2c: extend for clocks and RTL9607C support
501c0ea4eab3 Merge tag 'stm32-bus-firewall-for-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/drivers
bd33620fc5f7 Merge tag 'scmi-updates-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
83d3455675ad Merge tag 'memory-controller-drv-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
8fd4db03d1f8 Merge tag 'samsung-drivers-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
51ead9bc83fd Merge tag 'sunxi-dt-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
4b1d5d09cb17 Merge tag 'qcom-arm32-for-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
241684a9d6c1 Merge tag 'hisi-arm64-dt-for-7.1' of https://github.com/hisilicon/linux-hisi into soc/dt
efca6f8d93b1 Merge tag 'socfpga_updates_for_v7.1_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
bc928d214f9e Merge tag 'thead-dt-for-v7.1-p2' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
53e9e570dbfc Merge tag 'cix-dt-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt
a6c78c340783 Merge tag 'renesas-dts-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
4d9e71142340 Merge tag 'stm32-dt-for-7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
cb0e3de184fc Merge tag 'samsung-dt-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
c690344645a2 Merge tag 'samsung-dt64-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
982defe50b3e Merge tag 'arm-soc/for-7.1/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
8a4b1c9b2220 dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
58a70ae27831 dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
df68a162fff3 dt-bindings: input: awinic,aw86927: Add Awinic AW86938
128d1d591fb1 dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
63b20ebcd9fe arm64: dts: qcom: sdm845-lg-common: Add chassis-type
11d5a1273b36 arm64: dts: qcom: sdm845-lg: Add wifi nodes
28563ff8a3a1 arm64: dts: qcom: sdm845-lg-judyln: Add display panel
d059685725b3 arm64: dts: qcom: sdm845-lg-judyln: Add lab/ibb
c6baa9df4b20 arm64: dts: qcom: sdm845-lg-common: Add LEDs
e8d8769e9c9d arm64: dts: qcom: sdm845-lg-judyln: Add battery and charger
6e3e1b2219ba arm64: dts: qcom: sdm845-lg: Add uarts and Bluetooth
85a53171e368 arm64: dts: qcom: sdm845-lg-common: Enable qups and their dma controllers
170e05ba5894 arm64: dts: qcom: sdm845-lg-common: Enable venus
66a473c21903 arm64: dts: qcom: sdm845-lg-judyp: Define firmware paths for judyp
d666a6c97efb arm64: dts: qcom: sdm845-lg-judyln: Add firmware nodes, change path
4e555621f33e arm64: dts: qcom: sdm845-lg-common: Sort nodes and properties
e401a35c1169 arm64: dts: qcom: glymur-crd: Enable DisplayPort support
c23604f3a133 Merge tag 'arm-soc/for-7.1/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
bb771e3d3a04 Merge tag 'nuvoton-arm64-7.1-devicetree-0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
154198d80cbf Merge tag 'aspeed-7.1-devicetree-0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
b251cb5e7478 pmdomain: Merge branch dt into next
85f7a0a0bfc7 dt-bindings: can: mcp251xfd: add microchip,xstbyen property
5ed7e0053cdd powerpc: wii: Fix LED name pattern
6a2616b2bad7 powerpc: wii: Fix GPIO key name pattern
bc637d714ec9 powerpc: wii: Add unit address to /memory
3c96a6430a4d ARM: dts: am335x: Add Seeed Studio BeagleBone HDMI cape overlay
7ebb87dadff1 dt-bindings: power: reset: cortina,gemini-power-controller: convert to DT schema
55231e809114 dt-bindings: i2c: intel,ixp4xx-i2c: Convert to DT schema
40c788aa6e51 Merge tag 'drm-rust-next-2026-03-30' of https://gitlab.freedesktop.org/drm/rust/kernel into drm-next
823759a4d3e2 ARM: dts: qcom: msm8974: Drop RPM bus clocks
6c4eb4ff6a59 dt-bindings: display/msm/gpu: Drop redundant reg-names in one if:then:
6302f459a016 dt-bindings: display/msm/gmu: Add SDM670 compatible
9e1aa17e5088 dt-bindings: connector: add pd-disable dependency
660ef1fe3a53 riscv: dts: microchip: update mpfs gpio interrupts to better match the SoC
28a9d2e27dc1 dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
b4fd7580b62d dt-bindings: connector: Add PCIe M.2 Mechanical Key E connector
883af48c8cfa dt-bindings: serial: Document the graph port
99767d1e2421 dt-bindings: hwmon: isl68137: Add compatible strings for RAA228942 and RAA228943
9c637aa812e3 dt-bindings: hwmon: moortec,mr75203: adapt multipleOf for T-Head TH1520
34d714cc9e53 dt-bindings: trivial-devices: Add Delta Q54SN120A1 and Q54SW120A7
d166b189d4fb dt-bindings: hwmon: convert npcm750-pwm-fan to DT schema
e147e1c2a229 dt-bindings: trivial-devices: Add support for XDPE1A2G5B/7B
bd39dda8f947 dt-bindings: hwmon: add Aosong AHT10/AHT20/DHT20 to trivial devices
dc42e4c75721 dt-bindings: hwmon: ti,ina2xx: Add INA234 device
2ea92013330a hwmon: (bt1-pvt) Remove not-going-to-be-supported code for Baikal SoC
974e1042f54c arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts
b410bc96c410 dt-bindings: intel: Add Agilex5 SoCFPGA modular board
8dde2024b3cb arm64: dts: socfpga: stratix10: Add emmc support
bc40b72bfc27 dt-bindings: altera: Add fallback compatible for Stratix 10 SoCDK eMMC variant
4320c9515209 BackMerge tag 'v7.0-rc6' into drm-next
c3aefd0ce112 ASoC: Merge up fixes
35b902ac9d47 dt-bindings: serial: renesas,rsci: Document RZ/G3L SoC
1602416c108c dt-bindings: serial: 8250: Add Loongson 3A4000 uart compatible
fbb213ef7b79 dt-bindings: usb: maxim,max33359: Add supply property for vbus
4ad32eb1fc4a dt-bindings: mfd: maxim,max77759: reference power-supply schema and add regulator property
95ef2fd7c2a2 dt-bindings: usb: Add support for Terminus FE1.1s USB2.0 Hub controller
28fbb86f7ad7 dt-bindings: usb: qcom,snps-dwc3: Add constraints for IPQ5424 and IPQ9574
a8aeb4bac1a6 dt-bindings: usb: qcom,snps-dwc3: Add constraints for SM4250
6edc573d462e dt-bindings: usb: qcom,snps-dwc3: Add constraints for SM6375
370764609ccb dt-bindings: usb: qcom,snps-dwc3: Add missing clocks and interrupts constraints
8e68899667b3 dt-bindings: usb: qcom,snps-dwc3: Drop stale child node comment
fe82f3b8d0f9 dt-bindings: usb: cdns,usb3: document USBSSP controller support
073e984136eb dt-bindings: remoteproc: k3-r5f: Add memory-region-names
0d5d64fce838 dt-bindings: remoteproc: k3-r5f: Split up memory regions
a77be6db0eda dt-bindings: usb: richtek,rt1711h: Add Hynetek HUSB311
76a8cd0b21b3 dt-bindings: usb: richtek,rt1711h: Switch ETEK ET7304 to use a fallback compatible
e0c111c11015 dt-bindings: vendor-prefixes: Add Hynetek Semiconductor Co., Ltd.
cc743358dda2 dt-bindings: usb: dwc3: spacemit: add support for K3 SoC
8714c994be20 dt-bindings: usb: nxp,ptn5110: add optional orientation-gpios property
633d7d470607 dt-bindings: usb: document the Renesas UPD720201/UPD720202 USB 3.0 xHCI Host Controller
be15d6deb688 dt-bindings: usb: ti,usb8041: Support nested USB hubs
e09c99a0e66c dt-bindings: usb: qcom,snps-dwc3: Document the Eliza compatible
c055e0866607 regulator: mt6315: add regulator supplies
e24825c973d3 regulator: dt-bindings: mt6315: Add regulator supplies
138973ab329e arm64: dts: qcom: sm8250: Add missing CPU7 3.09GHz OPP
eb808b4982cf arm64: dts: qcom: sm8550-hdk: add support for the Display Card overlay
8f18496c9644 dt-bindings: clock: qcom: Add SM8750 GPU clocks
c2c73a13768a arm64: dts: qcom: msm8916-samsung-coreprimeltevzw: add device tree
a108fd710094 dt-bindings: qcom: Document samsung,coreprimeltevzw
33d35de20154 arm64: dts: qcom: msm8916-samsung-fortuna: Move SM5504 from rossa and refactor MUIC
17297ad6f5a9 dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
75309eeab545 dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
99f33441d2d7 arm64: dts: qcom: sdm670: add llcc
64e077963f36 arm64: dts: qcom: qcm6490-fairphone-fp5: Add front camera support
446487ec520a arm64: dts: qcom: qcm6490-fairphone-fp5: Sort pinctrl nodes by pins
befe11d6e34e arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses
9ee445827e1c arm64: dts: qcom: milos: Add CCI busses
17b140ab3032 dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
999a23f6fa15 arm64: dts: qcom: purwa-iot-evk: Enable UFS
5d6bf5a08d3c arm64: dts: qcom: eliza: Add thermal sensors
b5a37b768c9f arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP
3c70110e0d33 arm64: dts: qcom: sdm845-oneplus: Describe Wi-Fi/BT properly
da82565ad639 arm64: dts: qcom: sdm845-google: Describe Wi-Fi/BT properly
44654400deee arm64: dts: qcom: drop redundant zap-shader memory-region
2e5aead369bd arm64: dts: qcom: fix remaining gpu_zap_shader labels
ce45dfd0d8cf arm64: dts: qcom: msm8996: fix indentation in sdhc2 node
175b140ec027 arm64: dts: qcom: monaco-evk: enable UART6 for robot expansion board
01312becdef4 arm64: dts: qcom: lemans-evk: enable UART0 for robot expansion board
e705d5dc31ed arm64: dts: qcom: milos: Add missing CX power domain to GCC
a486c0781ae6 dt-bindings: clock: qcom: Add missing power-domains property
e26b3abfe544 arm64: dts: qcom: msm8939-asus-z00t: add regulators for ambient light and proximity sensor
70704bc4d663 arm64: dts: qcom: kaanapali: Duplicate whitespace cleanup
41fb9e094174 arm64: dts: monaco: extend fastrpc compute cb
48efb33720c1 arm64: dts: qcom: qcs6490-rb3gen2: Enable uPD720201 and GL3590
c78b5831a3d4 dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
174d7260b9be Merge drm/drm-fixes into drm-misc-next-fixes
01e3bb480051 dt-bindings: thermal: st,thermal-spear1340: convert to dtschema
b2bb26cda93d dts: riscv: spacemit: k3: add P1 PMIC regulator tree
cda03b931dd9 dts: riscv: spacemit: k3: Add i2c nodes
10aac04fe05f dt-bindings: net: macb: add property indicating timer adjust mode
3b719e3a86bd dt-bindings: net: cdns,macb: replace cdns,refclk-ext with cdns,refclk-source
c9935ec6d984 dt-bindings: mailbox: qcom-ipcc: Document the Eliza Inter-Processor Communication Controller
ece4de33731b arm64: dts: allwinner: enable h616 timer support
f298af9e2883 arm64: dts: allwinner: sun50i-h6: add UART DMA channels
6d1bd9c4cd07 arm64: dts: allwinner: sun50i-a64: add UART DMA channels
909e55756918 Merge tag 'renesas-pinctrl-for-v7.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
d37c32c158b4 arm64: tegra: Add Tegra264 GPIO controllers
d75156073d8c arm64: tegra: smaug: Enable SPI-NOR flash
0cd9d5b5c8bb arm64: tegra: Add Jetson AGX Thor Developer Kit support
2b337a189d80 dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit
e9bcd5aa9fa4 ARM: tegra: paz00: Configure WiFi rfkill switch through device tree
695725492e79 ARM: tegra: transformers: Add connector node
e896e8c2c428 ASoC: dt-bindings: mediatek,mt8173-rt5650-rt5514: convert to DT schema
a82824d6b6a9 arm64: tegra: Add PCI controllers on Tegra264
f0ade31f6400 arm64: tegra: Fix RTC aliases
6b42c2eef8bc arm64: tegra: Drop redundant clock and reset names for TSEC
35e4b6831b98 arm64: tegra: Fix snps,blen properties
735e795c76c5 dt-bindings: display: tegra: Document Tegra20 HDMI port
2ac492931939 dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings
391c09ee23e1 dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller
c159c8d749fe dt-bindings: memory: tegra210: Mark EMC as cooling device
6571ecefe535 dt-bindings: memory: Add Tegra210 memory controller bindings
655a9e209b86 dt-bindings: phy: tegra: Document Tegra210 USB PHY
b58062cc2302 dt-bindings: arm: tegra: Add missing compatible strings
1c8a21c89f81 dt-bindings: interrupt-controller: tegra: Fix reg entries
bea84ed1dbff dt-bindings: clock: tegra124-dfll: Convert to json-schema
a397f0154ef6 dt-bindings: phy: tegra-xusb: Document Type C support
2bd9f8332cb8 ARM: tegra: Add External Memory Controller node on Tegra114
2b4705598cf5 ARM: tegra: Add ACTMON node to Tegra114 device tree
4b0e897e5d9b ARM: tegra: lg-x3: Add node for capacitive buttons
789781ec6a8a ARM: tegra: lg-x3: Add USB and power related nodes
de5f16ee54cd ARM: tegra: lg-x3: Add panel and bridge nodes
6f6d2c2c9afb ARM: tn7: Adjust panel node
ac0c5ff25ce4 ARM: tegra: Add SOCTHERM support on Tegra114
a49de94ce895 arm64: dts: ti: k3-pinctrl: sort shift values numerically
61d318960441 arm64: dts: ti: k3-pinctrl: consistently use tabs for alignment
5cc1bf57266a arm64: dts: imx8qxp-mek: switch Type-C connector power-role to dual
3f509cd9f4e4 arm64: dts: imx8qm-mek: switch Type-C connector power-role to dual
2b46d84f153c arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
eecd6a98458f arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model
63084496b5c6 arm64: dts: lx2160a-cex7: add rtc alias
1e16cff3f997 arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
1eeb95a817b9 arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes
6eef2779e552 arm64: dts: lx2160a: add sda gpio references for i2c bus recovery
010dfcb18585 arm64: dts: lx2160a: rename pinmux nodes for readability
0dc3587d7b1b arm64: dts: lx2160a: remove duplicate pinmux nodes
17e0293ea036 arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
3ff06cef5b50 arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
bf57c9937c46 arm64: dts: freescale: imx8mp-moduline-display-106: add typec-power-opmode property
2d35e8cfaa19 arm64: dts: imx8mp-evk: Specify ADV7535 register addresses
b800c1889200 arm64: dts: imx8dxl-evk: Use audio-graph-card2 for wm8960-2 and wm8960-3
ad362eb27c9d arm64: dts: imx943-evk: Add pf09/53 thermal zone
e5bf7ad23755 arm64: dts: imx943-evk: Add fan node and enable active cooling on A55
5055cc3af145 arm64: dts: imx943-evk: Add nxp,ctrl-ids for scmi_misc
735475f83864 arm64: dts: imx943: Add thermal support
eea927631e7e arm64: dts: imx94: Add SCMI sensor/lmm/cpu nodes
75c932aeb583 arm64: dts: imx94: Add V2X/ELE mailbox nodes
17a7c497b8dc arm64: dts: imx94: Update pin headers
a2f59b438db6 arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support
fed2f589c0f7 arm64: dts: freescale: imx95-verdin: Add Yavia carrier board
0d16c567187a arm64: dts: freescale: imx95-verdin: Add Mallow carrier board
98db685f7b76 arm64: dts: freescale: imx95-verdin: Add Ivy carrier board
dfd3ad267af4 arm64: dts: freescale: imx95-verdin: Add Dahlia carrier board
eca52dcc7a57 arm64: dts: freescale: Add Verdin iMX95 support
3f733ba1edfc arm64: dts: imx8mp-tqma8mpql-mba8mp-ras314: add vcc supply for BT device
820a0fccf1a6 arm64: dts: freescale: imx93-tqma9352-mba93xxla-mini: Add WLAN/BT overlay
cbff3c0b42d5 arm64: dts: freescale: add initial device tree for TQMa93xx/MBa93xxLA-MINI
9e4f10075f15 arm64: dts: freescale: tqma8mqml/tqma8mxnl-mba8mx: Add dual-channel LVDS overlay
0e286e50ea4b arm64: dts: mba8mx: Add DSI->LVDS bridge IRQ
cc7b61b2c36d arm64: dts: imx95-15x15-evk: remove regulator-always-on for reg_m2_pwr
b048ebe4a606 arm64: dts: imx952-evk: Add PDM microphone sound card support
823f8854efb4 arm64: dts: imx952-evk: Add bt-sco sound card support
6747176927b9 arm64: dts: imx952-evk: Add sound-wm8962 support
291627095b4b arm64: dts: imx952: Add audio device nodes
688173aace54 arm64: dts: imx95-var-dart: Add support for Variscite Sonata board
04cfa236f72e arm64: dts: freescale: Add support for Variscite DART-MX95
c50dd5cb21e8 arm64: dts: imx91-var-dart: Add support for Variscite Sonata board
b2d16d6a804f arm64: dts: freescale: Add support for Variscite DART-MX91
38e5fe19f419 arm64: dts: imx95: Move funnel outside from soc
acb7d25561cb arm64: dts: imx8mn-tqma8mqnl-mba8mx: LVDS overlay: Reduce DSI burst clock to 600Mhz
7d12b795eb4e arm64: dts: imx8mm-tqma8mqml-mba8mx: LVDS overlay: Reduce DSI burst clock to 600Mhz
e0589814901a arm64: dts: imx8mm: Explicitly set DSI_PHY_REF clock as a child of CLK_24M
33b216cd7469 arm64: dts: freescale: add support for solidrun i.mx8mm som and evb
72977f81253f arm64: dts: freescale: add support for solidrun solidsense-n8 board
ec3d99a6a98f arm64: dts: imx8mp-hummingboard-iiot: add dt overlays for muxable ports
5c4b8cda2bf7 arm64: dts: freescale: add support for SolidRun i.MX8MP HummingBoard IIoT
be7000843f31 arm64: dts: imx8mm-var-som-symphony: Enable PCIe
aa93375c308b arm64: dts: imx8mm-var-som-symphony: Enable I2C4
4e3796da3f86 arm64: dts: imx8mm-var-som-symphony: Add TPM2 support
238244d9603b arm64: dts: imx8mm-var-som-symphony: Enable uSD on USDHC2
bcf6e7904de5 arm64: dts: imx8mm-var-som-symphony: Move USB configuration from SOM
84498d669ed0 arm64: dts: freescale: imx8mm-var-som: Rework WiFi/BT and add legacy dts
16db7b16f928 arm64: dts: freescale: imx8mm-var-som: Add MCP251xFD CAN controller
d37394702530 arm64: dts: freescale: imx8mm-var-som: Add support for WM8904 audio codec
d500201f4b2f arm64: dts: freescale: imx8mm-var-som: Update FEC support with MaxLinear PHY
ca8914c5714a arm64: dts: freescale: imx8mm-var-som: Align fsl,pins tables
dc774528a87e arm64: dts: freescale: imx8mm-var-som: Move UART4 description to Symphony
750822ce8ce8 arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts
3b8c2e1e9fc3 arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts
4f7ae4a8e4ab arm64: dts: imx8mp-kontron: Fix boot order for PMIC and RTC
163bbea3259c arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes
e1466cbf6a9d arm64: dts: imx93-tqma9352-mba91xxca: Add LVDS display overlay
e92b9de9a0c4 arm64: dts: imx93-tqma9352-mba91xxca: Add parallel display overlay
12970db7e01d arm64: dts: freescale: imx95-toradex-smarc: Support Cortex M7
9417cd82398e arm64: dts: imx8mm-tqma8mqml-mba8mx-tm070jvhg33: Remove compatible from overlay
bc21db7dd8c6 arm64: dts: imx8mn-tqma8mqnl-mba8mx-tm070jvhg33: Remove compatible from overlay
e6099c1443e3 arm64: dts: imx8mq-tqma8mq-mba8mx-tm070jvhg33: Remove compatible from overlay
62239dfb7001 arm64: dts: imx8mp-tqma8mpql-mba8mpxl-tm070jvhg33: Remove compatible from overlay
da25cd471dd1 arm64: dts: imx8mp-tqma8mpql-mba8mpxl-g133han01: Remove compatible from overlay
9137ef0b0ae5 arm64: dts: freescale: Add NXP S32N79-RDB board support
bb9c3471e1ad arm64: dts: freescale: Add NXP S32N79 SoC support
cebf69a6d507 arm64: dts: imx8mp-dhcom-pdk3: Use symbolic macro for IOMUXC_SAI2_TXC__GPIO4_IO25
d2abc91fe805 arm64: dts: imx943-evk: add Type-C and USB related nodes
4ee0cc5a13b3 arm64: dts: imx94: add USB nodes
1e41293c6f65 arm64: dts: imx91: Remove TMU's superfluous sensor ID
ff5ce34696d3 arm64: dts: tqma9352-mba91xxca: Change Ethernet PHY IRQ to IRQ_TYPE_LEVEL_LOW
4d6f5921bf4b arm64: dts: tqma9352-mba93xx*: Change Ethernet PHY IRQ to IRQ_TYPE_LEVEL_LOW
8dc22f45977a arm64: dts: imx8mp-frdm: Use symbolic macros for IOMUXC_SW_PAD_CTL_PAD
6037732cf159 arm64: dts: imx8mp: Make MX8MP_I2C_DEFAULT independent on drive strength
b53a193ef3a7 arm64: dts: freescale: imx8mp-tqma8mpql-mba8mp-ras314: fix UART1 RTS/CTS muxing
5126a2a9a43c arm64: dts: imx93-9x9-qsb: Add ontat,kd50g21-40nt-a1 panel
2158da498aa8 arm64: dts: imx8mp-beacon: remove fallback ethernet-phy-ieee802.3-c22
50edff50c595 arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)
817cdf4b9765 arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
d2a2aa555220 arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
975f3caeb910 arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
58e87a873b42 arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
8ad71da0189e arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
381db8921654 arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
71df345d8c95 arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
eff66c0855db arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
1307c4dc38a7 arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
b4ef12ba180a arm64: dts: imx8mp-debix-som-a: Correct PAD settings for PMIC_nINT
1a8a1e47fc0f arm64: dts: imx8mp-debix-model-a: Correct PAD settings for PMIC_nINT
c7d95e08177d Merge tag 'juno-updates-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
a01e6d715ad9 Merge tag 'mtk-dts32-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
92af5e826769 Merge tag 'mtk-dts64-for-v7.1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
bae1c9cf33f3 Merge tag 'thead-dt-for-v7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
3fca647f0c4d dt-bindings: thermal: qcom-tsens: Add Eliza SoC TSENS
1b00c19b9def Merge branch 'icc-msm8974' into icc-next
fdb305c5a574 Merge tag 'mediatek-drm-next-20260325' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
9d4ff4420846 arm64: dts: hisilicon: Rename dwmmc nodes to mmc
cb821afd0b40 arm64: dts: ti: k3-am642-evm: Add ICSSG0 overlay for dual EMAC support
f063ab913268 arm64: dts: ti: k3-am62p-verdin: Add Zinnia
b78a10c963f3 arm64: dts: ti: k3-am62p-verdin: Add SPI_1_CS as GPIO
3edc0d871b41 arm64: dts: ti: k3-am62p-verdin: Split UART_2 pinctrl group
cee895305457 arm64: dts: ti: k3-am62-verdin: Add Zinnia
48ccc5d72c0c arm64: dts: ti: k3-am62-verdin: Split UART_2 pinctrl group
7a1af59cfea1 arm64: dts: ti: k3-am62-verdin: Fix SPI_1 GPIO CS pinctrl label
13c169bda967 dt-bindings: arm: ti: Add verdin am62/am62p zinnia board
2b642ac67a88 dt-bindings: remove unimplemented AXI snps,kbbe snps,mb and snps,rb
e63919f16fb8 Merge tag 'drm-misc-next-2026-03-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
3358cee385b9 riscv: dts: spacemit: enable PCIe ports on Milk-V Jupiter
42c51f417b62 riscv: dts: spacemit: enable USB 3 ports on Milk-V Jupiter
7a0b4f192dd3 riscv: dts: spacemit: enable QSPI and add SPI NOR on Milk-V Jupiter
a97c112b631a riscv: dts: spacemit: add i2c aliases on Milk-V Jupiter
ebf52d7c3c21 riscv: dts: spacemit: add 24c04 eeprom on Milk-V Jupiter
469ae95d18e3 riscv: dts: spacemit: add LEDs for Milk-V Jupiter board
d27cf9ce8bd3 arm64: dts: ti: k3-j721s2: Make MAIN domain system control bus a simple-bus
c502fb289d7f arm64: dts: ti: k3-j7200: Make MAIN domain system control bus a simple-bus
06d329e6525a arm64: dts: ti: k3-am62-lp-sk: Enable internal pulls for MMC0 data pins
92ff4163e187 arm64: dts: ti: k3-am62l3-evm: Disable MMC1 internal pulls on data pins
d62e93542d91 arm64: dts: ti: k3-am62p5-sk: Disable MMC1 internal pulls on data pins
cc840a891818 arm64: dts: ti: k3-am62d2-evm: Enable Main UART wakeup
b80c6c67d8ee arm64: dts: ti: k3-am62l3-evm: Enable Main UART wakeup
e2ec79484a30 arm64: dts: ti: k3-am62p5-sk: Enable Main UART wakeup
38351d82654c arm64: dts: ti: k3-am62a7-sk: Enable Main UART wakeup
ee391b4fdfe4 arm64: dts: ti: k3-am62x-sk-common: Enable Main UART wakeup
acb6af307051 dt-bindings: net: nuvoton: Add schema for Nuvoton MA35 family GMAC
222b0f0b5211 dt-bindings: i2c: spacemit: k3: Add compatible
c6dc55edf825 dt-bindings: iio: amplifiers: ad8366: add adrf5702/3 support
d0b213838e1d dt-bindings: iio: adc: amlogic,meson-saradc: add S4 compatible
f96cd0460791 dt-bindings: spmi: qcom,x1e80100-spmi-pmic-arb: Document Eliza compatible
bb449c809c4a Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
d65a1481a9ff dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties
cb6031803d07 ARM: dts: renesas: Drop KSZ8041 PHY C22 compatible strings
b2cf11c29b17 ARM: dts: renesas: rza2mevb: Drop RTL8201F PHY C22 compatible string
73b941165a65 ARM: dts: renesas: r8a7742-iwg21d-q7-dbcm-ca: Drop KSZ8081 PHY C22 compatible string
7e1dc309e555 arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
fbf9b2379705 arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
a3f42aaa76ca arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
7f08484dca12 arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
33e3d98f261d Merge tag 'renesas-r9a08g046-dt-binding-defs-tag1' into renesas-dts-for-v7.1
9be9b3c538e3 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add versa3 clock generator node
eab8b4b57b9c dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC
6c0052dccdb5 dt-bindings: interconnect: qcom,msm8974: use qcom,rpm-common
0c57071ddc14 dt-bindings: interconnect: qcom,msm8974: drop bus clocks
2fa44bb4aff7 dt-bindings: arm: fsl: add Verdin iMX95
b2811d2e826f dt-bindings: arm: fsl: add MBa93xxLA-MINI
6af9c6e9a368 dt-bindings: arm: add bindings for TQMa95xxLA
bebfcdaacd8b dt-bindings: arm: lpc: add missed lpc43xx board
550dd2e98326 dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board
e1d10fec7b05 dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support
f54bb6714f5c dt-bindings: arm: fsl: Add compatible for i.MX8MP audio board (version 2)
8ff411118cea dt-bindings: arm: fsl: Add various solidrun i.MX8M boards
bc17d83e65c2 dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoC
396f09ce1da5 dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for interrupt-names
da5573ddac71 dt-bindings: firmware: qcom,scm: Document ipq9650 SCM
793315d3e100 arm64: dts: qcom: hamoa-evk: Add DP0/DP1 audio playback support
f32edc44c572 dt-bindings: interrupt-controller: Add LS7A PCH LPC
43ee646a01ea arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts
5bb2801feec9 arm64: dts: qcom: eliza: Add missing msi-parent for UFS
112a1ee4cc4d arm64: dts: qcom: eliza: Add missing CX power domain to GCC
06396c3ced21 arm64: dts: qcom: eliza: Coding style clean-ups
a8c4209fa6b9 arm64: dts: qcom: patch mahua thermal zones by label
908dfe21a347 arm64: dts: qcom: purwa: deduplicate thermal sensors with Hamoa
74ec667d7b78 arm64: dts: qcom: glymur-crd: Enable WLAN and Bluetooth
c9b811eb4fe6 arm64: dts: qcom: kodiak: Add LPASS I2S2 pinctrl definitions
921358e8a3b8 arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support
64e302d2f723 dt-bindings: qcom: add ipq5210 boards
ac4e4f40c8eb Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into HEAD
68084d3da4ee arm64: dts: qcom: sm8750: Enable TSENS and thermal zones
43aa073b3862 arm64: dts: qcom: mahua: Fix mahua bwmon
0f587b81265b arm64: dts: qcom: glymur: Add missing opp entry
c44036d18a93 arm64: dts: qcom: lemans: Correct QUP interrupt numbers
2d1d47b9d92f arm64: dts: qcom: qrb5165-rb5: Drop redundant non-controllable supplies
dad73ed780f9 arm64: dts: qcom: qrb4210-rb2: Drop redundant non-controllable supplies
9f8a5c18f89f arm64: dts: qcom: qrb2210-rb1: Drop redundant non-controllable supplies
d4bba29fbdbc arm64: dts: qcom: qcs615-ride: Drop redundant non-controllable supplies
fadec7f22c91 arm64: dts: qcom: lemans-ride: Drop redundant non-controllable supplies
d88a172ac406 arm64: dts: qcom: sm8650: Drop redundant VSYNC pin state
5a0cbbfa0f8d arm64: dts: qcom: sm8550: Drop redundant VSYNC pin state
115d66b7407c arm64: dts: qcom: sdm845-axolotl: Drop redundant VSYNC pin state
dd7dc80795a2 arm64: dts: qcom: msm8998: Drop redundant VSYNC pin state
b3e86e016b53 arm64: dts: qcom: msm8996: Drop redundant VSYNC pin state
43a221fac0b1 arm64: dts: qcom: pq5332-rdp-common: Enable QPIC SPI NAND support
9d5239baffdb arm64: dts: qcom: ipq5424-rdp466: Enable QPIC SPI NAND support
f55d029cffcf arm64: dts: qcom: ipq5332: Add QPIC SPI NAND controller support
0576f2696224 arm64: dts: qcom: ipq5424: Add QPIC SPI NAND controller support
340d342ad8c8 arm64: dts: qcom: lemans-evk: Enable the tertiary USB controller
65d975992d00 arm64: dts: qcom: lemans: Add role-switch support and HS endpoint for tertiary USB controller
25c06f602234 arm64: dts: qcom: lemans-evk: Rename vbus regulator for Primary USB controller
09bdcfd28451 arm64: dts: qcom: lemans-evk: Enable GPIO expander interrupt for Lemans EVK
f59271b0c60c arm64: dts: qcom: sm8650: Explicitly describe the IPA IMEM slice
294cc391464d arm64: dts: qcom: sm8550: Explicitly describe the IPA IMEM slice
e6c54173ceb0 arm64: dts: qcom: sm8350: Explicitly describe the IPA IMEM slice
7e5bd5fe9a4e arm64: dts: qcom: sm6350: Explicitly describe the IPA IMEM slice
7625a2222d0b arm64: dts: qcom: sdm845: Explicitly describe the IPA IMEM slice
355950a39e26 arm64: dts: qcom: sc7280: Explicitly describe the IPA IMEM slice
eff8f4df5d0e arm64: dts: qcom: sc7180: Explicitly describe the IPA IMEM slice
f0f20e145f18 arm64: dts: qcom: lemans-evk: Add IFP Mezzanine
fda2b603a1fc arm64: dts: qcom: monaco-evk: Add IFP Mezzanine
1f645154ff1b arm64: dts: qcom: sc7280-chrome-common: disable Venus
c60c4d66b19e arm64: dts: qcom: sm8150-hdk: describe WiFi/BT properly
ae2a2fdba93c arm64: dts: qcom: sdm845-db845c: describe WiFi/BT properly
801af787ec1f arm64: dts: qcom: sda660-ifc6560: describe WiFi/BT properly
603fa2a5ac54 arm64: dts: qcom: qrb4210-rb2: describe WiFi/BT properly
fc2bc44a6d54 arm64: dts: qcom: qrb2210-rb1: describe WiFi/BT properly
b5e928298801 arm64: dts: qcom: Add Redmi Go
a00cc16a976d arm64: dts: qcom: Add Redmi 4A
4a02e8d1781f dt-bindings: arm: qcom: Add Redmi 4A and Go
aeed4d9b2ee3 arm64: dts: qcom: msm8917-xiaomi-wingtech: Add goodix touch
3894686b0785 arm64: dts: qcom: Make a common base from Redmi 5A
f0f731265a62 arm64: dts: qcom: msm8917-xiaomi-riva: Fix board-id for all bootloader
26add387db0b arm64: dts: qcom: milos-fairphone-fp6: Enable UFS
424eeb705cad arm64: dts: qcom: milos: Add UFS nodes
85fbf558ee75 arm64: dts: qcom: add basic devicetree for Ayaneo Pocket S2 gaming console
bf1bc3229b7a arm64: dts: qcom: sm8650: Add sound DAI prefix for DP
f7ceb65c7000 dt-bindings: arm: qcom: document the Ayaneo Pocket S2
e139a936efc1 dt-binding: vendor-prefixes: document the Ayaneo brand
bc26f865b901 arm64: dts: qcom: sdm845-xiaomi-beryllium: Mark l1a regulator as powered during boot
7850c018a521 arm64: dts: qcom: hamoa/purwa: Flatten usb controller nodes
c975be6da66a arm64: dts: qcom: purwa-iot-evk: Add SDC2 node for purwa iot evk board
c5bdb8192db7 arm64: dts: qcom: sm7225-fairphone-fp4: Fix conflicting bias pinctrl
ced4468a8d50 arm64: dts: qcom: monaco-evk: add lt8713sx bridge with displayport
bf624005367a arm64: dts: qcom: milos: Add LPASS LPI pinctrl node
90c7399d23cf arm64: dts: qcom: sdm845-sony-xperia-tama: Add bluetooth
07915897519a arm64: dts: qcom: sdm845-sony-xperia-tama: Correct uart instances
c270ea5619a5 arm64: dts: qcom: sdm845-oneplus: Add alert-slider
fd4f32244b15 arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen
ea798d79dac8 arm64: dts: qcom: glymur-crd: Enable eDP display support
3bb512264646 arm64: dts: qcom: glymur: Describe display-related nodes
cfa0d2f3c0c8 arm64: dts: qcom: glymur-crd: Enable USB support
b81bf1cc7199 arm64: dts: qcom: glymur: Add USB related nodes
8fae6826d032 arm64: dts: qcom: glymur: Add glymur BWMONs
55bc5212f217 arm64: dts: qcom: kaanapali-mtp: Enable display DSI devices
37b43c014372 arm64: dts: qcom: kaanapali: add display hardware devices
78e983fe1389 arm64: dts: qcom: kaanapali-mtp: Enable bluetooth and Wifi
8171c1caeb25 arm64: dts: qcom: kaanapali-qrd: Add PMIC support
3bdaf792f54f arm64: dts: qcom: kaanapali-mtp: Add PMIC support
702b4275abeb arm64: dts: qcom: kaanapali: Add PMIC devices
09c1ddef9c69 arm64: dts: qcom: kaanapali: Add support for MM clock controllers for Kaanapali
e60f25e9b40b arm64: dts: qcom: kaanapali-mtp: Add audio support (WSA8845, WCD9395, DMIC)
14207d68c646 arm64: dts: qcom: kaanapali-qrd: Enable ADSP and CDSP
082b7e838b87 arm64: dts: qcom: kaanapali-mtp: Enable ADSP and CDSP
017252793424 arm64: dts: qcom: kaanapali: Add support for audio
5cf47f586fb3 arm64: dts: qcom: kaanapali: Add ADSP and CDSP for Kaanapali SoC
5d29941da470 arm64: dts: qcom: kaanapali: Add TSENS and thermal zones
22a0f82ebb41 arm64: dts: qcom: kaanapali: Add QUPv3 configuration for serial engines
07c7f7900947 arm64: dts: qcom: kaanapali: add coresight nodes
a28d92572015 arm64: dts: qcom: hamoa-iot-evk: Enable UFS
0d7b731cb5b8 arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
6d02a7984d4c arm64: dts: qcom: Add Arduino Monza (VENTUNO Q) board support
dbdcba955a24 dt-bindings: arm: qcom: add Arduino Monza, VENTUNO Q
bc9d6c53233c arm64: dts: qcom: Add Monaco Monza SoM
e02fb58155a9 arm64: dts: qcom: monaco: add dt entry for lpass lpi pinctrl
02e428f31579 arm64: dts: qcom: monaco: Add missing usb-role-switch property
c6173905230c arm64: dts: qcom: monaco: Add HS/SS endpoints for USB1 controller
dfbc109f4f59 arm64: dts: qcom: msm8916-wiko-chuppito: add initial devicetree
9deb8d0745b8 dt-bindings: arm: qcom: add wiko,chuppito compatible string
0f9ca5c400a3 dt-bindings: vendor-prefixes: add WIKO SAS
638d5d9b0045 arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1
217d7c14d168 arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0
8b15383481ca arm64: dts: qcom: sm8650: Enable UHS-I SDR50 and SDR104 SD card modes
d4e535a5de82 arm64: dts: qcom: sm8550: Enable UHS-I SDR50 and SDR104 SD card modes
855d4b09fa36 arm64: dts: qcom: sm8450: Enable UHS-I SDR50 and SDR104 SD card modes
526e4b51b39d arm64: dts: qcom: hamoa: Fix xo clock supply of platform SD host controller
01a495ae27e2 arm64: dts: qcom: sm8650: Fix xo clock supply of SD host controller
80b7d34ff4e0 arm64: dts: qcom: sm8550: Fix xo clock supply of platform SD host controller
6b0177eccbfb arm64: dts: qcom: sm8750: Fix GIC_ITS range length
09324ac4c4a5 arm64: dts: qcom: sm8650: Fix GIC_ITS range length
42461104a849 arm64: dts: qcom: sm8550: Fix GIC_ITS range length
7fed3d4f95bb arm64: dts: qcom: sm8450: Fix GIC_ITS range length
a34110a2cc76 arm64: dts: qcom: milos: Fix GIC_ITS range length
cf791013fa56 arm64: dts: qcom: kaanapali: Fix GIC_ITS range length
9ba34d5c161c arm64: dts: qcom: sm8750-mtp: Enable DisplayPort over USB
0dfba1b8b110 arm64: dts: qcom: sm8750-mtp: Enable USB headset and Type-C accessory mode
6fb2b3c57a1d arm64: dts: qcom: sm8750-mtp: Enable display
94bbb2a520d5 arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC
0d13a955f067 arm64: dts: qcom: sm8750: correct Iris corners for the MXC rail
ca8211445244 arm64: dts: qcom: sm8650: correct Iris corners for the MXC rail
03a4a4c90515 arm64: dts: qcom: sm8550: correct Iris corners for the MXC rail
ffe4072bc4a5 arm64: dts: qcom: monaco: correct Iris corners for the MXC rail
ca0280fd2013 arm64: dts: qcom: lemans: correct Iris corners for the MXC rail
c5a782258445 arm64: dts: qcom: hamoa: correct Iris corners for the MXC rail
94a621686b8b arm64: dts: qcom: milos: add ADSP GPR
2c0e31f66641 arm64: dts: qcom: milos: Add fastrpc nodes
4348eba4e269 arm64: dts: qcom: eliza: Enable Eliza MTP board support
bd9a50a07b1e arm64: dts: qcom: Introduce Eliza Soc base dtsi
1e2758c665cf dt-bindings: arm: qcom: Document Eliza SoC and its MTP board
50c9f965c318 Merge branch 'icc-eliza' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into HEAD
9fa807fe99d8 Merge branch '[email protected]' into HEAD
558ffd114b15 arm64: dts: qcom: Add Mahua SoC and CRD
fa687efa5039 arm64: dts: qcom: Commonize Glymur CRD DTSI
3b33afe94906 dt-bindings: arm: qcom: Document Mahua SoC and board
715c7e8f89d2 arm64: dts: qcom: hamoa-iot-evk: Update TSENS thermal zone configuration
6c5bc6c181bd arm64: dts: qcom: qcs8300-ride: Enable Bluetooth support
7ab80981c51a arm64: dts: qcom: qcs8300-ride: enable WLAN on qcs8300-ride
aa9edba641c1 arm64: dts: qcom: hamoa-iot-evk: Add SDC2 node for hamoa iot evk board
cb2a3f4e7738 arm64: dts: qcom: msm8939-asus-z00t: add ambient light and proximity sensor
22d50a586442 arm64: dts: qcom: pm6125: Enable RTC by default
abc352def61a arm64: dts: qcom: sm6125-xiaomi-ginkgo: Enable debug UART
faf50112d77d arm64: dts: qcom: sm6125: Add debug UART node
2d1a9dce5f5d arm64: dts: qcom: sm6125: Add PRNG node
3815f0eb7a38 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Fix volume up button
4c704d68af59 arm64: dts: qcom: monaco-evk-camera: Add DT overlay
2b40778ab643 arm64: dts: qcom: monaco-evk: Add camera AVDD regulators
d69d792a25c1 arm64: dts: qcom: monaco: Add camera MCLK pinctrl
c779e8fbad9c arm64: dts: qcom: monaco: Add CCI definitions
34db7ceca95e arm64: dts: qcom: milos-fairphone-fp6: Add Hall Effect sensor
56c3171ca60d arm64: dts: qcom: qcs8300-ride: add anx7625 DSI to DP bridge node
404f31c1977e arm64: dts: qcom: qcs8300: add Display Serial Interface device nodes
04a3d67372c5 arm64: dts: qcom: milos: Sort pinctrl subnodes by pins
8db2da43dc32 arm64: dts: qcom: qrb2210-arduino-imola: describe DSI / DP bridge
fc33fdd6bc96 arm64: dts: qcom: arduino-imola: fix faulty spidev node
7c12503cf6da arm64: dts: qcom: sm8550: Add UART15
a26d78e6a3c5 arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Add Focaltech FT3518 touchscreen
934573c1d0b3 arm64: dts: qcom: x1-asus-zenbook-a14: add HDMI port
f618bdad25d0 arm64: dts: qcom: hamoa-iot-som: Add firmware-name to QUPv3 nodes
64e18b078547 arm64: dts: qcom: kodiak: Add I2S1 pinctrl definitions
6ac05b7086d3 media: dt-bindings: add NXP i.MX93 compatible string
37808b3f603e dt-bindings: media: i2c: document Omnivision OV08D10 CMOS image sensor
32572537e324 regulator: dt-bindings: mps,mp8859: convert to DT schema
af51cc5f2e42 dt-bindings: media: i2c: Add ov2732 image sensor
3a5993751558 dt-bindings: mmc: hisilicon,hi3660-dw-mshc: Convert to DT schema
4c1903537cb8 dt-bindings: mmc: sdhci-msm: add IPQ9650 compatible
0c17e693fe96 dt-bindings: mmc: amlogic: Add compatible for T7 mmc
97a9c79fb15a dt-bindings: display: panel-lvds: Add compatibles for Samsung LTN070NL01 and LTN101AL03 panels
3f3038d5cfc3 dt-bindings: display: panel: Add compatible for Holitech HTF065H045
c361ee9a3610 dt-bindings: vendor-prefixes: Add Holitech
ff5b1ff2e744 dt-bindings: display: panel: Add Samsung S6E8FC0-M1906F9
451dfa8152a4 dt-bindings: display: panel: Align style of "true" properties
a90c2dfad191 dt-bindings: display: simple: Add Tianma TM050RDH03 panel
abfb31807f9a dt-bindings: ili9806e: add Rocktech RK050HR345-CT106A display
73cc16a70015 dt-bindings: display: panel: Add Himax HX83121A
119b0155bc64 dt-bindings: display: simple: Add JuTouch JT070TM041 panel
db4281a330ce dt-bindings: display: bridge: lvds-codec: add doestek,dtc34lm85am
29c55f2cb8b3 dt-bindings: vendor-prefixes: Add Doestek
a5ab765e5a94 dt-bindings: iio: proximity: add ST VL53L1X ToF sensor
b3b5b861b60e riscv: dts: spacemit: Add ethernet device for K3
624774e6456f BackMerge tag 'v7.0-rc4' into drm-next
2be4608c6a9e arm64: dts: rockchip: configure hdmirx in Rock 5 ITX
9fc82742cd69 ARM: dts: qcom: drop apq8084 support
aeeeb442eacf dt-bindings: adc: ltc2497: add support for ltc2305
d85767f8b9fd arm64: dts: renesas: beacon-renesom: Remove LVDS Panel
aa343de0abb0 ARM: dts: r9a06g032: Add #address-cells to the GIC node
00536eacdf9c arm64: dts: renesas: r9a09g056: Remove wdt{0,2,3} nodes
dea1ee5819e4 arm64: dts: renesas: sparrow-hawk: Add overlay for Olimex MIPI-HDMI adapter
120e09971233 arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe
a966b4256d03 arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock
261105e5e18c arm64: dts: renesas: r9a09g047: Add PCIe node
cb6f92b92293 arm64: dts: renesas: Fix KSZ9131 PHY bogus txdv-skew-psec properties
bcc81deed1a9 arm64: dts: renesas: Drop KSZ9131 PHY C22 compatible strings
42581ce6404e arm64: dts: renesas: Drop RTL8211F PHY C22 compatible strings
20a5540c2117 arm64: dts: renesas: Drop RTL8211E PHY C22 compatible strings
fc441f4c3850 arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare Display 13.3"
821a145fd347 dt-bindings: i2c: dw: Remove unused bindings
a87837852e8c ASoC: dt-bindings: rockchip: Convert rockchip-max98090.txt to yaml
e6e1385f6646 dt-bindings: bus: document the stm32 debug bus
fccd0d13f2f6 dt-bindings: pinctrl: document access-controllers property for stm32 HDP
ea317aafb34e dt-bindings: document access-controllers property for coresight peripherals
aeada126234c arm64: dts: st: enable display support on stm32mp257f-dk board
e907f65101d8 arm64: dts: st: describe power supplies for stm32mp257f-dk board
2f88e77daa27 arm64: dts: st: enable display support on stm32mp235f-dk board
5495dc4d495b arm64: dts: st: describe power supplies for stm32mp235f-dk board
5c45e203dc49 arm64: dts: st: add clock-cells to syscfg node on stm32mp231
6465900501c6 arm64: dts: st: add lvds support on stm32mp235
9b59e3887c41 arm64: dts: st: add ltdc support on stm32mp235
17741ad7b73b arm64: dts: st: add ltdc support on stm32mp231
cd60b5d7c27a arm64: dts: st: omit unused pinctrl groups from stm32mp25 dtb files
4c4ac7eee0ed arm64: dts: st: add bootph-all in bsec node to stm32mp215f-dk
1b66037092f4 arm64: dts: st: add bsec support to stm32mp21
368f9195ccae ARM: dts: stm32: fix misalignments in nodes of stm32mp131
b46238f17aeb ARM: dts: stm32: fix misalignments in nodes of stm32mp151
ad9f08f894d3 arm64: dts: st: describe i2c2 / i2c8 on stm32mp235f-dk
4c734f2d3f54 arm64: dts: st: describe i2c2 / i2c8 on stm32mp257f-dk
d12a870724f5 arm64: dts: st: disable DMA usage for i2c on stm32mp257f-ev1
fe8155e787f2 arm64: dts: st: add i2c2 pinmux nodes in stm32mp25-pinctrl.dtsi
2ace1c2134ed arm64: dts: st: update i2c nodes interrupt/wakeup-source in stm32mp231
26c41741c84f arm64: dts: st: update i2c nodes interrupt/wakeup-source in stm32mp251
2373d61b4b50 ARM: dts: stm32: remove i2c dma properties in stm32mp157c-ev1
9ca448598e28 ARM: dts: stm32: update i2c nodes interrupt/wakeup-source in stm32mp131
adf5d381d77d ARM: dts: stm32: update i2c nodes interrupt/dma in stm32mp151
5ae51d1ee555 ARM: dts: stm32: Add DT overlays for DH STM32MP13xx/STM32MP15xx DHSOM
bcdc1c230f2c arm: dts: stm32: enable CoreSight on the stm32mp135f-dk board
f77d504d6885 arm: dts: stm32: enable CoreSight on the stm32mp157c-ev1 board
4752f4165586 arm: dts: stm32: enable CoreSight on stm32mp15xx-dkx boards
eff6050f631a arm: dts: stm32: enable the debug bus on stm32mp1x boards
99d8a1d5e384 arm: dts: stm32: introduce the debug bus for stm32mp1x platforms
59b717ad4b1e riscv: dts: thead: beaglev-ahead: enable HDMI output
781ddc6b5eaa dt-bindings: mtd: mxc-nand: add missing compatible string and ref to nand-controller-legacy.yaml
40a38e9bd0e6 dt-bindings: mtd: gpmi-nand: ref to nand-controller-legacy.yaml
716c4c1b1e1e dt-bindings: mtd: refactor NAND bindings and add nand-controller-legacy.yaml
0db7f377b385 dt-bindings: mfd: max77620: Document optional RTC address for MAX77663
22b637a46ab4 dt-bindings: mfd: max77620: Convert to DT schema
774297bd5e1d dt-bindings: mfd: bd72720: Add ROHM BD73900
2148f698c260 dt-bindings: mfd: Convert fsl-imx25-tsadc.txt to yaml format
58d35c8fb867 dt-bindings: mfd: spacemit,p1: Add individual regulator supply properties
14b45221e9fa ASoC: dt-bindings: mediatek: Adjust style of blocks placement
5f55baed85d8 ASoC: dt-bindings: mediatek,mt2701-wm8960: Correctly use additionalProperties
c3d94da89afe Merge branch 'ib-scmi-pinctrl-gpio' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl into gpio/for-next
eb3e12477943 dt-bindings: mmc: sdhci-of-aspeed: Add AST2700 compatible
0dfe65c18d43 dt-bindings: display: msm: Document DSI controller and DSI PHY on SC8280XP
663d7ba5e281 dt-bindings: display/msm: dsi-controller-main: Add SC8280XP
0850d0110f3a dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP
04037cb0a01a dt-bindings: display/msm: qcom,eliza-mdss: Add Eliza SoC
bb6c70cb426d dt-bindings: display/msm: qcom,sm8650-dpu: Add Eliza SoC
6036871859db dt-bindings: display/msm: dsi-controller-main: Add Eliza SoC
135527a48541 dt-bindings: display/msm: dsi-phy-7nm: Add Eliza SoC
4e26f9a55167 dt-bindings: display/msm: dp-controller: Add Eliza SoC
69ccdd12a7c2 dt-bindings: clock, reset: Add econet EN751221
0eea2fd7469b dt-bindings: input: matrix-keymap: fix key board wording
ad685f0f95c7 dt-bindings: clock: eswin: Documentation for eic7700 SoC
ea40ae37ce06 dt-bindings: input: touchscreen: edt-ft5x06: Add FocalTech FT3519
877552bac508 arm64: dts: rockchip: assign pipe clock to rk356x PCIe lanes
14ef0d57db64 arm64: dts: rockchip: Add mphy reset to ufshc node
781522be5f86 arm64: dts: rockchip: Enable OTP controller for RK3528
3e83c8c50967 arm64: dts: rockchip: Enable OTP controller for RK356x
81ca20834e73 arm64: dts: rockchip: Enable OTP controller for RK3562
65ef27e60e55 arm64: dts: rockchip: Enable PCIe CLKREQ# for RK3588 on Rock 5b-5bp-5t series
d3c0af75891c arm64: dts: rockchip: add SD/eMMC aliases for ArmSom Sige5
dd7888422e1d arm64: dts: rockchip: Add SPDIF nodes to RK3576 device tree
203069735354 arm64: dts: rockchip: Add Khadas Edge 2L board
e78dbdd4a848 dt-bindings: arm: rockchip: Add Khadas Edge 2L board
7145f038481b media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string
d68f1b93fe51 media: dt-bindings: nxp,imx8-isi: Add i.MX95 ISI compatible string
8c30b9099bd0 Merge tag 'v7.0-rc5' into next
88d5f2f3ea76 regulator: da91xx: Allow caching of buck registers when no GPIO input control is configured
92156b1bd157 regulator: dt-bindings: dlg,da9121: Add dlg,no-gpio-control
5d9102605bfa riscv: dts: microchip: add tsu clock to macb on mpfs
6a8dbed3a2a9 dt-bindings: riscv: Add Supm extension description
b9018968d7ca riscv: dts: microchip: add pic64gx and its curiosity kit
d5eb75349608 dt-bindings: riscv: microchip: document the PIC64GX curiosity kit
ae352b99764d dt-bindings: timer: sifive,clint: add pic64gx compatibility
4e4243bbe7e7 riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit
a80b8dbaaf03 ASoC: Merge up fixes
ca62121f50a5 arm64: dts: rockchip: Fix RK3562 EVB2 model name
9eef6edfab28 ARM: dts: rockchip: Add Onion Omega4 Evaluation Board
17233b8e90db dt-bindings: arm: rockchip: Add Omega4 Evaluation board
9c2adb087835 ARM: dts: rockchip: Add support for RV1103B
f6ccbb2aba1a dt-bindings: soc: rockchip: grf: Add RV1103B compatibles
fc08398935b5 Merge branch 'v7.1-shared/clkids' into v7.1-armsoc/dts32
4581b92803fb dt-bindings: display: arm,komeda: add Arm China Linlon D6 compatible
52188fe79ac2 dt-bindings: vendor-prefixes: Add Arm Technology (China) Co., Ltd.
675b21f78fa8 ARM: dts: rockchip: Pass linux,code to the power key on rk3288-veyron-pinky
e510c8433fc1 ASoc: uda1380: Improve error reporting
2adcd366c1d2 ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node
8fcf0dfb1e88 Merge branch 'ib-scmi-pinctrl-gpio' into devel
e7069aa44f79 gpio: dt-bindings: Add GPIO on top of generic pin control
f6f9c042f704 Merge branch 'for-v7.1/dt-bindings-clk' into next/clk
0c5eb2a0c180 dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock
9f6986ed9e57 media: dt-bindings: ovti,ov8856: Allow orientation & rotation props
298b00b70ed2 dt-bindings: media: st,stm32-dcmi: add 'power-domains' property
9f88581d4a5a arm64: dts: cix: add FCH(S0)/S5 GPIO controllers for sky1
b0c51d9ea1ab arm64: dts: cix: Add scmi powerdomain nodes for sky1
7126118f3d92 dt-bindings: PCI: cix,sky1-pcie-host: Add power-domains
67454701be41 arm64: dts: cix: add support for cix sky1 resets
7a4d0351aba4 riscv: dts: spacemit: drop incorrect pinctrl for combo PHY
969317133383 riscv: dts: spacemit: reorder phy nodes for K1
88c8992bf7a6 dt-bindings: firmware: qcom,scm: document Eliza SCM Firmware Interface
b6f79738cf6d Merge branch '20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com' into clk-for-7.1
40e234464fb0 dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets
1eba11ab743e clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC
2254e8f5e1a3 regulator: cros-ec: cleanup and add supplies
b4da86c1d687 regulator: dt-bindings: cros-ec: Add regulator supply
dee9f5071e9b spi: hisi-kunpeng cleanup and fix
e6aa9555e386 arm64: dts: rockchip: Correct Joystick Axes on Gameforce Ace
02a9ece9666c arm64: dts: rockchip: Correct Fan Supply for Gameforce Ace
e7b625390511 Revert "arm64: dts: rockchip: add SPDIF audio to Beelink A1"
d31c3a27ea11 arm64: dts: rockchip: Fix Bluetooth stability on LCKFB TaiShan Pi
63f6069d8fe3 ARM: dts: rockchip: Fix LED node names on rk3288-phycore-rdk
82071dc68130 ARM: dts: rockchip: Fix GMAC description n RK3288 boards
cdf95afa7230 ARM: dts: rockchip: Fix RTC description on rk3288-firefly-reload
7c94feff8bff ARM: dts: rockchip: Add missing the touchscreen interrupt on rk3288-phycore-rdk
000e7634919a ARM: dts: rockchip: Fix the trackpad supply on rk3288-veyron-jerry
b75bd3a88d9f ARM: dts: rockchip: Fix the Bluetooth node name on rk3288-veyron
5999e52555a0 ARM: dts: rockchip: Remove invalid regulator-property from rk3288-veyron
0a66ca11ef63 ARM: dts: rockchip: Use mount-matrix on rk3188-bqedison2qc
ffc89017f56b ARM: dts: rockchip: Fix RTC compatible on rk3288-phycore-rdk
a3ae9f904f87 ARM: dts: rockchip: Move PHY reset to ethernet-phy node on rk3036 boards
d1834c70fbe7 ARM: dts: rockchip: Remove rockchip,grf from rk3288 tsadc
e0018f3eb668 Merge tag 'drm-misc-next-2026-03-12' into drm-rust-next
0d5178fd6b69 Merge branch '20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com' into clk-for-7.1
9b8daaf74e87 dt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC
568067f26d10 dt-bindings: mmc: Add sdhci support for Canaan k230
6ac9f2bc1115 arm64: dts: marvell: armada-37xx: drop 'marvell,usb-misc-reg' from USB host nodes
28ad92fa94c5 dt-bindings: mmc: snps,dwcmshc-sdhci: add HPE GSC dwcmshc compatible
b4408fc39ff0 dt-bindings: mmc: rockchip-dw-mshc: Fix the RV1103B compatible
ad1752a91379 arm64: dts: ti: k3-j722s: Add main_i2c4 device node
80edeb3eb358 media: dt-bindings: rockchip,vdec: Add alternative reg-names order for RK35{76,88}
9c0b978ae870 media: dt-bindings: rockchip,vdec: Mark reg-names required for RK35{76,88}
5f405c791683 arm64: dts: arm/corstone1000: Add corstone-1000-a320
30af7037715b arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi
6248f7dc9835 arm64: dts: arm/corstone1000: Move cpu nodes
0617469a3897 dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"
021ce4aea186 dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"
21942dce0c13 dt-bindings: gpio: fix microchip,mpfs-gpio interrupt documentation
6ef9263af513 arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0
d582f9b4d825 arm64: dts: renesas: r9a09g047: Add RSPI nodes
f7090e59831b dt-bindings: pinctrl: realtek: Add RTD1625 pinctrl binding
67db43bd5e22 dt-bindings: pinctrl: realtek: Improve 'realtek,duty-cycle' description
c9efcc6553a5 dt-bindings: pincfg-node: Add input-threshold-voltage-microvolt property
93f9ab40e46b Merge 7.0-rc5 into tty-next
22230b86f816 dt-bindings: phy: mediatek, dsi-phy: Add support for mt8167
2eec7dddee83 dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
fd58e4588851 dt-bindings: iio: dac: maxim,ds4424: add maxim,rfs-ohms property
d233ec86ed81 dt-bindings: iio: dac: maxim,ds4424: add ds4402/ds4404
84171489750c Merge tag 'v7.0-rc4' into togreg
fd680ffae6fb arm64: dts: ti: k3-j721s2: Use ti,j7200-padconf compatible
10cf2d31376e arm64: dts: ti: k3-am68-phyboard-izar: Add PEB-AV-15 overlay
ebad5bb777d7 arm64: dts: ti: k3-j721s2-main: Add DSI1
fbb6ab0adb8f arm64: dts: ti: k3-am68-phyboard-izar: Add LVDS-Display
115254f601a9 arm64: dts: ti: k3-am68-phycore-som: Add DSI->LVDS bridge
c556f245b72a arm64: dts: ti: k3-am68-phyboard-izar: Assign dss clocks
a663cd878291 arm64: dts: ti: am62-verdin: Enable pullup for eMMC data pins
93b1284eee0e dt-bindings: iio: dac: ltc2632: add LTC2654 compatible strings
174f284dd046 dt-bindings: iio: light: vcnl4000: add regulators
35c54813167f dt-bindings: iio: accel: adi,adxl372: add ADXL371 compatible
a367d9c1c19c Merge tag 'v7.1-rockchip-dts64-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
1297c8eb1d8a dt-bindings: net: ethernet-phy: add property enet-phy-pair-polarity
d7f184dc6670 dt-bindings: net: ethernet-phy: add property enet-phy-pair-order
f2e3d9a0a7cf ARM: dts: BCM5301X: EA9200: specify partitions
26f637aa73f2 ARM: dts: BCM5301X: EA9200: add LEDs
45ed0960f605 ARM: dts: BCM5301X: EA9200: add USB GPIOs
80d8c2df309f ARM: dts: BCM5301X: EA9200: add WiFi button
98a78c20b46e ARM: dts: broadcom: bcm2835-rpi: Move non simple-bus nodes to root level
c8e0e3b1462f ARM: dts: bcm63148: Add I2C block
774eb26255b3 ARM: dts: bcm63138: Add I2C block
46ea42b19361 ARM: dts: bcm6878: Add I2C bus block
304ae8769b88 ARM: dts: bcm6855: Add I2C bus blocks
5415f410d1e0 ARM: dts: bcm6846: Add I2C bus block
b4f6373f95a8 ARM: dts: bcm63138: Fix DMA IRQ
f846d6fc51aa ARM: dts: bcm6878: Fix PL081 DMA block IRQ
106af955dd0a ARM: dts: BCM5301X: AC5300: set WAN MAC from nvram
8acd4940c609 ARM: dts: BCM5301X: AC3100: set WAN MAC from nvram
8dbb69997a22 ARM: dts: BCM5301X: panamera: set WAN MAC from nvram
e87fdf38279a ARM: dts: BCM5301X: EA9200: set WAN MAC from nvram
1b24a8fc9341 dt-bindings: i2c: renesas,riic: Document the R9A08G046 support
bec902118b29 dt-bindings: i2c: qcom-cci: Document sm6150 compatible
29353b00fd10 dt-bindings: i2c: qcom-cci: Document Milos compatible
e80036829d88 riscv: dts: thead: th1520: add coefficients to the PVT node
830c656194f2 arm64: dts: broadcom: bcm2712: Move non simple-bus nodes to root level
5921dc0bec8c arm64: dts: renesas: rzt2h-rzn2h-evk: Fix GMAC pins sort order
46f5a3d8fdb2 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add PHY interrupt support
7a11acf5b848 arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add PHY interrupt support
1284dbb2913f arm64: dts: renesas: r9a09g057h48-kakip: Add pixpaper display overlay
7eebc3897e09 arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Clarify SD0 power jumper setup
d74f70444ff3 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Clarify SD0 power jumpers
668f89029dad arm64: dts: microchip: add EV23X71A board
d094bee12713 dt-bindings: arm: AT91: document EV23X71A board
82e582c35cc0 arm64: dts: microchip: add LAN969x support
609bd72df8a8 arm64: dts: microchip: add LAN969x clock header file
b8ed2e472b23 dt-bindings: extcon: ptn5150: Allow "connector" node to present
0ec6e737d57e dt-bindings: PCI: eswin: Add ESWIN PCIe Root Complex
6bc10ee6aef4 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b71cf4bb3963 dt-bindings: arm-smmu: Add compatible for Eliza SoC
4c6439178817 dt-bindings: clock: vf610: Add definitions for MTIP L2 switch
876d858ab193 dt-bindings: clock: vf610: Drop VF610_CLK_END define
920318548a29 dt-bindings: leds: lp5860: add enable-gpio
1f1aaf101b17 dt-bindings: touchscreen: trivial-touch: Move allOf: after required:
9074b52df9d6 dt-bindings: input: touchscreen: Convert TS-4800 to DT schema
482faab19499 dt-bindings: remoteproc: qcom,sm8550-pas: Add Glymur CDSP
4f1c7a29bbc1 dt-bindings: remoteproc: qcom,sm8550-pas: Add Glymur ADSP
e44bd3a4f6c8 dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs
5834055b8aaf dt-bindings: firmware: qcom,scm: Document ipq5210 SCM
818b9c72c43a Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into clk-for-7.1
e4ea91c1a5b4 dt-bindings: clock: add Qualcomm IPQ5210 GCC
26949b4f0faf dt-bindings: net: micrel: KSZ8041RNLI supports LED mode
ee158dea459d dt-bindings: net: micrel: Sort lists
a2a531664717 dt-bindings: power: Add Support for Allwinner A733 PCK600 Power Domain Controller
60356bb03307 spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
28b27d2768e8 spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property
dae52c367d95 dt-bindings: connector: Add SPR AVS Sink APDO definitions
1441274fb18e dt-bindings: usb: Add Corechips SL6341 USB2.0/3.0 hub controller
4db58427f856 dt-bindings: vendor-prefixes: Add Shenzhen Corechips Microelectronics
e75cc519bc76 ASoC: dt-bindings: adi,ssm2305: Convert to DT schema
5dc026f042cc arm64: dts: qcom: x1e80100: Add '#cooling-cells' for CPU nodes
575cdf38cf4e arm64: dts: qcom: x1-crd: add USB DisplayPort audio
fc07c0b7fec5 arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT
4a0087fb0962 arm64: dts: qcom: kodiak: Add missing usb-role-switch property
dbdd1ca5eafb dt-bindings: arm: qcom: Add Thundercomm AI Mini PC G1 IoT
31f8e1e01b45 arm64: dts: qcom: sm8550: Add ACD levels for GPU
1222df324893 arm64: dts: qcom: pmk8550: Add PWM controller
4def553c3707 arm64: dts: qcom: remove msm8996-v3.0.dtsi
0b3353dcebae arm64: dts: qcom: ipq9574: Enable eMMC variant
d878ede8ab42 dt-bindings: arm: qcom: Add IPQ9574 AL02-c2 and AL02-c7 eMMC variant
2e794d5431f3 arm64: dts: qcom: ipq9574-rdp433: Reorganize DTS to introduce eMMC support
b08dbf6fa5a4 arm64: dts: qcom: ipq9574: Add details for eMMC
4ad67f51b1ae arm64: dts: qcom: qcs8300: Add clocks for QoS configuration
adab14cb6a73 arm64: dts: qcom: msm8953-xiaomi-daisy: fix backlight
48599788dd4e arm64: dts: qcom: msm8937-xiaomi-land: correct wled ovp value
10496a851c7e arm64: dts: qcom: msm8953-xiaomi-vince: correct wled ovp value
581be0fe486a arm64: dts: qcom: sm8550: Update EAS properties
8ef637ba1db5 arm64: dts: qcom: hamoa: Add remoteproc IOMMUS in EL2 device trees
0ef68efaba77 dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson"
b0d31c82dca1 dt-bindings: net: Add support for Spacemit K3 dwmac
59dad3797d4d regulator: fp9931: Make vin-supply mandatory
d7200554c0bb regulator: dt-bindings: fp9931: Make vin-supply property as required
0c6fee1327e0 dt-bindings: net: cdns,macb: add a compatible for Microchip pic64hpsc
f9ae3e69ab05 dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller
adb2916acc4a Merge branch 'icc-qcs615' into icc-next
8c290b947d21 dt-bindings: dma: xlnx,axi-dma: Convert to DT schema
e30abb66f2e7 dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L
226288859390 dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS
216745d416f2 Merge tag 'renesas-dts-for-v7.1-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
c0f22f3f3510 dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts
247d8de6a257 arm64: dts: broadcom: bcm2712-d-rpi-5-b: update uart10 interrupt
5f48e85bf9d7 arm64: dts: broadcom: bcm2712-d-rpi-5-b: add fixes for pinctrl/pinctrl_aon
5fccbae8fbfe arm64: dts: broadcom: bcm2712-rpi-5-b: add pinctrl properties for csi i2cs
f7c7a5c60f26 arm64: dts: broadcom: bcm2712: add camera backend node pispbe
436e0be5b486 arm64: dts: broadcom: rp1: add csi nodes
9ea23c7a5ae9 arm64: dts: broadcom: rp1: add i2c controller
c563f4c152cd ARM: dts: BCM5301X: add root pcie bridges
aabeb8b81a5e ARM: dts: BCM5301X: Drop extra NAND controller compatible
cb853ce04b7a ARM: dts: BCM5301X: Describe PCIe controllers fully
a17b6a12bb45 arm64: dts: broadcom: bcm2712: Add V3D device node
4528273c29ca spi: controller registration fixes
bbd1b87a7f68 dt-bindings: mmc: sdhci-msm: add IPQ5210 compatible
26f80dd2c6a9 dt-bindings: media: i2c: alliedvision,alvium-csi2
f62b10e7d768 Merge 7.0-rc4 into usb-next
6f9a6c389f9f dt-bindings: pinctrl: qcom,sm8650-lpass-lpi-pinctrl: Add Glymur pinctrl
d537e09ae260 arm64: dts: qcom: glymur: Fix deprecated cpu compatibles
aa1909bc78b9 dt-bindings: arm: cpus: Extend Qualcomm Oryon compatibles
ec93399a945f dt-bindings: arm: qcom,ids: add SOC IDs for IPQ5210 family
f638fa022604 scsi: ufs: rockchip,rk3576-ufshc: dt-bindings: Add new mphy reset item
ab5c342be679 scsi: ufs: qcom: dt-bindings: Document the Eliza UFS controller
07e04ca91e25 dt-bindings: arm: qcom,ids: Add SoC IDs for SM7450 and SM7450P
df4a6c2428d6 dt-bindings: cache: qcom,llcc: Add SDM670 compatible
e108683f0d99 ASoC: basic support for configuring bus keepers
9bb5b1b7e937 ASoC: dt-bindings: add TDM slot idle mode properties
01adfb612268 ASoC: dt-bindings: update tdm-slot.txt references to tdm-slot.yaml
cd2a5762d818 ASoC: dt-bindings: convert tdm-slot to YAML
3a2af1ced9c1 ASoC: amd: Move to GPIO descriptors
624ae583e063 dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
c76252b9b9bd dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties
c2e8a1c34055 dt-bindings: crypto: inside-secure,safexcel: add compatible for MT7981
927a4d0cca5c riscv: dts: thead: lichee-pi-4a: enable HDMI
514eedc6b2d3 riscv: dts: thead: add DPU and HDMI device tree nodes
67fe66fb8180 dt-bindings: thermal: qcom-tsens: Document the SM8750 Temperature Sensor
b9e7b4d6e782 arm64: dts: allwinner: h6: Add TaiqiCat (TQC) A01 support
838f0d263738 dt-bindings: arm: sunxi: Add TaiqiCat (TQC) A01
53b63d9224bb dt-bindings: vendor-prefixes: Add Beijing Ultrapower Software Co., Ltd.
0acbf7efb78d dt-bindings: rng: atmel,at91-trng: add microchip,lan9691-trng
66a61ec0edae dt-bindings: bridge: lt8713sx: Add bindings
9c54806f18f3 arm64: dts: rockchip: enable vicap dvp on wolfvision pf5 io expander
e7a04b79cba0 arm64: dts: imx8mp-hummingboard-pulse: fix mini-hdmi dsi port reference
536e73c6a021 arm64: dts: imx8mp-hummingboard-pulse/cubox-m: fix vmmc gpio polarity
c9bf7916458d arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe
c9d367a88f5d arm64: dts: freescale: add pixpaper display overlay for i.MX93 FRDM
5b355e86d7be arm64: dts: tqma8mpql-mba8mp-ras314: Configure multiple queues on eqos
b8b97a45ce1e arm64: dts: tqma8mpql-mba8mpxl: Configure multiple queues on eqos
3efd45a11e21 arm64: dts: imx8mp-kontron: Use GPIO/IRQ defines in DL devicetree
66e6507d1565 arm64: dts: imx8mp-kontron: Drop vmmc-supply to fix SD card on SMARC eval carrier
e7cec130064a arm64: dts: imx8mp-kontron: Fix touch reset configuration on DL devices
39b6501d91c0 dt-bindings: arm64: add Marvell 7k COMe boards
1a8ddeb710bb dt-bindings: input: touchscreen: convert fsl-mx25-tcq.txt to yaml
f35d40ac31eb riscv: dts: spacemit: k3: add full resource to UART
545556e0ff10 riscv: dts: spacemit: k3: add GPIO support
6efb5a75b7ff riscv: dts: spacemit: k3: add pinctrl support
229f94412295 riscv: dts: spacemit: k3: add clock tree
f1366c61df7b dt-bindings: serial: 8250: spacemit: fix clock property for K3 SoC
1987cc6e0bb2 dt-bindings: rtc: isl12026: convert to YAML schema
da7272fe9e42 ARM: dts: renesas: armadillo800eva: Add wakeup-source to st1232
f01e19a0d3e5 ARM: dts: renesas: armadillo800eva: Enable SDHI1
990a7d82022b dt-bindings: pwm: amlogic: Document A4 A5 and T7 PWM
3b76581aa860 dt-bindings: rtc: microcrystal,rv3028: Allow to specify vdd-supply
cbddba5d80e8 arm64: dts: ti: k3-am62a7-sk: Fix pin name in comment from M19 to N22
4e2030a70d92 ARM: dts: omap: dm816x: Correct pinctrl register
f1a4d7f98ac6 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
9afb9ccc5e77 arm64: dts: rockchip: Add analog audio switches to RK3576 EVB1
8fad61a1a682 Merge tag 'v7.0-rc3' into next
d6cfdf40061d arm64: dts: zena: Move SRAM into SoC and memory node out of SoC
c272e42491b7 dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range
58c95ed4b396 dt-bindings: rtc: mpfs-rtc: permit resets
e0df1b9dab96 dt-bindings: serial: amlogic,meson-uart: Add compatible string for A9
f56f24da5e2b dt-bindings: serial: atmel,at91-usart: add microchip,lan9691-usart
dad5ba234e7d dt-bindings: serial: snps-dw-apb-uart: Add RV1103B compatible
b3d7e7f46832 arm64: dts: mediatek: mt7986a: Fix gpio-ranges pin count
663b05ddf056 arm64: dts: mediatek: mt7981b: Fix gpio-ranges pin count
711c15d32875 arm64: dts: mediatek: mt6795: Fix gpio-ranges pin count
23d6a3b41875 dt-bindings: net: qcom,ipa: document qcm2290 compatible
a9b1d3987f95 ARM: dts: renesas: r9a06g032-rzn1d400-db: Use interrupts for Micrel PHYs
cbcc9c67dbdc ARM: dts: renesas: r9a06g032-rzn1d400-db: Do not use underscores in node names
a2c36dbe7e51 ARM: dts: renesas: r9a06g032-rzn1d400-db: Add QSPI node including NOR flash
60be0d46401f arm64: dts: renesas: r9a09g057: Add DMA support for RSPI channels
46fc0efb8af9 arm64: dts: renesas: r9a09g056: Add DMA support for RSPI channels
de59102148a4 ARM: dts: renesas: r9a06g032: Describe the QSPI controller
c89adce2e7fc Merge drm/drm-next into drm-misc-next
0199905afc5a dt-bindings: bus: Remove unused bindings
6f40e2c22d88 arm64: dts: qcom: sm6125: Add missing MDSS core reset
1648955595c9 arm64: dts: qcom: sm6115: Add missing MDSS core reset
65a1e2ad58ce Merge branch '[email protected]' into arm64-for-7.1
4a9defa3b2ea Merge branch '[email protected]' into clk-for-7.1
72d02b89da27 dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets
b011d655ae77 dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets
41028a996349 Merge branch '[email protected]' into clk-for-7.1
b9a175978d84 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Eliza
6a58b6fa97a6 dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller
2f8403264607 dt-bindings: clock: qcom: document the Eliza Global Clock Controller
56b5ebb32305 ASoC: dt-bindings: ti,tas2770: Switch to undeprecated reset-gpios
1a8b5145d244 dt-bindings: usb: maxim,max3421: convert to DT schema
bb69e1ee7ef1 dt-bindings: connector: Add sink properties to comply with PD 3.1 spec
0b979c7f649f dt-bindings: usb: document the Etek ET7304 USB Type-C Port Controller
644e5b39076a dt-bindings: usb: qcom,dwc3: Allow high-speed interrupt on Glymur, Hamoa and Milos
1a2ce1869874 dt-bindings: usb: mpfs-musb: permit resets
88c557481398 dt-bindings: usb: cdns,usb3: support USB devices in DT
3f148a01d211 dt-bindings: pinctrl: pincfg-node: permit bias-high-impedance with other bias properties
c976a6d4b477 Merge v7.0-rc3 into drm-next
31bca2c52db8 dt-bindings: power: supply: document Samsung S2MU005 battery fuel gauge
532b7b0831e3 dt-bindings: interrupt-controller: apple,aic2: Add AICv3
0628aa98fc58 dt-bindings: media: i2c: Add Sony IMX355
197e9e594acc dt-bindings: media: qcom,sdm670-camss: Remove clock-lanes requirement
440da927d153 dt-bindings: media: st: dcmi: add DMA-MDMA chaining properties
5dd807ebb927 dt-bindings: media: mt9m114: document MI1040 sensor
c1b63a901c55 media: dt-bindings: ti,ds90ub960: Add support for DS90UB954-Q1
ca1acbf997eb media: dt-bindings: ti,ds90ub960: Refactor port definitions
f504ae9a4799 media: dt-bindings: Drop starfive,jh7110-camss from staging
3ba6fd89e212 dt-bindings: input: touchscreen: sitronix,st1232: Add wakeup-source
6292fdbb73da arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
33e5a62e36f9 arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
0ca5238df2af arm64: dts: exynos8895: Move I2C address/size-cells to DTSI
15ad87221dd2 arm64: dts: exynos7870: Move I2C address/size-cells to DTSI
6b9daa56dc35 ARM: dts: exyons4412: Drop duplicated I2C address/size-cells
a78509c86479 ARM: dts: exynos4210-smdkv310: Drop duplicated I2C address/size-cells
77e966a10563 ARM: dts: exynos3250: Drop duplicated I2C address/size-cells
0917cbf338f5 dt-bindings: display: panel: Align style of additionalProperties
7a12cc387af6 dt-bindings: display: panel: Drop redundant properties
81f70a958d03 dt-bindings: display: innolux,p097pfg: Document ports
31768b64363f dt-bindings: display: samsung,s6d7aa0: Document port
aed330c2adcc dt-bindings: display: panel: document Atrix 4G and Droid X2 DSI panel
a60dfcff2e3a dt-bindings: panel-simple-dsi: add nt37700f compatible
0c6983a00dda dt-bindings: arm: qcom: document google,bonito-tianma board
89b7580b345d dt-bindings: display: panel: Document the rotation property
8521ddf2a5d9 dt-bindings: display: panel: Add compatible for TAIGUAN XTI05101-01A
069c92c4b695 dt-bindings: vendor: add taiguanck
986408e730ea dt-bindings: display: panel: add LXD M9189A
617c21bf4072 dt-bindings: vendor-prefixes: Add lxd
94a2c3b94505 dt-bindings: display: simple: Add Powertip PH800480T032-ZHC19 panel
a73682b64332 dt-bindings: display: simple: add EDT ET057023UDBA panel
83d1706da5db arm64: dts: allwinner: sun55i-t527: avaota-a1: Enable LEDs
c8c227132381 arm64: dts: allwinner: sun55i-a523: Add LED controller
22b8ebf9d836 dt-bindings: leds: sun50i-a100: Add compatible for Allwinner A523 SoC
83c08ee3d713 ASoC: ti: davinci-mcasp: McASP code cleanup and clk
523cdadce7e4 dt-bindings: pinctrl: qcom: Add Milos LPASS LPI pinctrl
f2b3f85b6df9 dt-bindings: thermal: lmh: Add SDM670 compatible
c16a1455a46e dt-bindings: thermal: tsens: add SDM670 compatible
7949d872084a arm64: dts: ti: k3-am62l-main: Add RNG node
035a8558259e dt-bindings: arm: ti: Drop Kontron SMARC-sAM67 module
2781cc29d56d dt-bindings: mfd: sl28cpld: Drop sa67mcu compatible
a777f148b9af arm64: dts: ti: remove the Kontron SMARC-sAM67
2428165a77bc arm64: dts: ti: k3-j721s2-common-proc-board: Add QSPI flash partition details
5eef22c36875 arm64: dts: ti: k3-j721e-common-proc-board: add ti,min-output-impedance
a36c3d839af6 arm64: dts: ti: k3-j7200-common-proc-board: add ti,min-output-impedance
a75df18329d3 arm64: dts: ti: k3-am654-base-board: add ti,min-output-impedance
b97a6a72e156 arm64: dts: ti: k3-am642-{evm,sk}: add ti,min-output-impedance
5d87903ee008 arm64: boot: dts: ti: k3-am62l3-evm: enable wkup_uart0_target node
0f709ac341ca arm64: boot: dts: ti: k3-am62l3-evm: define wkup_uart0 pins
ae1495930f63 arm64: boot: dts: ti: k3-am62l-wakeup: create label for wkup_uart0 target-module
38551da2279d arm64: dts: ti: k3-am62l: include WKUP_UART0 in wakeup peripheral window
f320851c16bb arm64: dts: ti: k3-am62d2-evm: Set wakeup-source system-states
82de76c2b753 arm64: dts: ti: k3-am62-phycore-som: Add 128MiB of global CMA
d5744d44ec86 riscv: dts: spacemit: Add 'linux,pci-domain' to PCIe nodes for K1
a0b1c8ec845c dt-bindings: leds: sc2731: Add compatible for SC2730
6a1f7c5af0ed dt-bindings: gpio: realtek-otto: add rtl9607 compatible
d4fcbce3068d arm64: dts: rockchip: Enable GPU on rk3566-pinenote
a287659a2afb dt-bindings: clk: tenstorrent: Add tenstorrent,atlantis-prcm-rcpu
200a6b7444a9 arm64: dts: qcom: correct RBR opp entry
3bbb857a263c arm64: dts: qcom: monaco-evk: Enable the secondary USB controller
59ee6a33f810 arm64: dts: qcom: monaco: Add role-switch support and HS endpoint for secondary USB controller
fb816c5248e1 arm64: dts: qcom: monaco-evk: Enable GPIO expander interrupt for Monaco EVK
9de38c419058 arm64: dts: qcom: sdm845: Introduce camera master clock pinctrl
4025a0a1c836 arm64: dts: qcom: qcm6490-idp: add and enable BT node
cab4bb2d01f7 arm64: dts: qcom: monaco-evk: Enable SDHC1 for eMMC
909a7893d2e6 arm64: dts: qcom: monaco: Complete SDHC definition
2988884051e1 arm64: dts: qcom: talos: add ETR device
8eb5246677b1 arm: dts: ti: omap: align node patterns with established convention
fa56f7b57a5a dt-bindings: arm: fsl: add bindings for TQMa8x
1a9222336241 dt-bindings: fsl: imx7ulp-smc1: Add #clock-cells property
48e42cc00de2 dt-bindings: mmc: fsl-imx-esdhc: add S32N79 support
d51e28f19bdd dt-bindings: mmc: loongson,ls2k0500-mmc: Add compatible for Loongson-2K0300
a8a9901610b9 mmc: Merge the immutable mux branch into next
cd652bd76f5c dt-bindings: mmc: renesas,sdhi: Add mux-states property
f6f2a1483211 dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H}
debfedfd5950 dt-bindings: soc: cix: document the syscon on Sky1 SoC
263d86dbebbe ASoC: dt-bindings: cirrus,cs42l43: Add CS42L43B variant
ced1f5f3870e dt-bindings: gpio: gpio-delay: Use Alexander's email
e025c996549d arm64: dts: ti: k3-am69-aquila-clover: Fix DP regulator enable GPIO
aa24d63b1fb0 arm64: dts: ti: k3-am69-aquila-dev: Fix DP regulator enable GPIO
c671c7afe7e1 arm64: dts: ti: k3-am62l: support cpufreq scaling
70d45d88c356 arm: dts: microchip: remove unused #address-cells/#size-cells from sam9x60 udc node
4a9c8d0d944e dt-bindings: firmware: arm,scmi: Document arm,no-completion-irq property
b25cad3e386d arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gauge
d643400cd569 dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema
a02370b02b99 dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
77fdb37b2b05 dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema
abe9ad520fa1 dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema
a72c88c0d84e dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema
4ee3792205ec dt-bindings: crypto: qcom,inline-crypto-engine: Document the Eliza ICE
f984bdd21bc0 Merge branch 'icc-qcs8300' into icc-next
262e58cb33b5 dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
9eb133e81a93 dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK
bcd804b042a3 Merge branch 'icc-mahua' into icc-next
1601e1315182 Merge branch 'icc-eliza' into icc-next
3103d68f1dcf dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Eliza SoC
9fa2d8de4547 dt-bindings: interconnect: OSM L3: Add Eliza EPSS L3 compatible
7d3ec6edf05f dt-bindings: interconnect: qcom,glymur-rpmh: De-acronymize SoC name
c32e86a83f0c dt-bindings: interconnect: OSM L3: Document sm8550 OSM L3 compatible
73d2683e277c arm64: dts: renesas: r9a09g087: Wire up DMA support for SPI
f1160fd99b3f arm64: dts: renesas: r9a09g077: Wire up DMA support for SPI
86d0bcd31331 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable RTC
ae8e361cbb93 arm64: dts: renesas: r9a09g056: Add RTC node
6f2ceae6a5ae arm64: dts: renesas: ebisu: Describe PCIe/USB3.0 clock generator
4de7cebe1fec arm64: dts: renesas: ulcb: ulcb-kf: Describe PCIe/USB3.0 clock generator
93dab8266fc2 arm64: dts: renesas: salvator-common: Describe PCIe/USB3.0 clock generator
097202a5066c arm64: dts: renesas: r8a77990: Add USB 3.0 PHY and USB3S0 clock nodes
af4aaef59611 arm64: dts: renesas: r8a77990: Describe PCIe root port
acf598fa7b92 arm64: dts: renesas: r8a77965: Describe PCIe root ports
bc410f3f2935 arm64: dts: renesas: r8a77961: Describe PCIe root ports
32f09955014a arm64: dts: renesas: r8a77960: Describe PCIe root ports
6a4c880de25a arm64: dts: renesas: r8a77951: Describe PCIe root ports
2345a5df1bdb ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling
d72fc2d9b48e arm64: dts: renesas: sparrow-hawk: Mark OTP and HSCIF0 pins as bootph-all
087fa6d0bd19 dt-bindings: interconnect: qcom,qcs8300-rpmh: add clocks property to enable QoS
db1f2b17de01 dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in Mahua SoC
fe9683a1c084 ARM: dts: stm32: enable DCMI DMA-MDMA chaining on stm32mp157c-ev1.dts
02eb59f7a636 ARM: dts: stm32: add sram node within stm32mp151.dtsi
55a557775d89 ARM: dts: stm32: phyboard-sargas and phycore: Add optional interfaces
904da3355425 ARM: dts: stm32: phyboard-sargas and phycore: Fix coding style issues
7fb45f2555cd ARM: dts: stm32: phycore-stm32mp15: Disable optional SoM peripherals
1bfef84746e8 ARM: dts: stm32: phyboard-sargas: Move aliases from dts to dtsi
c775b71b91e6 ARM: dts: stm32: phycore-stm32mp15: Add dummy memory-node
643114f5d358 ARM: dts: stm32: phycore-stm32mp15: qspi: Fix memory map and pinctrl
acb25d2e6283 ARM: dts: stm32: phyboard-sargas: Fix uart4 and sai2 pinctrl
d486f5a22b00 ARM: dts: stm32: Add new pinmux groups for phyboard-sargas and phycore
f950501a3d3c dt-bindings: arm: stm32: Modify STM32MP15x Phytec board items types
71f06eb92bdc ARM: dts: stm32: phyboard-sargas: Introduce SoM device tree
1d6289f0d68f ARM: dts: stm32: phycore-stm32mp15: Rename device tree files
f2b69375b638 dt-bindings: arm: mediatek: audsys: fix formatting issues
5f6fa55c0a0a ARM: dts: ti: omap: samsung-espresso10: Add initial support for Galaxy Tab 2 10.1
fcae71d4d519 ARM: dts: ti: omap: samsung-espresso7: Add initial support for Galaxy Tab 2 7.0
7a0d635481e2 dt-bindings: omap: Add Samsung Galaxy Tab 2 7.0 and 10.1
1877419acc9f ARM: dts: ti: omap: espresso-common: Add common device tree for Samsung Galaxy Tab 2 series
67511c6aa63a dt-bindings: display: panel-lvds: Add compatibles for Samsung LTN070NL01 and LTN101AL03 panels
ae3c6dce17fc dt-bindings: display: bridge: lvds-codec: add doestek,dtc34lm85am
33e3b55125ba dt-bindings: vendor-prefixes: Add Doestek
76b1f6c854e8 ARM: dts: twl6032: Add DTS file for TWL6032 PMIC
805ad5d12f8d dt-bindings: qcom,pdc: document the Eliza Power Domain Controller
bbddf7c8649e Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
086f62f32cba dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali CDSP
5538340cb886 dt-bindings: remoteproc: qcom,sm8550-pas: Add Kaanapali ADSP
4239f30af60a arm64: dts: mediatek: mt8195-cherry-dojo: Describe M.2 M-key NVMe slot
ce0e7ed46f2b arm64: dts: mediatek: mt8195-cherry: add WiFi PCIe and BT USB power supplies
1000ff378f34 arm64: dts: exynos: add initial support for Samsung Galaxy J5
e00e4c53c77b dt-bindings: arm: samsung: add compatible for samsung-j5y17lte
72d1b1e35832 dt-bindings: PCI: Add Andes QiLai PCIe support
12a9a4d1c858 dt-bindings: mux: Remove nodename pattern constraints
824c35870618 dt-bindings: net: dsa: maxlinear,mxl862xx: remove port label
705668fb1f83 arm64: dts: qcom: monaco: Add EL2 overlay
d2d791bd83e2 arm64: dts: qcom: lemans: disable zap-shader for EL2 configuration
a9959a159a87 arm64: dts: qcom: talos: Add missing clock-names to GCC
96b0c5ac472c arm64: dts: qcom: ipq9574: remove MP5496 regulator references from SoC dtsi
f80f030c8003 arm64: dts: qcom: kodiak: Fix PCIe1 PHY ref clock voting
288fb32a678f arm64: dts: qcom: Add support for ECS LIVA QC710
dba4d24e90ff dt-bindings: arm: qcom: Add ECS LIVA QC710
0aaa873b5207 arm64: dts: qcom: sdm630: add SPI7 interface
d56fbd064377 dt-bindings: arm: qcom,ids: Add SoC ID for CQ7790
6f34068cca43 arm64: dts: qcom: Add base PURWA-IOT-EVK board
6f8c624bf39e arm64: dts: qcom: Add PURWA-IOT-SOM platform
edc416557f9f dt-bindings: arm: qcom: Document PURWA-IOT-EVK board
a9f5e1cb1fd8 arm64: dts: qcom: qcs6490-rubikpi3: Use lt9611 DSI Port B
86e1b8569a9b arm64: dts: qcom: talos: Mark usb controllers are wakeup capable devices
37a426e144bb arm64: dts: qcom: talos: Flatten usb controller nodes
46f85155ddb1 arm64: dts: qcom: Add Redmi Note 8T
87f781f4e200 dt-bindings: arm: qcom: Add Xiaomi Redmi Note 8T
b04e43ac1194 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Fix reserved gpio ranges
2ca705cd93aa arm64: dts: qcom: sm6125-xiaomi-ginkgo: Remove extcon
5cc825e02a73 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Set memory-region for framebuffer
260e9ee68d5f arm64: dts: qcom: sm6125-xiaomi-ginkgo: Correct reserved memory ranges
30a352009e00 arm64: dts: qcom: sm6125-xiaomi-ginkgo: Remove board-id
7aea352ab46c ARM: dts: qcom: Drop unused .dtsi
5592784066aa dt-bindings: mmc: dwcmshc-sdhci: Fix resets array validation
04c92aeefeee dt-bindings: power: qcom,rpmpd: document the Eliza RPMh Power Domains
02a4424aa735 dt-bindings: gpio: mpfs-gpio: permit resets
b9e5ade6cd92 dt-bindings: net: qcom,ipa: Add sram property for describing IMEM slice
7901a1cb696a dt-bindings: sram: qcom,imem: Allow modem-tables subnode
6fd4e3501a97 dt-bindings: power: supply: cpcap-battery: document monitored-battery property
ef33037a7c3d dt-bindings: power: supply: max17042: drop formatting specifier |
86ac273f867a dt-bindings: power: supply: max17042: support shunt-resistor-micro-ohms
eac5d61f8d31 dt-bindings: power: supply: max17042: add support for max77759
32a803d3f97d dt-bindings: iio: adc: cpcap-adc: document Mot ADC
01087b4b7cba spi: dt-bindings: mpfs-spi: remove clock-names
50aefe7563cb spi: dt-bindings: mpfs-spi: permit resets
367cd0e82ba7 dt-bindings: soc: microchip: mpfs-sys-controller: Add pic64gx compatibility
c1d6b3a0e470 dt-bindings: soc: microchip: add compatible for the mss-top-sysreg on pic64gx
d15547bd9539 dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane support
809678b3e3ed dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad
6f5bb4a79246 dt-bindings: arm: nvidia: Document the Tegra238 CCPLEX cluster
da7ca9a2c751 dt-bindings: cpufreq: qcom-hw: document Eliza cpufreq hardware
8137942f3df9 spi: Merge up v7.0-rc2
720959a10fd2 regulator: pf9453: Fix IRQ trigger and allow
989eed7f316a arm64: dts: imx93-phyboard-segin: Add peb-av-02 overlay
423e9ec6088d arm64: dts: freescale: Add the GOcontroll Moduline Mini
b29949020273 arm64: dts: freescale: Add the GOcontroll Moduline IV
c72e5d50c794 arm64: dts: freescale: add Ka-Ro Electronics tx8m-1610 COM
e61d94426a9a arm64: dts: imx8mm: Add pinctrl config definitions
44aa267d53b4 arm64: dts: freescale: add NXP FRDM-IMX91S board support
f2808445f025 arm64: dts: imx91-11x11-evk: Add usdhc3 for SDIO WiFi support
42b669ce8d1f arm64: dts: imx8mp-evk: Add usdhc1 for SDIO WiFi support
b6b040180c9a dt-bindings: arm: fsl: Add GOcontroll Moduline IV/Mini
38760584eb9a dt-bindings: arm: fsl: Add FRDM-IMX91S board
154c3087c6c8 dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
b7885dc5dc2e arm64: dts: imx8mp-evk: Enable pull select bit for PCIe regulator GPIO (M.2 W_DISABLE1)
7a9e92eb39c0 arm64: dts: imx943-evk: add usdhc3 for SDIO WiFi support
4dc85883e5b9 arm64: dts: imx952-evk: add MT35XU01G spi nor flash
aed1ca4ec11a arm64: dts: imx952: Add xspi node
3eb8c8dd56f8 arm64: dts: marvell: armada-37xx: drop redundant status property
6060a7d20d45 arm64: dts: marvell: armada-37xx: align 'phy-names' of EHCI node with DT schema
35534e644dcb dt-bindings: arm64: add Marvell 7k COMe boards
1dcb86d924dc arm64: dts: marvell: armada-3720: drop 'marvell,xenon-emmc' properties
2bb1a9babe39 arm64: dts: marvell: uDPU: add ethernet aliases
b50530300a29 arm/arm64: dts: marvell: Drop unused .dtsi
2db42793452f arm64: dts: a7k: use phy handle
d5fc105cb250 ASoC: tegra: Add support for WM8962 and CPCAP
5423831ff03c PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC
28d437903eda ASoC: partial match the sdca codec name
fbe3ea5c831a arm64: dts: rockchip: Make Jaguar PCIe-refclk pin use pull-up config
44a929a3397f arm64: dts: rockchip: add pinctrl for clk-generator GPIO on rk3588-tiger
602fd7427255 arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-tiger
05116be7a4d0 arm64: dts: rockchip: use gated-fixed-clock for pcie-refclk on rk3588-jaguar
fd607e2918b1 arm64: dts: rockchip: Enable displayport for rk3576 evb2
9664058abc30 arm64: dts: rockchip: Add battery and charger on rk3566-pinenote
ac55eb6a4306 dt-bindings: clock: rockchip: Add RV1103B CRU support
176225b2d111 riscv: dts: spacemit: adapt regulator node name to preferred form
cf5a183295c4 arm64: dts: rockchip: Fix sdmmc pwren pinctrl for rk3576-evb2
1b32f4215350 arm64: dts: zena: Add support for Zena CSS
37968efee2d9 dt-bindings: arm: Add Zena CSS compatibility
0066303ab7b2 arm64: dts: mediatek: mt7988a-bpi-r4pro: fix model string
17d45396c879 dt-bindings: pinctrl: marvell,armada3710-xb-pinctrl: add missing items keyword
e4b6173cb2f7 Merge tag 'drm-misc-next-2026-02-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
aa65b47dd9d2 ASoC: dt-bindings: nvidia,tegra-audio-max9808x: document additional board pins
259d84fbff82 ASoC: dt-bindings: nvidia,tegra-audio: document WM8962 CODEC
68e1a2bfa79b ASoC: dt-bindings: nvidia,tegra-audio: document CPCAP CODEC
9ef5731ee2bc dt-bindings: iio: gyroscope: bosch,bmg160: add bmx055 gyroscope binding
99f8dd4df370 dt-bindings: iio: magnetometer: bosch,bmc150_magn: add bmx055 magnetometer binding
5edeff3a9bdc dt-bindings: iio: accel: bosch,bma255: add bmx055 accel binding
a9159a54b427 dt-bindings: iio: adc: adi,ad4030: Add ADAQ4216 and ADAQ4224
ccfe81e590ec dt-bindings: iio: adc: adi,ad4030: Add PWM
1b4c4b828ee5 scsi: ufs: qcom,sc7180-ufshc: dt-bindings: Add UFSHC compatible for x1e80100
26eb4bb49b73 scsi: ufs: qcom,sc7180-ufshc: dt-bindings: Document the Milos UFS Controller
f3f1e0911667 arm64: dts: exynosautov920: add CMU_G3D clock DT nodes
7e0803a60718 dt-bindings: clock: exynosautov920: add G3D clock definitions
4a1147e38aa8 arm64: dts: exynos: gs101-pixel: add all S2MPG1x regulators
4f7f76158e28 ARM: dts: microchip: sama7d65: add LVDS controller
58bb66734182 ARM: dts: microchip: sama7d65: add LCD controller
5348506dae16 dt-bindings: crypto: ice: add operating-points-v2 property for QCOM ICE
9f58c4ef401d dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY
f5faf6bd8f72 dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
036d727a1243 dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
e0d43e01c3d5 dt-bindings: phy: Add Canaan K230 USB PHY
070f325c50bf dt-bindings: pinctrl: pincfg-node: add restrictions on conflicting properties
07d3d0dcc6d4 mfd: cpcap: convert documentation to schema and add
091302ab1d4b ARM: dts: exynos: Add Google Manta (Nexus 10)
3385fdd73dc7 dt-bindings: ARM: samsung: Add Google Manta (Nexus 10)
8d6cd624655c regulator: dt-bindings: cpcap-regulator: document Mot regulator
923025247dbb regulator: dt-bindings: cpcap-regulator: convert to DT schema
9a7a39c21994 dt-bindings: input: Add Parade TC3408 touchscreen controller
b6fd98316f66 dt-bindings: dma: snps,dw-axi-dmac: Add CV1800B compatible
0649d330e78b riscv: dts: spacemit: Update PMIC supply properties for BPI-F3 and Jupiter
c3fdbf9b8d4a riscv: dts: spacemit: pcie: fix missing power regulator
dbac6b706387 dt-bindings: firmware: google,gs101-acpm-ipc: add S2MPG11 secondary PMIC
af038aebf541 arm64: dts: exynos: add initial support for Samsung Galaxy J7 (2016)
f8be95695d75 dt-bindings: arm: samsung: add compatible for samsung-j7xelte
092e1f90d44e dt-bindings: cache: bt1-l2-ctl: Remove unused bindings
7d3e9ec7e4c9 dt-bindings: usb: st,st-ohci-300x: convert to DT schema
218ff51da14a dt-bindings: usb: introduce nxp,imx-dwc3
cda397b2ceef dt-bindings: usb: ti,dwc3: convert to DT schema
09322d278473 dt-bindings: usb: ti,omap4-musb: convert to DT schema
3714ca7758f8 dt-bindings: mtd: mxc-nand: add i.MX25 and i.MX27 nand support
949504fdf636 dt-bindings: mtd: Describe MTD partitions concatenation
e4770c48b962 arm64: dts: qcom: x1-vivobook-s15: add Purwa-compatible device tree
690c2de35eb4 arm64: dts: qcom: x1-vivobook-s15: create a common dtsi for Hamoa and Purwa variants
9e35833a1c1a dt-bindings: arm: qcom: Add ASUS Vivobook X1P42100 variant
49c782cd6a42 dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
1107d192f777 dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
43e557012b37 arm64: dts: qcom: merge duplicate references to pmc8380_3_gpios
f546cc40f96a arm64: dts: qcom: add apq8096sg-db820c, AP8096SG variant of DB820c
6a53aa9e4ee3 dt-bindings: arm: qcom: add Dragonboard 820c using APQ8096SG SoC
7f7722af5cc5 arm64: dts: imx93-11x11-evk: change usdhc tuning step for eMMC and SD
e193a4eda155 arm64: dts: imx91-11x11-evk: change usdhc tuning step for eMMC and SD
412f307ab88e dt-bindings: arm: cpus: Deprecate Qualcomm generic compatibles
e4693ef5e9d4 dt-bindings: arm: fsl: Add i.MX93 Wireless EVK board
8e3089836514 dt-bindings: arm: fsl: add Variscite DART-MX95 Boards
f4b18ef50b62 dt-bindings: soc: imx93-media-blk-ctrl: Add PDFC subnode to schema and example
cd34d142b3b4 arm64: dts: imx95-evk: update the dma-channel-mask property
998ecdabc93c arm64: dts: imx95: Reserve eDMA channels 0-1 for V2X
cc4ae371aea7 arm64: dts: imx93: Add i.MX93 Wireless EVK board support
5c2528438b68 arm64: dts: imx93: Add imx93w.dtsi for i.MX93 Wireless SiP
6adbd8af184a arm64: dts: imx93: Move 11x11 EVK specific parts back to imx93-11x11-evk.dts
8de2aac84b9d arm64: dts: imx93: Extract common EVK description into shared dtsi
e45b6ba9f243 arm64: dts: imx95-15x15-frdm: support AONMIX MQS
2590f86f0edb arm64: dts: imx95: add AONMIX MQS node
0ed4bc8b5e1a arm64: dts: freescale: imx95-toradex-smarc: fix PMIC_SD2_VSEL label position
cab1a0ec4e61 ARM: dts: imx51-babbage: rename at45db321d@1 to flash@1
a100721b1c46 ARM: dts: imx51-ts4800: rename fpga@0 to fpga@0,0
8e9cdf79a93f ARM: dts: imx35: remove simple-bus 'usbphy'
ec887f8b5c52 ARM: dts: imx35: rename i2c clock-names to ipg
6e233f3150fe ARM: dts: imx35: rename emi to emi-bus to fix CHECK_DTBS warning
20bdf086f0ae arm64: dts: imx8-apalis: Fix LEDs name collision
acf55a42536b arm64: dts: imx8-apalis: Remove obsolete TODO comment
c32ae1da50fd arm64: dts: imx943-evk: enable lpuart6 for Bluetooth
b3102cb49bfa arm64: dts: imx93-14x14-evk: enable lpuart5 for Bluetooth
a16e129abc1f arm64: dts: imx8-apalis: Disable the audmix
2083eca6cf92 arm64: dts: imx95-19x19-evk: enable lpuart5 for Bluetooth support
53f692242c45 arm64: dts: imx93-evk/qsb: add m2-pcm-level-shifter-hog to enable BT HFP
f391477d8f4e arm64: dts: imx93: Add parallel display output nodes
8d193a70ecea ata: ahci-dwc: Remove not-going-to-be-supported code for Baikal SoC
8470313a08f5 arm64: dts: axis: artpec9: Fix missing soc unit address
73db7cd1b035 ARM: dts: arm: Use lowercase hex
06a0ba3a4bd8 arm64: dts: axis: Add ARTPEC-9 Alfred board support
a0c4f0863e64 arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC support
6f2b1bd45192 dt-bindings: arm: axis: Add ARTPEC-9 alfred board
0b9f8401e576 dt-bindings: clock: Add ARTPEC-9 clock controller
de16b446de6e ARM: dts: mediatek: mt7623: fix efuse fallback compatible
44ab4b6fd671 arm64: dts: mt8167: Reorder nodes according to mmio address
a7eef1e6c2c4 dt-bindings: mmc: rockchip-dw-mshc: Add RV1103B compatible
895b09946bfb dt-bindings: mmc: arasan,sdhci: Add Axiado AX3000 SoC
22ce1d7d45a6 arm64: dts: mediatek: mt6359: give regulators unique names
a83c88438856 arm64: dts: mediatek: mt8365: Describe infracfg-nao as a pure syscon
b71e3233a1c8 arm64: dts: mediatek: mt8365-evk: add mmc aliases
be7958c27a84 arm64: dts: mediatek: mt8395-radxa-nio-12l: add mmc aliases
2a12bbb63e85 arm64: dts: mediatek: mt8395-genio-common: add mmc aliases
5a9daaeeb9fc arm64: dts: mediatek: mt8195-cherry: Disable xhci1 completely
2a476e696b91 dt-bindings: pinctrl: imx35: add compatible string fsl,imx25-iomuxc
0ca16e2989a1 dt-bindings: pinctrl: convert fsl,imx27-pinctrl.txt to YAML
b36d95456124 dt-bindings: pinctrl: document the Eliza Top Level Mode Multiplexer
8a618c303e95 arm64: dts: freescale: imx93-phy{core,board}: Add i2c bus recovery
0270e5d8206e ARM: dts: imx6ull-engicam-microgea-bmm: set touchscreen glitch threshold
da35363815ef Merge branch 'ib-iio-thermal-qcom-pmic5' into togreg Immutable branch to allow this base work to be merged into thermal.
b3442f4bce6b dt-bindings: iio: amplifiers: Add AD8366 support
3d68f155b9e1 dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC
41474105bf70 dt-bindings: iio: adc: Split out QCOM VADC channel properties
a4dca5d658f1 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8940
4eb2e1589890 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8937
451379f4414d dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8917
2940be16dba8 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MDM9607
2bc7f3608e8c arm64: dts: imx8mp-evk: add bluetooth dts node
d45b8f4821d5 arm64: dts: imx8mp-evk: replace space with tab
b569979c1a23 arm64: dts: imx8mn-evk: add bluetooth dts node
d158b82107a8 arm64: dts: imx8mm-evk: add uart3 port
5aaddc504098 arm64: dts: imx8mm-evk: add uart1 and bluetooth node
a4118f8c06a3 arm64: dts: imx8mm-evk: correct the spdif compatible string
1f59376d1824 arm64: dts: imx8mm-evk: replace space with tab
b1908c258ebd dt-bindings: fsl: add compatible string fsl,imx25-aips
d2c6da7b4113 dt-bindings: clock: qcom: Add video clock controller on Glymur SoC
b67b96c1c98f dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur
b076e54c8dc7 dt-bindings: clock: qcom: document the Glymur GPU Clock Controller
45dfd16e3ca5 dt-bindings: soc: qcom: qcom,pmic-glink: Add Glymur and Kaanapali compatibles
3c0f0d6ab687 dt-bindings: clock: qcom,glymur-dispcc: De-acronymize SoC name
0496c7023285 arm64: dts: qcom: glymur: Enable Glymur CRD board support
7fb2a2b7bd4e arm64: dts: qcom: Introduce Glymur base dtsi
41ace86d903f dt-bindings: arm: qcom: Document Glymur SoC and board
44237fa7548c spi: dt-bindings: renesas,rzv2h-rspi: allow multiple DMAs
cda65260e08e arm64: dts: hisilicon: hikey960/970: Convert to use standard mmc alias
9480455d1baf dt-bindings: mmc: add binding for BST DWCMSHC SDHCI controller
e6388d9d0f80 dt-bindings: mmc: spacemit,sdhci: add support for K3 SoC
cc91f181eec9 dt-bindings: mmc: arm,pl18x: Do not use plural form of a proper noun PrimeCell
f10b6a397d94 dt-bindings: mmc: spacemit,sdhci: add reset support
4146defe73ca dt-bindings: mmc: arasan,sdhci: Allow "dma-coherent" property
f58d028606dd dt-bindings: mmc: brcm,iproc-sdhci: Allow "dma-coherent" and "iommus" properties
082db39f0cf6 dt-bindings: mmc: cdns,sdhci: Drop required "resets" on AMD Pensando ELBA
be14a669ebe3 dt-bindings: mmc: mtk-sd: Add support for MT8189 SoC
eb296f43e2ba dt-bindings: power: Add MediaTek MT8189 power domain
3c5fed690886 dt-bindings: power: mt7622-power: Add MT7622_POWER_DOMAIN_AUDIO
2466d7ee1dfe dt-bindings: power: mt8196-gpufreq: Describe nvmem provider ability
6762f98e0cdb dt-bindings: power: define ID for Marvell PXA1908 audio domain
e9cb669f1d0d Merge drm/drm-next into drm-misc-next
212be72a6ba4 dt-bindings: pinctrl: qcom,sm8450-lpass-lpi-pinctrl: Add SA8775P and QCS8300 pinctrl
d4224292c0d8 dt-bindings: pinctrl: rockchip: Add RV1103B compatible
43d48f114036 dt-bindings: iio: dac: Fix typo in ti,dac7612.yaml
3710465cab64 dt-bindings: iio: adc: adi,ad4080: add support for AD4082, AD4085 and AD4088
416cecf7b7e8 dt-bindings: iio: adc: adi,ad4030: Reference spi-peripheral-props
52d42a4312bb dt-bindings: iio: light: vcnl4000: add Capella CM36686 and CM36672P
267ee8872423 dt-bindings: iio: adc: adi,ad7380: add spi-rx-bus-width property
6d25dc37f112 dt-bindings: iio: proximity: hx9023s: support firmware-name property
065f45e3115d ARM: dts: aspeed: anacapa: Add retimer EEPROMs
f51b0cca97e7 dt-bindings: mfd: spacemit,p1: Add individual regulator supply properties
fe39ffd09719 ASoC: dt-bindings: awinic,aw88395: Document firmware-name property
ce14fbfa5f94 arm64: dts: nuvoton: drop unused syscon property from watchdog node
8940c3e260e9 ARM: dts: aspeed: anacapa: add NFC device
8bc5cc4d3c09 ARM: dts: aspeed: Add Asrock Paul IPMI card
0e273e1db58d dt-bindings: arm: aspeed: Add Asrock Paul IPMI card
33f17534d242 ARM: dts: aspeed: Add 128M alt flash layout to NVIDIA MSX4
af5cbcc119cf ARM: dts: aspeed: Add Asus Kommando IPMI card
293a6898fc7d dt-bindings: arm: aspeed: Add Asus Kommando IPMI card
11428af279d0 arm64: dts: rockchip: Describe HDMI supplies for nanopi4 boards
f7b8299cbae5 arm64: dts: rockchip: Clean up NanoPi-R2S Plus gmac2io
78f66af66a8a arm64: dts: rockchip: add pwm-fan for NanoPC-T6
adba73229e08 arm64: dts: rockchip: Add rk3576 evb2 board
cf9bb4565c2a dt-bindings: arm: rockchip: Add rk3576 evb2 board
11fd08fabdf7 arm64: dts: rockchip: Add overlay for FriendlyElec HD702E
e386d997b5b5 arm64: dts: rockchip: Move RK3399 eDP pinctrl to boards
110e8499e8fc arm64: dts: rockchip: add overlay for qnap-ts133 device revision
1ef9b5f07fbf arm64: dts: rockchip: add overlay for qnap-ts233 device revision
aabcc7c8186d arm64: dts: rockchip: add overlay for qnap-ts433 device revision
98d4b5155921 arm64: dts: rockchip: Add port subnodes to RK356x SATA controllers
5f91aeabf85a arm64: dts: rockchip: add Awinic aw87391 amplifiers for Anbernic RG-DS
a46f65b32bcd arm64: dts: rockchip: Add supply for pd_rkvdec and pd_venc on rk3388-evbs
6ea507542114 arm64: dts: rockchip: add node name for RK3588_PD_RKVDEC0/1 and RK3588_PD_VENC0/1
63aa02df84f4 arm64: dts: rockchip: Add OneThing Edge Cube series
76f4a58eddc4 dt-bindings: arm: rockchip: Add OneThing Edge Cube series
42f013ece2d6 dt-bindings: vendor-prefixes: Add Shenzhen OneThing Technologies Co., Ltd.
1063e17d2567 arm64: dts: rockchip: Add DisplayPort dt node for rk3576
71071eda69f4 dt-bindings: display: rockchip: Add rk3576 DisplayPort
798b9f753f0f dt-bindings: display: lt9611: Support single Port B input
344f02f7f12b dt-bindings: display: tilcdc: Mark panel binding as deprecated
2d2a8ac9a7c6 dt-bindings: display: tilcdc: Convert to DT schema
38382922b6f8 dt-bindings: drm/bridge: anx7625: describe Type-C connector
8fc657cfd6f1 Merge drm/drm-next into drm-misc-next
a9ea3154e5c2 dt-bindings: display/bridge: add binding for TH1520 HDMI controller
25c467ec6fe8 dt-bindings: display: add verisilicon,dc
e94eef888bd5 dt-bindings: vendor-prefixes: add verisilicon
271ddfa2fbc6 dt-bindings: display: panel: Move FriendlyElec HD702E to eDP
4183ce07d60c dt-bindings: display: bridge: ldb: Document nxp, enable-termination-resistor

git-subtree-dir: dts/upstream
git-subtree-split: e8613e1cf44541aa3f22e5ac52ac63138cb4aa15

43 files changed, 2983 insertions, 53 deletions

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 8776844e0ee..336f7bb7188 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -245,6 +245,7 @@
 #define QCOM_ID_IPQ5000			503
 #define QCOM_ID_IPQ0509			504
 #define QCOM_ID_IPQ0518			505
+#define QCOM_ID_SM7450			506
 #define QCOM_ID_SM6375			507
 #define QCOM_ID_IPQ9514			510
 #define QCOM_ID_IPQ9550			511
@@ -260,10 +261,12 @@
 #define QCOM_ID_SM8475			530
 #define QCOM_ID_SM8475P			531
 #define QCOM_ID_SA8255P			532
+#define QCOM_ID_SA8650P			533
 #define QCOM_ID_SA8775P			534
 #define QCOM_ID_QRU1000			539
 #define QCOM_ID_SM8475_2		540
 #define QCOM_ID_QDU1000			545
+#define QCOM_ID_SM7450P			547
 #define QCOM_ID_X1E80100		555
 #define QCOM_ID_SM8650			557
 #define QCOM_ID_SM4450			568
@@ -294,6 +297,13 @@
 #define QCOM_ID_QCS8275			675
 #define QCOM_ID_QCS9075			676
 #define QCOM_ID_QCS615			680
+#define QCOM_ID_CQ7790M			731
+#define QCOM_ID_CQ7790S			732
+#define QCOM_ID_IPQ5200			765
+#define QCOM_ID_IPQ5210			766
+#define QCOM_ID_QCF2200			767
+#define QCOM_ID_QCF3200			768
+#define QCOM_ID_QCF3210			769
 
 /*
  * The board type and revision information, used by Qualcomm bootloaders and
diff --git a/include/dt-bindings/clock/axis,artpec9-clk.h b/include/dt-bindings/clock/axis,artpec9-clk.h
new file mode 100644
index 00000000000..c6787be8d68
--- /dev/null
+++ b/include/dt-bindings/clock/axis,artpec9-clk.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ * Copyright (c) 2025  Axis Communications AB.
+ *             https://www.axis.com
+ *
+ * Device Tree binding constants for ARTPEC-9 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
+#define _DT_BINDINGS_CLOCK_ARTPEC9_H
+
+/* CMU_CMU */
+#define CLK_FOUT_SHARED0_PLL						1
+#define CLK_DOUT_SHARED0_DIV2						2
+#define CLK_DOUT_SHARED0_DIV3						3
+#define CLK_DOUT_SHARED0_DIV4						4
+#define CLK_FOUT_SHARED1_PLL						5
+#define CLK_DOUT_SHARED1_DIV2						6
+#define CLK_DOUT_SHARED1_DIV3						7
+#define CLK_DOUT_SHARED1_DIV4						8
+#define CLK_FOUT_AUDIO_PLL						9
+#define CLK_DOUT_CMU_ADD						10
+#define CLK_DOUT_CMU_BUS						11
+#define CLK_DOUT_CMU_CDC_CORE						12
+#define CLK_DOUT_CMU_CORE_MAIN						13
+#define CLK_DOUT_CMU_CPUCL_SWITCH					14
+#define CLK_DOUT_CMU_DLP_CORE						15
+#define CLK_DOUT_CMU_FSYS0_BUS						16
+#define CLK_DOUT_CMU_FSYS0_IP						17
+#define CLK_DOUT_CMU_FSYS1_BUS						18
+#define CLK_DOUT_CMU_FSYS1_SCAN0					19
+#define CLK_DOUT_CMU_FSYS1_SCAN1					20
+#define CLK_DOUT_CMU_GPU_3D						21
+#define CLK_DOUT_CMU_GPU_2D						22
+#define CLK_DOUT_CMU_IMEM_ACLK						23
+#define CLK_DOUT_CMU_IMEM_CA5						24
+#define CLK_DOUT_CMU_IMEM_JPEG						25
+#define CLK_DOUT_CMU_IMEM_SSS						26
+#define CLK_DOUT_CMU_IPA_CORE						27
+#define CLK_DOUT_CMU_LCPU						28
+#define CLK_DOUT_CMU_MIF_SWITCH						29
+#define CLK_DOUT_CMU_MIF_BUSP						30
+#define CLK_DOUT_CMU_PERI_DISP						31
+#define CLK_DOUT_CMU_PERI_IP						32
+#define CLK_DOUT_CMU_RSP_CORE						33
+#define CLK_DOUT_CMU_TRFM						34
+#define CLK_DOUT_CMU_VIO_CORE_L						35
+#define CLK_DOUT_CMU_VIO_CORE						36
+#define CLK_DOUT_CMU_VIP0						37
+#define CLK_DOUT_CMU_VIP1						38
+#define CLK_DOUT_CMU_VPP_CORE						39
+#define CLK_DOUT_CMU_VIO_AUDIO						40
+
+/* CMU_BUS */
+#define CLK_MOUT_BUS_ACLK_USER						1
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_ACLK_USER						1
+
+/* CMU_CPUCL */
+#define CLK_FOUT_CPUCL_PLL0						1
+#define CLK_MOUT_CPUCL_PLL0						2
+#define CLK_FOUT_CPUCL_PLL1						3
+#define CLK_MOUT_CPUCL_PLL_SCU						4
+#define CLK_MOUT_CPUCL_SWITCH_SCU_USER					5
+#define CLK_MOUT_CPUCL_SWITCH_USER					6
+#define CLK_DOUT_CPUCL_CPU						7
+#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK				8
+#define CLK_DOUT_CPUCL_CLUSTER_GICCLK					9
+#define CLK_DOUT_CPUCL_CLUSTER_PCLK					10
+#define CLK_DOUT_CPUCL_CMUREF						11
+#define CLK_DOUT_CPUCL_CLUSTER_ATCLK					12
+#define CLK_DOUT_CPUCL_CLUSTER_SCU					13
+#define CLK_DOUT_CPUCL_DBG						14
+#define CLK_GOUT_CPUCL_SHORTSTOP					15
+#define CLK_GOUT_CPUCL_CLUSTER_CPU					16
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK				17
+#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG				18
+
+/* CMU_FSYS0 */
+#define CLK_MOUT_FSYS0_BUS_USER						1
+#define CLK_MOUT_FSYS0_IP_USER						2
+#define CLK_MOUT_FSYS0_MAIN_USER					3
+#define CLK_DOUT_FSYS0_125						4
+#define CLK_DOUT_FSYS0_ADC						5
+#define CLK_DOUT_FSYS0_BUS_300						6
+#define CLK_DOUT_FSYS0_EQOS0						7
+#define CLK_DOUT_FSYS0_EQOS1						8
+#define CLK_DOUT_FSYS0_MMC_CARD0					9
+#define CLK_DOUT_FSYS0_MMC_CARD1					10
+#define CLK_DOUT_FSYS0_MMC_CARD2					11
+#define CLK_DOUT_FSYS0_QSPI						12
+#define CLK_DOUT_FSYS0_SFMC_NAND					13
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I			14
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I			15
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250	16
+#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK		17
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250	18
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK		19
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I			20
+#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I			21
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK			22
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK			23
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK				24
+#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK			25
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK			26
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK			27
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK				28
+#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK			29
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN				30
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN				31
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN				32
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK				33
+#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK				34
+#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND			35
+#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK				36
+#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK				37
+#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK				38
+#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK				39
+#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK				40
+#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0				41
+
+/* CMU_FSYS1 */
+#define CLK_FOUT_FSYS1_PLL						1
+#define CLK_MOUT_FSYS1_SCAN0_USER					2
+#define CLK_MOUT_FSYS1_SCAN1_USER					3
+#define CLK_MOUT_FSYS1_BUS_USER						4
+#define CLK_DOUT_FSYS1_200						5
+#define CLK_DOUT_FSYS1_BUS_300						6
+#define CLK_DOUT_FSYS1_OTP_MEM						7
+#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL				8
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100		9
+#define CLK_GOUT_FSYS1_UART0_PCLK					10
+#define CLK_GOUT_FSYS1_UART0_SCLK_UART					11
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300		12
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC		13
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC		14
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC		15
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC		16
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC		17
+#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC		18
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20		19
+#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY			20
+#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK			21
+#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK				22
+
+/* CMU_IMEM */
+#define CLK_MOUT_IMEM_ACLK_USER						1
+#define CLK_MOUT_IMEM_CA5_USER						2
+#define CLK_MOUT_IMEM_SSS_USER						3
+#define CLK_MOUT_IMEM_JPEG_USER						4
+#define CLK_DOUT_IMEM_PCLK						5
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK				6
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN				7
+#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG				8
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK				9
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN				10
+#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG				11
+#define CLK_GOUT_IMEM_MCT0_PCLK						12
+#define CLK_GOUT_IMEM_MCT1_PCLK						13
+#define CLK_GOUT_IMEM_MCT2_PCLK						14
+#define CLK_GOUT_IMEM_MCT3_PCLK						15
+#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF					16
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_IP_USER						1
+#define CLK_MOUT_PERI_DISP_USER						2
+#define CLK_DOUT_PERI_125						3
+#define CLK_DOUT_PERI_PCLK						4
+#define CLK_DOUT_PERI_SPI						5
+#define CLK_DOUT_PERI_UART1						6
+#define CLK_DOUT_PERI_UART2						7
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK			8
+#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK			9
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK			10
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK				11
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK				12
+#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK			13
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK			14
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK				15
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK				16
+#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK			17
+#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS			18
+#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK				19
+#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK				20
+#define CLK_GOUT_PERI_SPI0_PCLK						21
+#define CLK_GOUT_PERI_SPI0_SCLK_SPI					22
+#define CLK_GOUT_PERI_UART1_PCLK					23
+#define CLK_GOUT_PERI_UART1_SCLK_UART					24
+#define CLK_GOUT_PERI_UART2_PCLK					25
+#define CLK_GOUT_PERI_UART2_SCLK_UART					26
+
+#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
deleted file mode 100644
index 5f166d27a00..00000000000
--- a/include/dt-bindings/clock/bt1-ccu.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
- *
- * Baikal-T1 CCU clock indices
- */
-#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
-#define __DT_BINDINGS_CLOCK_BT1_CCU_H
-
-#define CCU_CPU_PLL			0
-#define CCU_SATA_PLL			1
-#define CCU_DDR_PLL			2
-#define CCU_PCIE_PLL			3
-#define CCU_ETH_PLL			4
-
-#define CCU_AXI_MAIN_CLK		0
-#define CCU_AXI_DDR_CLK			1
-#define CCU_AXI_SATA_CLK		2
-#define CCU_AXI_GMAC0_CLK		3
-#define CCU_AXI_GMAC1_CLK		4
-#define CCU_AXI_XGMAC_CLK		5
-#define CCU_AXI_PCIE_M_CLK		6
-#define CCU_AXI_PCIE_S_CLK		7
-#define CCU_AXI_USB_CLK			8
-#define CCU_AXI_HWA_CLK			9
-#define CCU_AXI_SRAM_CLK		10
-
-#define CCU_SYS_SATA_REF_CLK		0
-#define CCU_SYS_APB_CLK			1
-#define CCU_SYS_GMAC0_TX_CLK		2
-#define CCU_SYS_GMAC0_PTP_CLK		3
-#define CCU_SYS_GMAC1_TX_CLK		4
-#define CCU_SYS_GMAC1_PTP_CLK		5
-#define CCU_SYS_XGMAC_REF_CLK		6
-#define CCU_SYS_XGMAC_PTP_CLK		7
-#define CCU_SYS_USB_CLK			8
-#define CCU_SYS_PVT_CLK			9
-#define CCU_SYS_HWA_CLK			10
-#define CCU_SYS_UART_CLK		11
-#define CCU_SYS_I2C1_CLK		12
-#define CCU_SYS_I2C2_CLK		13
-#define CCU_SYS_GPIO_CLK		14
-#define CCU_SYS_TIMER0_CLK		15
-#define CCU_SYS_TIMER1_CLK		16
-#define CCU_SYS_TIMER2_CLK		17
-#define CCU_SYS_WDT_CLK			18
-
-#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
diff --git a/include/dt-bindings/clock/econet,en751221-scu.h b/include/dt-bindings/clock/econet,en751221-scu.h
new file mode 100644
index 00000000000..318ec8a4670
--- /dev/null
+++ b/include/dt-bindings/clock/econet,en751221-scu.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+
+#define EN751221_CLK_PCIE	0
+#define EN751221_CLK_SPI	1
+#define EN751221_CLK_BUS	2
+#define EN751221_CLK_CPU	3
+#define EN751221_CLK_GSW	4
+
+#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */
diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h
new file mode 100644
index 00000000000..d7ef697d0f7
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-clock.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 clock controller.
+ *
+ * Authors:
+ *	Yifeng Huang <[email protected]>
+ *	Xuyang Dong <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+
+#define EIC7700_CLK_XTAL_32K				0
+#define EIC7700_CLK_PLL_CPU				1
+#define EIC7700_CLK_SPLL0_FOUT1				2
+#define EIC7700_CLK_SPLL0_FOUT2				3
+#define EIC7700_CLK_SPLL0_FOUT3				4
+#define EIC7700_CLK_SPLL1_FOUT1				5
+#define EIC7700_CLK_SPLL1_FOUT2				6
+#define EIC7700_CLK_SPLL1_FOUT3				7
+#define EIC7700_CLK_SPLL2_FOUT1				8
+#define EIC7700_CLK_SPLL2_FOUT2				9
+#define EIC7700_CLK_SPLL2_FOUT3				10
+#define EIC7700_CLK_VPLL_FOUT1				11
+#define EIC7700_CLK_VPLL_FOUT2				12
+#define EIC7700_CLK_VPLL_FOUT3				13
+#define EIC7700_CLK_APLL_FOUT1				14
+#define EIC7700_CLK_APLL_FOUT2				15
+#define EIC7700_CLK_APLL_FOUT3				16
+#define EIC7700_CLK_EXT_MCLK				17
+#define EIC7700_CLK_LPDDR_REF_BAK			18
+#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE		19
+#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE		20
+#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE	21
+#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE	22
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0		23
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1		24
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2		25
+#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE		26
+#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE		27
+#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE	28
+#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE		29
+#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE	30
+#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE	31
+#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1		32
+#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE		33
+#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE		34
+#define EIC7700_CLK_MUX_SATA_PHY_2MUX1			35
+#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE		36
+#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE	37
+#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE	38
+#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK		39
+#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE	40
+#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE		41
+#define EIC7700_CLK_MUX_RMII_REF_2MUX			42
+#define EIC7700_CLK_MUX_ETH_CORE_2MUX1			43
+#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1		44
+#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE		45
+#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE	46
+#define EIC7700_CLK_DIV_SYS_CFG_DYNM			47
+#define EIC7700_CLK_DIV_NOC_NSP_DYNM			48
+#define EIC7700_CLK_DIV_BOOTSPI_DYNM			49
+#define EIC7700_CLK_DIV_SCPU_CORE_DYNM			50
+#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM			51
+#define EIC7700_CLK_DIV_GPU_ACLK_DYNM			52
+#define EIC7700_CLK_DIV_DSP_ACLK_DYNM			53
+#define EIC7700_CLK_DIV_D2D_ACLK_DYNM			54
+#define EIC7700_CLK_DIV_HSP_ACLK_DYNM			55
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0		56
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1		57
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0		58
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1		59
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2		60
+#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM			61
+#define EIC7700_CLK_DIV_NPU_ACLK_DYNM			62
+#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM		63
+#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM		64
+#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM		65
+#define EIC7700_CLK_DIV_VI_ACLK_DYNM			66
+#define EIC7700_CLK_DIV_VI_DVP_DYNM			67
+#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM			68
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0		69
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1		70
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2		71
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3		72
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4		73
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5		74
+#define EIC7700_CLK_DIV_VO_ACLK_DYNM			75
+#define EIC7700_CLK_DIV_IESMCLK_DYNM			76
+#define EIC7700_CLK_DIV_VO_PIXEL_DYNM			77
+#define EIC7700_CLK_DIV_VO_MCLK_DYNM			78
+#define EIC7700_CLK_DIV_VC_ACLK_DYNM			79
+#define EIC7700_CLK_DIV_JD_DYNM				80
+#define EIC7700_CLK_DIV_JE_DYNM				81
+#define EIC7700_CLK_DIV_VE_DYNM				82
+#define EIC7700_CLK_DIV_VD_DYNM				83
+#define EIC7700_CLK_DIV_G2D_DYNM			84
+#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM			85
+#define EIC7700_CLK_DIV_CRYPTO_DYNM			86
+#define EIC7700_CLK_DIV_VI_DW_DYNM			87
+#define EIC7700_CLK_DIV_NPU_E31_DYNM			88
+#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM		89
+#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM			90
+#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM			91
+#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM			92
+#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM			93
+#define EIC7700_CLK_DIV_DDR_ACLK_DYNM			94
+#define EIC7700_CLK_DIV_AON_RTC_DYNM			95
+#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM		96
+#define EIC7700_CLK_DIV_VO_CEC_DYNM			97
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0		98
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1		99
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2		100
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3		101
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0		102
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1		103
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2		104
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3		105
+#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK		106
+#define EIC7700_CLK_GATE_SPLL0_FOUT2			107
+#define EIC7700_CLK_GATE_NOC_NSP_CLK			108
+#define EIC7700_CLK_GATE_BOOTSPI			109
+#define EIC7700_CLK_GATE_BOOTSPI_CFG			110
+#define EIC7700_CLK_GATE_SCPU_CORE			111
+#define EIC7700_CLK_GATE_SCPU_BUS			112
+#define EIC7700_CLK_GATE_LPCPU_CORE			113
+#define EIC7700_CLK_GATE_LPCPU_BUS			114
+#define EIC7700_CLK_GATE_GPU_ACLK			115
+#define EIC7700_CLK_GATE_GPU_GRAY_CLK			116
+#define EIC7700_CLK_GATE_GPU_CFG_CLK			117
+#define EIC7700_CLK_GATE_DSPT_ACLK			118
+#define EIC7700_CLK_GATE_DSPT_CFG_CLK			119
+#define EIC7700_CLK_GATE_D2D_ACLK			120
+#define EIC7700_CLK_GATE_D2D_CFG_CLK			121
+#define EIC7700_CLK_GATE_TCU_ACLK			122
+#define EIC7700_CLK_GATE_TCU_CFG_CLK			123
+#define EIC7700_CLK_GATE_DDRT_CFG_CLK			124
+#define EIC7700_CLK_GATE_DDRT0_P0_ACLK			125
+#define EIC7700_CLK_GATE_DDRT0_P1_ACLK			126
+#define EIC7700_CLK_GATE_DDRT0_P2_ACLK			127
+#define EIC7700_CLK_GATE_DDRT0_P3_ACLK			128
+#define EIC7700_CLK_GATE_DDRT0_P4_ACLK			129
+#define EIC7700_CLK_GATE_DDRT1_P0_ACLK			130
+#define EIC7700_CLK_GATE_DDRT1_P1_ACLK			131
+#define EIC7700_CLK_GATE_DDRT1_P2_ACLK			132
+#define EIC7700_CLK_GATE_DDRT1_P3_ACLK			133
+#define EIC7700_CLK_GATE_DDRT1_P4_ACLK			134
+#define EIC7700_CLK_GATE_TIMER_CLK_0			135
+#define EIC7700_CLK_GATE_TIMER_CLK_1			136
+#define EIC7700_CLK_GATE_TIMER_CLK_2			137
+#define EIC7700_CLK_GATE_TIMER_CLK_3			138
+#define EIC7700_CLK_GATE_TIMER_PCLK_0			139
+#define EIC7700_CLK_GATE_TIMER_PCLK_1			140
+#define EIC7700_CLK_GATE_TIMER_PCLK_2			141
+#define EIC7700_CLK_GATE_TIMER_PCLK_3			142
+#define EIC7700_CLK_GATE_TIMER3_CLK8			143
+#define EIC7700_CLK_GATE_PCIET_ACLK			144
+#define EIC7700_CLK_GATE_PCIET_CFG_CLK			145
+#define EIC7700_CLK_GATE_PCIET_CR_CLK			146
+#define EIC7700_CLK_GATE_PCIET_AUX_CLK			147
+#define EIC7700_CLK_GATE_NPU_ACLK			148
+#define EIC7700_CLK_GATE_NPU_CFG_CLK			149
+#define EIC7700_CLK_GATE_NPU_LLC_ACLK			150
+#define EIC7700_CLK_GATE_NPU_CLK			151
+#define EIC7700_CLK_GATE_NPU_E31_CLK			152
+#define EIC7700_CLK_GATE_VI_ACLK			153
+#define EIC7700_CLK_GATE_VI_DVP_CLK			154
+#define EIC7700_CLK_GATE_VI_CFG_CLK			155
+#define EIC7700_CLK_GATE_VI_DIG_DW_CLK			156
+#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK			157
+#define EIC7700_CLK_GATE_VI_SHUTTER_0			158
+#define EIC7700_CLK_GATE_VI_SHUTTER_1			159
+#define EIC7700_CLK_GATE_VI_SHUTTER_2			160
+#define EIC7700_CLK_GATE_VI_SHUTTER_3			161
+#define EIC7700_CLK_GATE_VI_SHUTTER_4			162
+#define EIC7700_CLK_GATE_VI_SHUTTER_5			163
+#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC		164
+#define EIC7700_CLK_GATE_VI_PHY_CFG			165
+#define EIC7700_CLK_GATE_VO_ACLK			166
+#define EIC7700_CLK_GATE_VO_CFG_CLK			167
+#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK		168
+#define EIC7700_CLK_GATE_VO_PIXEL_CLK			169
+#define EIC7700_CLK_GATE_VO_I2S_MCLK			170
+#define EIC7700_CLK_GATE_HSP_CFG_CLK			171
+#define EIC7700_CLK_GATE_VC_ACLK			172
+#define EIC7700_CLK_GATE_VC_CFG_CLK			173
+#define EIC7700_CLK_GATE_VC_JE_CLK			174
+#define EIC7700_CLK_GATE_VC_JD_CLK			175
+#define EIC7700_CLK_GATE_VC_VE_CLK			176
+#define EIC7700_CLK_GATE_VC_VD_CLK			177
+#define EIC7700_CLK_GATE_G2D_CFG_CLK			178
+#define EIC7700_CLK_GATE_G2D_CLK			179
+#define EIC7700_CLK_GATE_G2D_ACLK			180
+#define EIC7700_CLK_GATE_AONDMA_CFG			181
+#define EIC7700_CLK_GATE_AONDMA_ACLK			182
+#define EIC7700_CLK_GATE_AON_ACLK			183
+#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK		184
+#define EIC7700_CLK_GATE_VO_CR_CLK			185
+#define EIC7700_CLK_GATE_HSP_ACLK			186
+#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK		187
+#define EIC7700_CLK_GATE_RTC_CFG			188
+#define EIC7700_CLK_GATE_RTC				189
+#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK		190
+#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK		191
+#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK		192
+#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK		193
+#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK		194
+#define EIC7700_CLK_GATE_HSP_RMII_REF_0			195
+#define EIC7700_CLK_GATE_HSP_RMII_REF_1			196
+#define EIC7700_CLK_GATE_PKA_CFG			197
+#define EIC7700_CLK_GATE_SPACC_CFG			198
+#define EIC7700_CLK_GATE_CRYPTO				199
+#define EIC7700_CLK_GATE_TRNG_CFG			200
+#define EIC7700_CLK_GATE_OTP_CFG			201
+#define EIC7700_CLK_GATE_MAILBOX_0			202
+#define EIC7700_CLK_GATE_MAILBOX_1			203
+#define EIC7700_CLK_GATE_MAILBOX_2			204
+#define EIC7700_CLK_GATE_MAILBOX_3			205
+#define EIC7700_CLK_GATE_MAILBOX_4			206
+#define EIC7700_CLK_GATE_MAILBOX_5			207
+#define EIC7700_CLK_GATE_MAILBOX_6			208
+#define EIC7700_CLK_GATE_MAILBOX_7			209
+#define EIC7700_CLK_GATE_MAILBOX_8			210
+#define EIC7700_CLK_GATE_MAILBOX_9			211
+#define EIC7700_CLK_GATE_MAILBOX_10			212
+#define EIC7700_CLK_GATE_MAILBOX_11			213
+#define EIC7700_CLK_GATE_MAILBOX_12			214
+#define EIC7700_CLK_GATE_MAILBOX_13			215
+#define EIC7700_CLK_GATE_MAILBOX_14			216
+#define EIC7700_CLK_GATE_MAILBOX_15			217
+#define EIC7700_CLK_GATE_LSP_I2C0_PCLK			218
+#define EIC7700_CLK_GATE_LSP_I2C1_PCLK			219
+#define EIC7700_CLK_GATE_LSP_I2C2_PCLK			220
+#define EIC7700_CLK_GATE_LSP_I2C3_PCLK			221
+#define EIC7700_CLK_GATE_LSP_I2C4_PCLK			222
+#define EIC7700_CLK_GATE_LSP_I2C5_PCLK			223
+#define EIC7700_CLK_GATE_LSP_I2C6_PCLK			224
+#define EIC7700_CLK_GATE_LSP_I2C7_PCLK			225
+#define EIC7700_CLK_GATE_LSP_I2C8_PCLK			226
+#define EIC7700_CLK_GATE_LSP_I2C9_PCLK			227
+#define EIC7700_CLK_GATE_LSP_WDT0_PCLK			228
+#define EIC7700_CLK_GATE_LSP_WDT1_PCLK			229
+#define EIC7700_CLK_GATE_LSP_WDT2_PCLK			230
+#define EIC7700_CLK_GATE_LSP_WDT3_PCLK			231
+#define EIC7700_CLK_GATE_LSP_SSI0_PCLK			232
+#define EIC7700_CLK_GATE_LSP_SSI1_PCLK			233
+#define EIC7700_CLK_GATE_LSP_PVT_PCLK			234
+#define EIC7700_CLK_GATE_AON_I2C0_PCLK			235
+#define EIC7700_CLK_GATE_AON_I2C1_PCLK			236
+#define EIC7700_CLK_GATE_LSP_UART0_PCLK			237
+#define EIC7700_CLK_GATE_LSP_UART1_PCLK			238
+#define EIC7700_CLK_GATE_LSP_UART2_PCLK			239
+#define EIC7700_CLK_GATE_LSP_UART3_PCLK			240
+#define EIC7700_CLK_GATE_LSP_UART4_PCLK			241
+#define EIC7700_CLK_GATE_LSP_TIMER_PCLK			242
+#define EIC7700_CLK_GATE_LSP_FAN_PCLK			243
+#define EIC7700_CLK_GATE_LSP_PVT0_CLK			244
+#define EIC7700_CLK_GATE_LSP_PVT1_CLK			245
+#define EIC7700_CLK_GATE_VC_JE_PCLK			246
+#define EIC7700_CLK_GATE_VC_JD_PCLK			247
+#define EIC7700_CLK_GATE_VC_VE_PCLK			248
+#define EIC7700_CLK_GATE_VC_VD_PCLK			249
+#define EIC7700_CLK_GATE_VC_MON_PCLK			250
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK			251
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST		252
+#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2		253
+#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24		254
+#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10	255
+#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2	256
+#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2		257
+#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2		258
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2		259
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4		260
+#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20		261
+#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6	262
+#define EIC7700_CLK_DIV_NOC_WDREF_DYNM			263
+#define EIC7700_CLK_GATE_DDR0_TRACE			264
+#define EIC7700_CLK_GATE_DDR1_TRACE			265
+#define EIC7700_CLK_GATE_RNOC_NSP			266
+#define EIC7700_CLK_GATE_NOC_WDREF			267
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 80dacda5722..95285589615 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -126,6 +126,7 @@
 #define CLK_GOUT_GPIO_ALIVE_PCLK	22
 #define CLK_GOUT_PMU_ALIVE_PCLK		23
 #define CLK_GOUT_SYSREG_APM_PCLK	24
+#define CLK_GOUT_MAILBOX_APM_AP_PCLK	25
 
 /* CMU_AUD */
 #define CLK_DOUT_AUD_AUDIF		1
diff --git a/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h b/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
new file mode 100644
index 00000000000..20d84ee24ad
--- /dev/null
+++ b/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+
+#define EQ6LPC_PLL_CPU		0
+#define EQ6LPC_PLL_DDR		1
+#define EQ6LPC_PLL_PER		2
+#define EQ6LPC_PLL_VDI		3
+#define EQ6LPC_PLL_ACC		4
+
+#define EQ6LPC_CPU_OCC		5
+
+#define EQ6LPC_ACC_VDI		6
+#define EQ6LPC_ACC_OCC		7
+#define EQ6LPC_ACC_FCMU		8
+
+#define EQ6LPC_DDR_OCC		9
+
+#define EQ6LPC_PER_OCC		10
+#define EQ6LPC_PER_I2C_SER	11
+#define EQ6LPC_PER_PCLK		12
+#define EQ6LPC_PER_TSU		13
+#define EQ6LPC_PER_OSPI		14
+#define EQ6LPC_PER_GPIO		15
+#define EQ6LPC_PER_TIMER	16
+#define EQ6LPC_PER_I2C		17
+#define EQ6LPC_PER_UART		18
+#define EQ6LPC_PER_SPI		19
+#define EQ6LPC_PER_PERIPH	20
+
+#define EQ6LPC_VDI_OCC		21
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
index b9b51617a33..07051030607 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7180.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
@@ -6,6 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
 
+/* Clocks */
 #define DISP_CC_PLL0				0
 #define DISP_CC_PLL0_OUT_EVEN			1
 #define DISP_CC_MDSS_AHB_CLK			2
@@ -40,7 +41,11 @@
 #define DISP_CC_MDSS_VSYNC_CLK_SRC		31
 #define DISP_CC_XO_CLK				32
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+#define DISP_CC_MDSS_RSCC_BCR			1
+
+/* GDSCs */
 #define MDSS_GDSC				0
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h
index 4ff974f4fcc..f58b85d2c81 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm6125.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h
@@ -6,6 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
 
+/* Clocks */
 #define DISP_CC_PLL0			0
 #define DISP_CC_MDSS_AHB_CLK		1
 #define DISP_CC_MDSS_AHB_CLK_SRC	2
@@ -35,7 +36,10 @@
 #define DISP_CC_MDSS_VSYNC_CLK_SRC	26
 #define DISP_CC_XO_CLK			27
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+
+/* GDSCs */
 #define MDSS_GDSC			0
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,eliza-dispcc.h b/include/dt-bindings/clock/qcom,eliza-dispcc.h
new file mode 100644
index 00000000000..30c6d856fa9
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-dispcc.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0						0
+#define DISP_CC_PLL1						1
+#define DISP_CC_PLL2						2
+#define DISP_CC_ESYNC0_CLK					3
+#define DISP_CC_ESYNC0_CLK_SRC					4
+#define DISP_CC_ESYNC1_CLK					5
+#define DISP_CC_ESYNC1_CLK_SRC					6
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK				7
+#define DISP_CC_MDSS_AHB1_CLK					8
+#define DISP_CC_MDSS_AHB_CLK					9
+#define DISP_CC_MDSS_AHB_CLK_SRC				10
+#define DISP_CC_MDSS_BYTE0_CLK					11
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				12
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				13
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				14
+#define DISP_CC_MDSS_BYTE1_CLK					15
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				16
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				17
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				18
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				19
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				20
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				21
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				22
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				23
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			24
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			25
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				26
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			27
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				28
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			29
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		30
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				31
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				32
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				33
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				34
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				35
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			36
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				38
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				40
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			41
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				43
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				44
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				45
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				46
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				47
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			48
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				50
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				52
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			53
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				54
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				55
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				57
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				58
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			59
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			60
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				61
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			62
+#define DISP_CC_MDSS_ESC0_CLK					63
+#define DISP_CC_MDSS_ESC0_CLK_SRC				64
+#define DISP_CC_MDSS_ESC1_CLK					65
+#define DISP_CC_MDSS_ESC1_CLK_SRC				66
+#define DISP_CC_MDSS_HDMI_AHBM_CLK				67
+#define DISP_CC_MDSS_HDMI_APP_CLK				68
+#define DISP_CC_MDSS_HDMI_APP_CLK_SRC				69
+#define DISP_CC_MDSS_HDMI_CRYPTO_CLK				70
+#define DISP_CC_MDSS_HDMI_INTF_CLK				71
+#define DISP_CC_MDSS_HDMI_PCLK_CLK				72
+#define DISP_CC_MDSS_HDMI_PCLK_CLK_SRC				73
+#define DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC			74
+#define DISP_CC_MDSS_MDP1_CLK					75
+#define DISP_CC_MDSS_MDP_CLK					76
+#define DISP_CC_MDSS_MDP_CLK_SRC				77
+#define DISP_CC_MDSS_MDP_LUT1_CLK				78
+#define DISP_CC_MDSS_MDP_LUT_CLK				79
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				80
+#define DISP_CC_MDSS_PCLK0_CLK					81
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				82
+#define DISP_CC_MDSS_PCLK1_CLK					83
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				84
+#define DISP_CC_MDSS_PCLK2_CLK					85
+#define DISP_CC_MDSS_PCLK2_CLK_SRC				86
+#define DISP_CC_MDSS_RSCC_AHB_CLK				87
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				88
+#define DISP_CC_MDSS_VSYNC1_CLK					89
+#define DISP_CC_MDSS_VSYNC_CLK					90
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				91
+#define DISP_CC_OSC_CLK						92
+#define DISP_CC_OSC_CLK_SRC					93
+#define DISP_CC_SLEEP_CLK					94
+#define DISP_CC_SLEEP_CLK_SRC					95
+#define DISP_CC_XO_CLK						96
+#define DISP_CC_XO_CLK_SRC					97
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC						0
+#define MDSS_INT2_GDSC						1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,eliza-gcc.h b/include/dt-bindings/clock/qcom,eliza-gcc.h
new file mode 100644
index 00000000000..4d27b329ae9
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-gcc.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				2
+#define GCC_BOOT_ROM_AHB_CLK					3
+#define GCC_CAM_BIST_MCLK_AHB_CLK				4
+#define GCC_CAMERA_AHB_CLK					5
+#define GCC_CAMERA_HF_AXI_CLK					6
+#define GCC_CAMERA_SF_AXI_CLK					7
+#define GCC_CAMERA_XO_CLK					8
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				9
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				10
+#define GCC_CNOC_PCIE_SF_AXI_CLK				11
+#define GCC_DDRSS_GPU_AXI_CLK					12
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				13
+#define GCC_DISP_AHB_CLK					14
+#define GCC_DISP_HF_AXI_CLK					15
+#define GCC_GP1_CLK						16
+#define GCC_GP1_CLK_SRC						17
+#define GCC_GP2_CLK						18
+#define GCC_GP2_CLK_SRC						19
+#define GCC_GP3_CLK						20
+#define GCC_GP3_CLK_SRC						21
+#define GCC_GPLL0						22
+#define GCC_GPLL0_OUT_EVEN					23
+#define GCC_GPLL4						24
+#define GCC_GPLL7						25
+#define GCC_GPLL8						26
+#define GCC_GPLL9						27
+#define GCC_GPU_CFG_AHB_CLK					28
+#define GCC_GPU_GEMNOC_GFX_CLK					29
+#define GCC_GPU_GPLL0_CPH_CLK_SRC				30
+#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC				31
+#define GCC_GPU_SMMU_VOTE_CLK					32
+#define GCC_MMU_TCU_VOTE_CLK					33
+#define GCC_PCIE_0_AUX_CLK					34
+#define GCC_PCIE_0_AUX_CLK_SRC					35
+#define GCC_PCIE_0_CFG_AHB_CLK					36
+#define GCC_PCIE_0_MSTR_AXI_CLK					37
+#define GCC_PCIE_0_PHY_RCHNG_CLK				38
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				39
+#define GCC_PCIE_0_PIPE_CLK					40
+#define GCC_PCIE_0_PIPE_CLK_SRC					41
+#define GCC_PCIE_0_PIPE_DIV2_CLK				42
+#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC				43
+#define GCC_PCIE_0_SLV_AXI_CLK					44
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				45
+#define GCC_PCIE_1_AUX_CLK					46
+#define GCC_PCIE_1_AUX_CLK_SRC					47
+#define GCC_PCIE_1_CFG_AHB_CLK					48
+#define GCC_PCIE_1_MSTR_AXI_CLK					49
+#define GCC_PCIE_1_PHY_RCHNG_CLK				50
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				51
+#define GCC_PCIE_1_PIPE_CLK					52
+#define GCC_PCIE_1_PIPE_CLK_SRC					53
+#define GCC_PCIE_1_PIPE_DIV2_CLK				54
+#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC				55
+#define GCC_PCIE_1_SLV_AXI_CLK					56
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				57
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				58
+#define GCC_PCIE_RSCC_XO_CLK					59
+#define GCC_PDM2_CLK						60
+#define GCC_PDM2_CLK_SRC					61
+#define GCC_PDM_AHB_CLK						62
+#define GCC_PDM_XO4_CLK						63
+#define GCC_QMIP_CAMERA_CMD_AHB_CLK				64
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				65
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				66
+#define GCC_QMIP_GPU_AHB_CLK					67
+#define GCC_QMIP_PCIE_AHB_CLK					68
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				69
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				70
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				71
+#define GCC_QUPV3_WRAP1_CORE_CLK				72
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				73
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			74
+#define GCC_QUPV3_WRAP1_S0_CLK					75
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				76
+#define GCC_QUPV3_WRAP1_S1_CLK					77
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				78
+#define GCC_QUPV3_WRAP1_S2_CLK					79
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				80
+#define GCC_QUPV3_WRAP1_S3_CLK					81
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				82
+#define GCC_QUPV3_WRAP1_S4_CLK					83
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				84
+#define GCC_QUPV3_WRAP1_S5_CLK					85
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				86
+#define GCC_QUPV3_WRAP1_S6_CLK					87
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				88
+#define GCC_QUPV3_WRAP1_S7_CLK					89
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				90
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK				91
+#define GCC_QUPV3_WRAP2_CORE_CLK				92
+#define GCC_QUPV3_WRAP2_S0_CLK					93
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC				94
+#define GCC_QUPV3_WRAP2_S1_CLK					95
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC				96
+#define GCC_QUPV3_WRAP2_S2_CLK					97
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC				98
+#define GCC_QUPV3_WRAP2_S3_CLK					99
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC				100
+#define GCC_QUPV3_WRAP2_S4_CLK					101
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC				102
+#define GCC_QUPV3_WRAP2_S5_CLK					103
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC				104
+#define GCC_QUPV3_WRAP2_S6_CLK					105
+#define GCC_QUPV3_WRAP2_S6_CLK_SRC				106
+#define GCC_QUPV3_WRAP2_S7_CLK					107
+#define GCC_QUPV3_WRAP2_S7_CLK_SRC				108
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				109
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				110
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK				111
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK				112
+#define GCC_SDCC1_AHB_CLK					113
+#define GCC_SDCC1_APPS_CLK					114
+#define GCC_SDCC1_APPS_CLK_SRC					115
+#define GCC_SDCC1_ICE_CORE_CLK					116
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				117
+#define GCC_SDCC2_AHB_CLK					118
+#define GCC_SDCC2_APPS_CLK					119
+#define GCC_SDCC2_APPS_CLK_SRC					120
+#define GCC_UFS_PHY_AHB_CLK					121
+#define GCC_UFS_PHY_AXI_CLK					122
+#define GCC_UFS_PHY_AXI_CLK_SRC					123
+#define GCC_UFS_PHY_ICE_CORE_CLK				124
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				125
+#define GCC_UFS_PHY_PHY_AUX_CLK					126
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				127
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				128
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				129
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				130
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				131
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				132
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				133
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				134
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				135
+#define GCC_USB30_PRIM_ATB_CLK					136
+#define GCC_USB30_PRIM_MASTER_CLK				137
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				138
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				139
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			140
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		141
+#define GCC_USB30_PRIM_SLEEP_CLK				142
+#define GCC_USB3_PRIM_PHY_AUX_CLK				143
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				144
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				145
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				146
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				147
+#define GCC_VIDEO_AHB_CLK					148
+#define GCC_VIDEO_AXI0_CLK					149
+#define GCC_VIDEO_AXI1_CLK					150
+#define GCC_VIDEO_XO_CLK					151
+
+/* GCC power domains */
+#define GCC_PCIE_0_GDSC						0
+#define GCC_PCIE_0_PHY_GDSC					1
+#define GCC_PCIE_1_GDSC						2
+#define GCC_PCIE_1_PHY_GDSC					3
+#define GCC_UFS_MEM_PHY_GDSC					4
+#define GCC_UFS_PHY_GDSC					5
+#define GCC_USB30_PRIM_GDSC					6
+#define GCC_USB3_PHY_GDSC					7
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_PCIE_0_BCR						3
+#define GCC_PCIE_0_LINK_DOWN_BCR				4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
+#define GCC_PCIE_0_PHY_BCR					6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
+#define GCC_PCIE_1_BCR						8
+#define GCC_PCIE_1_LINK_DOWN_BCR				9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
+#define GCC_PCIE_1_PHY_BCR					11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
+#define GCC_PCIE_PHY_BCR					13
+#define GCC_PCIE_PHY_CFG_AHB_BCR				14
+#define GCC_PCIE_PHY_COM_BCR					15
+#define GCC_PCIE_RSCC_BCR					16
+#define GCC_PDM_BCR						17
+#define GCC_QUPV3_WRAPPER_1_BCR					18
+#define GCC_QUPV3_WRAPPER_2_BCR					19
+#define GCC_QUSB2PHY_PRIM_BCR					20
+#define GCC_QUSB2PHY_SEC_BCR					21
+#define GCC_SDCC1_BCR						22
+#define GCC_SDCC2_BCR						23
+#define GCC_UFS_PHY_BCR						24
+#define GCC_USB30_PRIM_BCR					25
+#define GCC_USB3_DP_PHY_PRIM_BCR				26
+#define GCC_USB3_DP_PHY_SEC_BCR					27
+#define GCC_USB3_PHY_PRIM_BCR					28
+#define GCC_USB3_PHY_SEC_BCR					29
+#define GCC_USB3PHY_PHY_PRIM_BCR				30
+#define GCC_USB3PHY_PHY_SEC_BCR					31
+#define GCC_VIDEO_AXI0_CLK_ARES					32
+#define GCC_VIDEO_AXI1_CLK_ARES					33
+#define GCC_VIDEO_BCR						34
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,eliza-tcsr.h b/include/dt-bindings/clock/qcom,eliza-tcsr.h
new file mode 100644
index 00000000000..aeb5e2b1a47
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-tcsr.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H
+
+/* TCSR_CC clocks */
+#define TCSR_HDMI_CLKREF_EN				0
+#define TCSR_PCIE_0_CLKREF_EN				1
+#define TCSR_PCIE_1_CLKREF_EN				2
+#define TCSR_UFS_CLKREF_EN				3
+#define TCSR_USB2_CLKREF_EN				4
+#define TCSR_USB3_CLKREF_EN				5
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
index b9d8438a15f..9ed7b794aac 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
@@ -322,5 +322,10 @@
 #define USB30_MP_GDSC						8
 #define USB30_PRIM_GDSC						9
 #define USB30_SEC_GDSC						10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC		11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC		12
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC		13
+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC			14
+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC			15
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h
index 10c12b8c51c..6907653c799 100644
--- a/include/dt-bindings/clock/qcom,glymur-gcc.h
+++ b/include/dt-bindings/clock/qcom,glymur-gcc.h
@@ -574,5 +574,6 @@
 #define GCC_VIDEO_AXI0_CLK_ARES					89
 #define GCC_VIDEO_AXI1_CLK_ARES					90
 #define GCC_VIDEO_BCR						91
+#define GCC_VIDEO_AXI0C_CLK_ARES				92
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,glymur-gpucc.h b/include/dt-bindings/clock/qcom,glymur-gpucc.h
new file mode 100644
index 00000000000..35f5abb848f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-gpucc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK						0
+#define GPU_CC_CB_CLK						1
+#define GPU_CC_CX_ACCU_SHIFT_CLK				2
+#define GPU_CC_CX_FF_CLK					3
+#define GPU_CC_CX_GMU_CLK					4
+#define GPU_CC_CXO_AON_CLK					5
+#define GPU_CC_CXO_CLK						6
+#define GPU_CC_DEMET_CLK					7
+#define GPU_CC_DPM_CLK						8
+#define GPU_CC_FF_CLK_SRC					9
+#define GPU_CC_FREQ_MEASURE_CLK					10
+#define GPU_CC_GMU_CLK_SRC					11
+#define GPU_CC_GPU_SMMU_VOTE_CLK				12
+#define GPU_CC_GX_ACCU_SHIFT_CLK				13
+#define GPU_CC_GX_ACD_AHB_FF_CLK				14
+#define GPU_CC_GX_AHB_FF_CLK					15
+#define GPU_CC_GX_GMU_CLK					16
+#define GPU_CC_GX_RCG_AHB_FF_CLK				17
+#define GPU_CC_HUB_AON_CLK					18
+#define GPU_CC_HUB_CLK_SRC					19
+#define GPU_CC_HUB_CX_INT_CLK					20
+#define GPU_CC_HUB_DIV_CLK_SRC					21
+#define GPU_CC_MEMNOC_GFX_CLK					22
+#define GPU_CC_PLL0						23
+#define GPU_CC_PLL0_OUT_EVEN					24
+#define GPU_CC_RSCC_HUB_AON_CLK					25
+#define GPU_CC_RSCC_XO_AON_CLK					26
+#define GPU_CC_SLEEP_CLK					27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC						0
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR						0
+#define GPU_CC_CX_BCR						1
+#define GPU_CC_FAST_HUB_BCR					2
+#define GPU_CC_FF_BCR						3
+#define GPU_CC_GMU_BCR						4
+#define GPU_CC_GX_BCR						5
+#define GPU_CC_XO_BCR						6
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-bindings/clock/qcom,glymur-videocc.h
new file mode 100644
index 00000000000..98c0debef8f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-videocc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK					0
+#define VIDEO_CC_AHB_CLK_SRC					1
+#define VIDEO_CC_MVS0_CLK					2
+#define VIDEO_CC_MVS0_CLK_SRC					3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC				4
+#define VIDEO_CC_MVS0_FREERUN_CLK				5
+#define VIDEO_CC_MVS0_SHIFT_CLK					6
+#define VIDEO_CC_MVS0C_CLK					7
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				8
+#define VIDEO_CC_MVS0C_FREERUN_CLK				9
+#define VIDEO_CC_MVS0C_SHIFT_CLK				10
+#define VIDEO_CC_MVS1_CLK					11
+#define VIDEO_CC_MVS1_DIV_CLK_SRC				12
+#define VIDEO_CC_MVS1_FREERUN_CLK				13
+#define VIDEO_CC_MVS1_SHIFT_CLK					14
+#define VIDEO_CC_PLL0						15
+#define VIDEO_CC_SLEEP_CLK					16
+#define VIDEO_CC_SLEEP_CLK_SRC					17
+#define VIDEO_CC_XO_CLK						18
+#define VIDEO_CC_XO_CLK_SRC					19
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC					0
+#define VIDEO_CC_MVS0C_GDSC					1
+#define VIDEO_CC_MVS1_GDSC					2
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_MVS0_BCR					1
+#define VIDEO_CC_MVS0C_BCR					2
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES				3
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES				4
+#define VIDEO_CC_MVS1_FREERUN_CLK_ARES				5
+#define VIDEO_CC_XO_CLK_ARES					6
+#define VIDEO_CC_MVS1_BCR					7
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bindings/clock/qcom,ipq5210-gcc.h
new file mode 100644
index 00000000000..84116f34ee4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
+
+#define GCC_ADSS_PWM_CLK					0
+#define GCC_ADSS_PWM_CLK_SRC					1
+#define GCC_CMN_12GPLL_AHB_CLK					2
+#define GCC_CMN_12GPLL_SYS_CLK					3
+#define GCC_CNOC_LPASS_CFG_CLK					4
+#define GCC_CNOC_PCIE0_1LANE_S_CLK				5
+#define GCC_CNOC_PCIE1_2LANE_S_CLK				6
+#define GCC_CNOC_USB_CLK					7
+#define GCC_GEPHY_SYS_CLK					8
+#define GCC_LPASS_AXIM_CLK_SRC					9
+#define GCC_LPASS_CORE_AXIM_CLK					10
+#define GCC_LPASS_SWAY_CLK					11
+#define GCC_LPASS_SWAY_CLK_SRC					12
+#define GCC_MDIO_AHB_CLK					13
+#define GCC_MDIO_GEPHY_AHB_CLK					14
+#define GCC_NSS_TS_CLK						15
+#define GCC_NSS_TS_CLK_SRC					16
+#define GCC_NSSCC_CLK						17
+#define GCC_NSSCFG_CLK						18
+#define GCC_NSSNOC_ATB_CLK					19
+#define GCC_NSSNOC_MEMNOC_1_CLK					20
+#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC				21
+#define GCC_NSSNOC_MEMNOC_CLK					22
+#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC				23
+#define GCC_NSSNOC_NSSCC_CLK					24
+#define GCC_NSSNOC_PCNOC_1_CLK					25
+#define GCC_NSSNOC_QOSGEN_REF_CLK				26
+#define GCC_NSSNOC_SNOC_1_CLK					27
+#define GCC_NSSNOC_SNOC_CLK					28
+#define GCC_NSSNOC_TIMEOUT_REF_CLK				29
+#define GCC_NSSNOC_XO_DCD_CLK					30
+#define GCC_PCIE0_AHB_CLK					31
+#define GCC_PCIE0_AUX_CLK					32
+#define GCC_PCIE0_AXI_M_CLK					33
+#define GCC_PCIE0_AXI_M_CLK_SRC					34
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK				35
+#define GCC_PCIE0_AXI_S_CLK					36
+#define GCC_PCIE0_AXI_S_CLK_SRC					37
+#define GCC_PCIE0_PIPE_CLK					38
+#define GCC_PCIE0_PIPE_CLK_SRC					39
+#define GCC_PCIE0_RCHNG_CLK					40
+#define GCC_PCIE0_RCHNG_CLK_SRC					41
+#define GCC_PCIE1_AHB_CLK					42
+#define GCC_PCIE1_AUX_CLK					43
+#define GCC_PCIE1_AXI_M_CLK					44
+#define GCC_PCIE1_AXI_M_CLK_SRC					45
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK				46
+#define GCC_PCIE1_AXI_S_CLK					47
+#define GCC_PCIE1_AXI_S_CLK_SRC					48
+#define GCC_PCIE1_PIPE_CLK					49
+#define GCC_PCIE1_PIPE_CLK_SRC					50
+#define GCC_PCIE1_RCHNG_CLK					51
+#define GCC_PCIE1_RCHNG_CLK_SRC					52
+#define GCC_PCIE_AUX_CLK_SRC					53
+#define GCC_PCNOC_BFDCD_CLK_SRC					54
+#define GCC_PON_APB_CLK						55
+#define GCC_PON_TM_CLK						56
+#define GCC_PON_TM2X_CLK					57
+#define GCC_PON_TM2X_CLK_SRC					58
+#define GCC_QDSS_AT_CLK						59
+#define GCC_QDSS_AT_CLK_SRC					60
+#define GCC_QDSS_DAP_CLK					61
+#define GCC_QDSS_TSCTR_CLK_SRC					62
+#define GCC_QPIC_AHB_CLK					63
+#define GCC_QPIC_CLK						64
+#define GCC_QPIC_CLK_SRC					65
+#define GCC_QPIC_IO_MACRO_CLK					66
+#define GCC_QPIC_IO_MACRO_CLK_SRC				67
+#define GCC_QRNG_AHB_CLK					68
+#define GCC_QUPV3_AHB_MST_CLK					69
+#define GCC_QUPV3_AHB_SLV_CLK					70
+#define GCC_QUPV3_WRAP_SE0_CLK					71
+#define GCC_QUPV3_WRAP_SE0_CLK_SRC				72
+#define GCC_QUPV3_WRAP_SE1_CLK					73
+#define GCC_QUPV3_WRAP_SE1_CLK_SRC				74
+#define GCC_QUPV3_WRAP_SE2_CLK					75
+#define GCC_QUPV3_WRAP_SE2_CLK_SRC				76
+#define GCC_QUPV3_WRAP_SE3_CLK					77
+#define GCC_QUPV3_WRAP_SE3_CLK_SRC				78
+#define GCC_QUPV3_WRAP_SE4_CLK					79
+#define GCC_QUPV3_WRAP_SE4_CLK_SRC				80
+#define GCC_QUPV3_WRAP_SE5_CLK					81
+#define GCC_QUPV3_WRAP_SE5_CLK_SRC				82
+#define GCC_SDCC1_AHB_CLK					83
+#define GCC_SDCC1_APPS_CLK					84
+#define GCC_SDCC1_APPS_CLK_SRC					85
+#define GCC_SDCC1_ICE_CORE_CLK					86
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				87
+#define GCC_SLEEP_CLK_SRC					88
+#define GCC_SNOC_LPASS_CLK					89
+#define GCC_SNOC_PCIE0_AXI_M_CLK				90
+#define GCC_SNOC_PCIE1_AXI_M_CLK				91
+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC				92
+#define GCC_UNIPHY0_AHB_CLK					93
+#define GCC_UNIPHY0_SYS_CLK					94
+#define GCC_UNIPHY1_AHB_CLK					95
+#define GCC_UNIPHY1_SYS_CLK					96
+#define GCC_UNIPHY2_AHB_CLK					97
+#define GCC_UNIPHY2_SYS_CLK					98
+#define GCC_UNIPHY_SYS_CLK_SRC					99
+#define GCC_USB0_AUX_CLK					100
+#define GCC_USB0_AUX_CLK_SRC					101
+#define GCC_USB0_MASTER_CLK					102
+#define GCC_USB0_MASTER_CLK_SRC					103
+#define GCC_USB0_MOCK_UTMI_CLK					104
+#define GCC_USB0_MOCK_UTMI_CLK_SRC				105
+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC				106
+#define GCC_USB0_PHY_CFG_AHB_CLK				107
+#define GCC_USB0_PIPE_CLK					108
+#define GCC_USB0_PIPE_CLK_SRC					109
+#define GCC_USB0_SLEEP_CLK					110
+#define GCC_XO_CLK_SRC						111
+#define GPLL0_MAIN						112
+#define GPLL0							113
+#define GPLL2_MAIN						114
+#define GPLL2							115
+#define GPLL4_MAIN						116
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
new file mode 100644
index 00000000000..28d325beb07
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ6018_CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ6018. */
+#define IPQ6018_BIAS_PLL_CC_CLK			1
+#define IPQ6018_BIAS_PLL_NSS_NOC_CLK		2
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
new file mode 100644
index 00000000000..354258a481c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ8074_CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ8074. */
+#define IPQ8074_BIAS_PLL_CC_CLK			1
+#define IPQ8074_BIAS_PLL_NSS_NOC_CLK		2
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h
new file mode 100644
index 00000000000..8fbde162c85
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-gcc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+
+/* GCC clocks */
+#define GCC_BOOT_ROM_AHB_CLK					0
+#define GCC_GP1_CLK						1
+#define GCC_GP1_CLK_SRC						2
+#define GCC_GP2_CLK						3
+#define GCC_GP2_CLK_SRC						4
+#define GCC_GPLL0						5
+#define GCC_GPLL0_OUT_EVEN					6
+#define GCC_MMU_0_TCU_VOTE_CLK					7
+#define GCC_PCIE_A_AUX_CLK					8
+#define GCC_PCIE_A_AUX_CLK_SRC					9
+#define GCC_PCIE_A_CFG_AHB_CLK					10
+#define GCC_PCIE_A_DTI_QTC_CLK					11
+#define GCC_PCIE_A_MSTR_AXI_CLK					12
+#define GCC_PCIE_A_PHY_AUX_CLK					13
+#define GCC_PCIE_A_PHY_AUX_CLK_SRC				14
+#define GCC_PCIE_A_PHY_RCHNG_CLK				15
+#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC				16
+#define GCC_PCIE_A_PIPE_CLK					17
+#define GCC_PCIE_A_PIPE_CLK_SRC					18
+#define GCC_PCIE_A_SLV_AXI_CLK					19
+#define GCC_PCIE_A_SLV_Q2A_AXI_CLK				20
+#define GCC_PCIE_B_AUX_CLK					21
+#define GCC_PCIE_B_AUX_CLK_SRC					22
+#define GCC_PCIE_B_CFG_AHB_CLK					23
+#define GCC_PCIE_B_DTI_QTC_CLK					24
+#define GCC_PCIE_B_MSTR_AXI_CLK					25
+#define GCC_PCIE_B_PHY_AUX_CLK					26
+#define GCC_PCIE_B_PHY_AUX_CLK_SRC				27
+#define GCC_PCIE_B_PHY_RCHNG_CLK				28
+#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC				29
+#define GCC_PCIE_B_PIPE_CLK					30
+#define GCC_PCIE_B_PIPE_CLK_SRC					31
+#define GCC_PCIE_B_SLV_AXI_CLK					32
+#define GCC_PCIE_B_SLV_Q2A_AXI_CLK				33
+#define GCC_PCIE_C_AUX_CLK					34
+#define GCC_PCIE_C_AUX_CLK_SRC					35
+#define GCC_PCIE_C_CFG_AHB_CLK					36
+#define GCC_PCIE_C_DTI_QTC_CLK					37
+#define GCC_PCIE_C_MSTR_AXI_CLK					38
+#define GCC_PCIE_C_PHY_AUX_CLK					39
+#define GCC_PCIE_C_PHY_AUX_CLK_SRC				40
+#define GCC_PCIE_C_PHY_RCHNG_CLK				41
+#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC				42
+#define GCC_PCIE_C_PIPE_CLK					43
+#define GCC_PCIE_C_PIPE_CLK_SRC					44
+#define GCC_PCIE_C_SLV_AXI_CLK					45
+#define GCC_PCIE_C_SLV_Q2A_AXI_CLK				46
+#define GCC_PCIE_D_AUX_CLK					47
+#define GCC_PCIE_D_AUX_CLK_SRC					48
+#define GCC_PCIE_D_CFG_AHB_CLK					49
+#define GCC_PCIE_D_DTI_QTC_CLK					50
+#define GCC_PCIE_D_MSTR_AXI_CLK					51
+#define GCC_PCIE_D_PHY_AUX_CLK					52
+#define GCC_PCIE_D_PHY_AUX_CLK_SRC				53
+#define GCC_PCIE_D_PHY_RCHNG_CLK				54
+#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC				55
+#define GCC_PCIE_D_PIPE_CLK					56
+#define GCC_PCIE_D_PIPE_CLK_SRC					57
+#define GCC_PCIE_D_SLV_AXI_CLK					58
+#define GCC_PCIE_D_SLV_Q2A_AXI_CLK				59
+#define GCC_PCIE_LINK_AHB_CLK					60
+#define GCC_PCIE_LINK_XO_CLK					61
+#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK				62
+#define GCC_PCIE_NOC_CNOC_SF_QX_CLK				63
+#define GCC_PCIE_NOC_M_CFG_CLK					64
+#define GCC_PCIE_NOC_M_PDB_CLK					65
+#define GCC_PCIE_NOC_MSTR_AXI_CLK				66
+#define GCC_PCIE_NOC_PWRCTL_CLK					67
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK				68
+#define GCC_PCIE_NOC_REFGEN_CLK					69
+#define GCC_PCIE_NOC_REFGEN_CLK_SRC				70
+#define GCC_PCIE_NOC_S_CFG_CLK					71
+#define GCC_PCIE_NOC_S_PDB_CLK					72
+#define GCC_PCIE_NOC_SAFETY_CLK					73
+#define GCC_PCIE_NOC_SAFETY_CLK_SRC				74
+#define GCC_PCIE_NOC_SLAVE_AXI_CLK				75
+#define GCC_PCIE_NOC_TSCTR_CLK					76
+#define GCC_PCIE_NOC_XO_CLK					77
+#define GCC_PDM2_CLK						78
+#define GCC_PDM2_CLK_SRC					79
+#define GCC_PDM_AHB_CLK						80
+#define GCC_PDM_XO4_CLK						81
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK				82
+#define GCC_QUPV3_WRAP3_CORE_CLK				83
+#define GCC_QUPV3_WRAP3_M_CLK					84
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK				85
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC			86
+#define GCC_QUPV3_WRAP3_S0_CLK					87
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC				88
+#define GCC_QUPV3_WRAP3_S_AHB_CLK				89
+#define GCC_SMMU_PCIE_QTC_VOTE_CLK				90
+
+/* GCC power domains */
+#define GCC_PCIE_A_GDSC						0
+#define GCC_PCIE_A_PHY_GDSC					1
+#define GCC_PCIE_B_GDSC						2
+#define GCC_PCIE_B_PHY_GDSC					3
+#define GCC_PCIE_C_GDSC						4
+#define GCC_PCIE_C_PHY_GDSC					5
+#define GCC_PCIE_D_GDSC						6
+#define GCC_PCIE_D_PHY_GDSC					7
+#define GCC_PCIE_NOC_GDSC					8
+
+/* GCC resets */
+#define GCC_PCIE_A_BCR						0
+#define GCC_PCIE_A_LINK_DOWN_BCR				1
+#define GCC_PCIE_A_NOCSR_COM_PHY_BCR				2
+#define GCC_PCIE_A_PHY_BCR					3
+#define GCC_PCIE_A_PHY_CFG_AHB_BCR				4
+#define GCC_PCIE_A_PHY_COM_BCR					5
+#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR			6
+#define GCC_PCIE_B_BCR						7
+#define GCC_PCIE_B_LINK_DOWN_BCR				8
+#define GCC_PCIE_B_NOCSR_COM_PHY_BCR				9
+#define GCC_PCIE_B_PHY_BCR					10
+#define GCC_PCIE_B_PHY_CFG_AHB_BCR				11
+#define GCC_PCIE_B_PHY_COM_BCR					12
+#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR			13
+#define GCC_PCIE_C_BCR						14
+#define GCC_PCIE_C_LINK_DOWN_BCR				15
+#define GCC_PCIE_C_NOCSR_COM_PHY_BCR				16
+#define GCC_PCIE_C_PHY_BCR					17
+#define GCC_PCIE_C_PHY_CFG_AHB_BCR				18
+#define GCC_PCIE_C_PHY_COM_BCR					19
+#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR			20
+#define GCC_PCIE_D_BCR						21
+#define GCC_PCIE_D_LINK_DOWN_BCR				22
+#define GCC_PCIE_D_NOCSR_COM_PHY_BCR				23
+#define GCC_PCIE_D_PHY_BCR					24
+#define GCC_PCIE_D_PHY_CFG_AHB_BCR				25
+#define GCC_PCIE_D_PHY_COM_BCR					26
+#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR			27
+#define GCC_PCIE_NOC_BCR					28
+#define GCC_PDM_BCR						29
+#define GCC_QUPV3_WRAPPER_3_BCR					30
+#define GCC_TCSR_PCIE_BCR					31
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h
new file mode 100644
index 00000000000..95f333d8e1a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-negcc.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+
+/* NE_GCC clocks */
+#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK			0
+#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK				1
+#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK			2
+#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK			3
+#define NE_GCC_AHB2PHY_CLK					4
+#define NE_GCC_CNOC_USB2_AXI_CLK				5
+#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK				6
+#define NE_GCC_CNOC_USB3_SEC_AXI_CLK				7
+#define NE_GCC_FRQ_MEASURE_REF_CLK				8
+#define NE_GCC_GP1_CLK						9
+#define NE_GCC_GP1_CLK_SRC					10
+#define NE_GCC_GP2_CLK						11
+#define NE_GCC_GP2_CLK_SRC					12
+#define NE_GCC_GPLL0						13
+#define NE_GCC_GPLL0_OUT_EVEN					14
+#define NE_GCC_GPLL2						15
+#define NE_GCC_GPU_2_CFG_CLK					16
+#define NE_GCC_GPU_2_GPLL0_CLK_SRC				17
+#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC				18
+#define NE_GCC_GPU_2_HSCNOC_GFX_CLK				19
+#define NE_GCC_GPU_2_SMMU_VOTE_CLK				20
+#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK				21
+#define NE_GCC_QUPV3_WRAP2_CORE_CLK				22
+#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK				23
+#define NE_GCC_QUPV3_WRAP2_S0_CLK				24
+#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC				25
+#define NE_GCC_QUPV3_WRAP2_S1_CLK				26
+#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC				27
+#define NE_GCC_QUPV3_WRAP2_S2_CLK				28
+#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC				29
+#define NE_GCC_QUPV3_WRAP2_S3_CLK				30
+#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC				31
+#define NE_GCC_QUPV3_WRAP2_S4_CLK				32
+#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC				33
+#define NE_GCC_QUPV3_WRAP2_S5_CLK				34
+#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC				35
+#define NE_GCC_QUPV3_WRAP2_S6_CLK				36
+#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC				37
+#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK				38
+#define NE_GCC_SDCC4_APPS_CLK					39
+#define NE_GCC_SDCC4_APPS_CLK_SRC				40
+#define NE_GCC_SDCC4_AXI_CLK					41
+#define NE_GCC_UFS_PHY_AHB_CLK					42
+#define NE_GCC_UFS_PHY_AXI_CLK					43
+#define NE_GCC_UFS_PHY_AXI_CLK_SRC				44
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK				45
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC				46
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK				47
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC				48
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK				49
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC			50
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK				51
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC			52
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK				53
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC			54
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK				55
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC			56
+#define NE_GCC_USB20_MASTER_CLK					57
+#define NE_GCC_USB20_MASTER_CLK_SRC				58
+#define NE_GCC_USB20_MOCK_UTMI_CLK				59
+#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC				60
+#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC			61
+#define NE_GCC_USB20_SLEEP_CLK					62
+#define NE_GCC_USB31_PRIM_ATB_CLK				63
+#define NE_GCC_USB31_PRIM_EUD_AHB_CLK				64
+#define NE_GCC_USB31_PRIM_MASTER_CLK				65
+#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC			66
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK				67
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC			68
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		69
+#define NE_GCC_USB31_PRIM_SLEEP_CLK				70
+#define NE_GCC_USB31_SEC_ATB_CLK				71
+#define NE_GCC_USB31_SEC_EUD_AHB_CLK				72
+#define NE_GCC_USB31_SEC_MASTER_CLK				73
+#define NE_GCC_USB31_SEC_MASTER_CLK_SRC				74
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK				75
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC			76
+#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC		77
+#define NE_GCC_USB31_SEC_SLEEP_CLK				78
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK				79
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC			80
+#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK			81
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK				82
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC			83
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK				84
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC				85
+#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK				86
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK				87
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC			88
+
+/* NE_GCC power domains */
+#define NE_GCC_UFS_MEM_PHY_GDSC					0
+#define NE_GCC_UFS_PHY_GDSC					1
+#define NE_GCC_USB20_PRIM_GDSC					2
+#define NE_GCC_USB31_PRIM_GDSC					3
+#define NE_GCC_USB31_SEC_GDSC					4
+#define NE_GCC_USB3_PHY_GDSC					5
+#define NE_GCC_USB3_SEC_PHY_GDSC				6
+
+/* NE_GCC resets */
+#define NE_GCC_GPU_2_BCR					0
+#define NE_GCC_QUPV3_WRAPPER_2_BCR				1
+#define NE_GCC_SDCC4_BCR					2
+#define NE_GCC_UFS_PHY_BCR					3
+#define NE_GCC_USB20_PRIM_BCR					4
+#define NE_GCC_USB31_PRIM_BCR					5
+#define NE_GCC_USB31_SEC_BCR					6
+#define NE_GCC_USB3_DP_PHY_PRIM_BCR				7
+#define NE_GCC_USB3_DP_PHY_SEC_BCR				8
+#define NE_GCC_USB3_PHY_PRIM_BCR				9
+#define NE_GCC_USB3_PHY_SEC_BCR					10
+#define NE_GCC_USB3PHY_PHY_PRIM_BCR				11
+#define NE_GCC_USB3PHY_PHY_SEC_BCR				12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h
new file mode 100644
index 00000000000..b6253dd2aa8
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+
+/* NW_GCC clocks */
+#define NW_GCC_ACMU_MUX_CLK					0
+#define NW_GCC_CAMERA_AHB_CLK					1
+#define NW_GCC_CAMERA_HF_AXI_CLK				2
+#define NW_GCC_CAMERA_SF_AXI_CLK				3
+#define NW_GCC_CAMERA_TRIG_CLK					4
+#define NW_GCC_CAMERA_XO_CLK					5
+#define NW_GCC_DISP_0_AHB_CLK					6
+#define NW_GCC_DISP_0_HF_AXI_CLK				7
+#define NW_GCC_DISP_0_TRIG_CLK					8
+#define NW_GCC_DISP_1_AHB_CLK					9
+#define NW_GCC_DISP_1_HF_AXI_CLK				10
+#define NW_GCC_DISP_1_TRIG_CLK					11
+#define NW_GCC_DPRX0_AXI_HF_CLK					12
+#define NW_GCC_DPRX0_CFG_AHB_CLK				13
+#define NW_GCC_DPRX1_AXI_HF_CLK					14
+#define NW_GCC_DPRX1_CFG_AHB_CLK				15
+#define NW_GCC_EVA_AHB_CLK					16
+#define NW_GCC_EVA_AXI0_CLK					17
+#define NW_GCC_EVA_AXI0C_CLK					18
+#define NW_GCC_EVA_TRIG_CLK					19
+#define NW_GCC_EVA_XO_CLK					20
+#define NW_GCC_FRQ_MEASURE_REF_CLK				21
+#define NW_GCC_GP1_CLK						22
+#define NW_GCC_GP1_CLK_SRC					23
+#define NW_GCC_GP2_CLK						24
+#define NW_GCC_GP2_CLK_SRC					25
+#define NW_GCC_GPLL0						26
+#define NW_GCC_GPLL0_OUT_EVEN					27
+#define NW_GCC_GPU_2_CFG_AHB_CLK				28
+#define NW_GCC_GPU_2_GPLL0_CLK_SRC				29
+#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC				30
+#define NW_GCC_GPU_2_HSCNOC_GFX_CLK				31
+#define NW_GCC_GPU_CFG_AHB_CLK					32
+#define NW_GCC_GPU_GPLL0_CLK_SRC				33
+#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC				34
+#define NW_GCC_GPU_HSCNOC_GFX_CLK				35
+#define NW_GCC_GPU_SMMU_VOTE_CLK				36
+#define NW_GCC_HSCNOC_GPU_2_AXI_CLK				37
+#define NW_GCC_HSCNOC_GPU_AXI_CLK				38
+#define NW_GCC_MMU_1_TCU_VOTE_CLK				39
+#define NW_GCC_VIDEO_AHB_CLK					40
+#define NW_GCC_VIDEO_AXI0_CLK					41
+#define NW_GCC_VIDEO_AXI0C_CLK					42
+#define NW_GCC_VIDEO_AXI1_CLK					43
+#define NW_GCC_VIDEO_XO_CLK					44
+
+/* NW_GCC power domains */
+
+/* NW_GCC resets */
+#define NW_GCC_CAMERA_BCR					0
+#define NW_GCC_DISPLAY_0_BCR					1
+#define NW_GCC_DISPLAY_1_BCR					2
+#define NW_GCC_DPRX0_BCR					3
+#define NW_GCC_DPRX1_BCR					4
+#define NW_GCC_EVA_BCR						5
+#define NW_GCC_GPU_2_BCR					6
+#define NW_GCC_GPU_BCR						7
+#define NW_GCC_VIDEO_BCR					8
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
new file mode 100644
index 00000000000..f0f7422af69
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+
+/* SE_GCC clocks */
+#define SE_GCC_EEE_EMAC0_CLK					0
+#define SE_GCC_EEE_EMAC0_CLK_SRC				1
+#define SE_GCC_EEE_EMAC1_CLK					2
+#define SE_GCC_EEE_EMAC1_CLK_SRC				3
+#define SE_GCC_EMAC0_AXI_CLK					4
+#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK				5
+#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK				6
+#define SE_GCC_EMAC0_PHY_AUX_CLK				7
+#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC				8
+#define SE_GCC_EMAC0_PTP_CLK					9
+#define SE_GCC_EMAC0_PTP_CLK_SRC				10
+#define SE_GCC_EMAC0_RGMII_CLK					11
+#define SE_GCC_EMAC0_RGMII_CLK_SRC				12
+#define SE_GCC_EMAC0_RPCS_RX_CLK				13
+#define SE_GCC_EMAC0_RPCS_TX_CLK				14
+#define SE_GCC_EMAC0_XGXS_RX_CLK				15
+#define SE_GCC_EMAC0_XGXS_TX_CLK				16
+#define SE_GCC_EMAC1_AXI_CLK					17
+#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK				18
+#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK				19
+#define SE_GCC_EMAC1_PHY_AUX_CLK				20
+#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC				21
+#define SE_GCC_EMAC1_PTP_CLK					22
+#define SE_GCC_EMAC1_PTP_CLK_SRC				23
+#define SE_GCC_EMAC1_RGMII_CLK					24
+#define SE_GCC_EMAC1_RGMII_CLK_SRC				25
+#define SE_GCC_EMAC1_RPCS_RX_CLK				26
+#define SE_GCC_EMAC1_RPCS_TX_CLK				27
+#define SE_GCC_EMAC1_XGXS_RX_CLK				28
+#define SE_GCC_EMAC1_XGXS_TX_CLK				29
+#define SE_GCC_FRQ_MEASURE_REF_CLK				30
+#define SE_GCC_GP1_CLK						31
+#define SE_GCC_GP1_CLK_SRC					32
+#define SE_GCC_GP2_CLK						33
+#define SE_GCC_GP2_CLK_SRC					34
+#define SE_GCC_GPLL0						35
+#define SE_GCC_GPLL0_OUT_EVEN					36
+#define SE_GCC_GPLL2						37
+#define SE_GCC_GPLL4						38
+#define SE_GCC_GPLL5						39
+#define SE_GCC_MMU_2_TCU_VOTE_CLK				40
+#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK				41
+#define SE_GCC_QUPV3_WRAP0_CORE_CLK				42
+#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK				43
+#define SE_GCC_QUPV3_WRAP0_S0_CLK				44
+#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC				45
+#define SE_GCC_QUPV3_WRAP0_S1_CLK				46
+#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC				47
+#define SE_GCC_QUPV3_WRAP0_S2_CLK				48
+#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC				49
+#define SE_GCC_QUPV3_WRAP0_S3_CLK				50
+#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC				51
+#define SE_GCC_QUPV3_WRAP0_S4_CLK				52
+#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC				53
+#define SE_GCC_QUPV3_WRAP0_S5_CLK				54
+#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC				55
+#define SE_GCC_QUPV3_WRAP0_S6_CLK				56
+#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC				57
+#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK				58
+#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK				59
+#define SE_GCC_QUPV3_WRAP1_CORE_CLK				60
+#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK				61
+#define SE_GCC_QUPV3_WRAP1_S0_CLK				62
+#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC				63
+#define SE_GCC_QUPV3_WRAP1_S1_CLK				64
+#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC				65
+#define SE_GCC_QUPV3_WRAP1_S2_CLK				66
+#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC				67
+#define SE_GCC_QUPV3_WRAP1_S3_CLK				68
+#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC				69
+#define SE_GCC_QUPV3_WRAP1_S4_CLK				70
+#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC				71
+#define SE_GCC_QUPV3_WRAP1_S5_CLK				72
+#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC				73
+#define SE_GCC_QUPV3_WRAP1_S6_CLK				74
+#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC				75
+#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK				76
+
+/* SE_GCC power domains */
+#define SE_GCC_EMAC0_GDSC					0
+#define SE_GCC_EMAC1_GDSC					1
+
+/* SE_GCC resets */
+#define SE_GCC_EMAC0_BCR					0
+#define SE_GCC_EMAC1_BCR					1
+#define SE_GCC_QUPV3_WRAPPER_0_BCR				2
+#define SE_GCC_QUPV3_WRAPPER_1_BCR				3
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
new file mode 100644
index 00000000000..3f0e2ff7acc
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+
+/* TCSR_CC clocks */
+#define TCSR_DP_RX_0_CLKREF_EN					0
+#define TCSR_DP_RX_1_CLKREF_EN					1
+#define TCSR_DP_TX_0_CLKREF_EN					2
+#define TCSR_DP_TX_1_CLKREF_EN					3
+#define TCSR_DP_TX_2_CLKREF_EN					4
+#define TCSR_DP_TX_3_CLKREF_EN					5
+#define TCSR_PCIE_CLKREF_EN					6
+#define TCSR_UFS_CLKREF_EN					7
+#define TCSR_USB2_0_CLKREF_EN					8
+#define TCSR_USB2_1_CLKREF_EN					9
+#define TCSR_USB2_2_CLKREF_EN					10
+#define TCSR_USB3_0_CLKREF_EN					11
+#define TCSR_USB3_1_CLKREF_EN					12
+#define TCSR_UX_SGMII_0_CLKREF_EN				13
+#define TCSR_UX_SGMII_1_CLKREF_EN				14
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
index d1a6c45b502..ab8d312ade3 100644
--- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h
+++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
@@ -6,7 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 
-/* DISP_CC clocks */
+/* Clocks */
 #define DISP_CC_PLL0			0
 #define DISP_CC_PLL0_OUT_MAIN		1
 #define DISP_CC_MDSS_AHB_CLK		2
@@ -30,7 +30,10 @@
 #define DISP_CC_SLEEP_CLK		20
 #define DISP_CC_SLEEP_CLK_SRC		21
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+
+/* GDSCs */
 #define MDSS_GDSC			0
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
new file mode 100644
index 00000000000..e2143d905fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK						0
+#define GPU_CC_CB_CLK						1
+#define GPU_CC_CX_ACCU_SHIFT_CLK				2
+#define GPU_CC_CX_FF_CLK					3
+#define GPU_CC_CX_GMU_CLK					4
+#define GPU_CC_CXO_AON_CLK					5
+#define GPU_CC_CXO_CLK						6
+#define GPU_CC_DEMET_CLK					7
+#define GPU_CC_DPM_CLK						8
+#define GPU_CC_FF_CLK_SRC					9
+#define GPU_CC_FREQ_MEASURE_CLK					10
+#define GPU_CC_GMU_CLK_SRC					11
+#define GPU_CC_GX_ACCU_SHIFT_CLK				12
+#define GPU_CC_GX_ACD_AHB_FF_CLK				13
+#define GPU_CC_GX_AHB_FF_CLK					14
+#define GPU_CC_GX_GMU_CLK					15
+#define GPU_CC_GX_RCG_AHB_FF_CLK				16
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				17
+#define GPU_CC_HUB_AON_CLK					18
+#define GPU_CC_HUB_CLK_SRC					19
+#define GPU_CC_HUB_CX_INT_CLK					20
+#define GPU_CC_HUB_DIV_CLK_SRC					21
+#define GPU_CC_MEMNOC_GFX_CLK					22
+#define GPU_CC_PLL0						23
+#define GPU_CC_PLL0_OUT_EVEN					24
+#define GPU_CC_RSCC_HUB_AON_CLK					25
+#define GPU_CC_RSCC_XO_AON_CLK					26
+#define GPU_CC_SLEEP_CLK					27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC						0
+
+/* GPU_CC resets */
+#define GPU_CC_GPU_CC_CB_BCR					0
+#define GPU_CC_GPU_CC_CX_BCR					1
+#define GPU_CC_GPU_CC_FAST_HUB_BCR				2
+#define GPU_CC_GPU_CC_FF_BCR					3
+#define GPU_CC_GPU_CC_GMU_BCR					4
+#define GPU_CC_GPU_CC_GX_BCR					5
+#define GPU_CC_GPU_CC_XO_BCR					6
+
+#endif
diff --git a/include/dt-bindings/clock/renesas,r9a08g046-cpg.h b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h
new file mode 100644
index 00000000000..018b0a1e434
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h
@@ -0,0 +1,342 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A08G046 CPG Core Clocks */
+#define R9A08G046_CLK_I			0
+#define R9A08G046_CLK_IC0		1
+#define R9A08G046_CLK_IC1		2
+#define R9A08G046_CLK_IC2		3
+#define R9A08G046_CLK_IC3		4
+#define R9A08G046_CLK_P0		5
+#define R9A08G046_CLK_P1		6
+#define R9A08G046_CLK_P2		7
+#define R9A08G046_CLK_P3		8
+#define R9A08G046_CLK_P4		9
+#define R9A08G046_CLK_P5		10
+#define R9A08G046_CLK_P6		11
+#define R9A08G046_CLK_P7		12
+#define R9A08G046_CLK_P8		13
+#define R9A08G046_CLK_P9		14
+#define R9A08G046_CLK_P10		15
+#define R9A08G046_CLK_P13		16
+#define R9A08G046_CLK_P14		17
+#define R9A08G046_CLK_P15		18
+#define R9A08G046_CLK_P16		19
+#define R9A08G046_CLK_P17		20
+#define R9A08G046_CLK_P18		21
+#define R9A08G046_CLK_P19		22
+#define R9A08G046_CLK_P20		23
+#define R9A08G046_CLK_M0		24
+#define R9A08G046_CLK_M1		25
+#define R9A08G046_CLK_M2		26
+#define R9A08G046_CLK_M3		27
+#define R9A08G046_CLK_M4		28
+#define R9A08G046_CLK_M5		29
+#define R9A08G046_CLK_M6		30
+#define R9A08G046_CLK_AT		31
+#define R9A08G046_CLK_B			32
+#define R9A08G046_CLK_ETHTX01		33
+#define R9A08G046_CLK_ETHTX02		34
+#define R9A08G046_CLK_ETHRX01		35
+#define R9A08G046_CLK_ETHRX02		36
+#define R9A08G046_CLK_ETHRM0		37
+#define R9A08G046_CLK_ETHTX11		38
+#define R9A08G046_CLK_ETHTX12		39
+#define R9A08G046_CLK_ETHRX11		40
+#define R9A08G046_CLK_ETHRX12		41
+#define R9A08G046_CLK_ETHRM1		42
+#define R9A08G046_CLK_G			43
+#define R9A08G046_CLK_HP		44
+#define R9A08G046_CLK_SD0		45
+#define R9A08G046_CLK_SD1		46
+#define R9A08G046_CLK_SD2		47
+#define R9A08G046_CLK_SPI0		48
+#define R9A08G046_CLK_SPI1		49
+#define R9A08G046_CLK_S0		50
+#define R9A08G046_CLK_SWD		51
+#define R9A08G046_OSCCLK		52
+#define R9A08G046_OSCCLK2		53
+#define R9A08G046_MIPI_DSI_PLLCLK	54
+#define R9A08G046_USB_SCLK		55
+
+/* R9A08G046 Module Clocks */
+#define R9A08G046_CA55_SCLK		0
+#define R9A08G046_CA55_PCLK		1
+#define R9A08G046_CA55_ATCLK		2
+#define R9A08G046_CA55_GICCLK		3
+#define R9A08G046_CA55_PERICLK		4
+#define R9A08G046_CA55_ACLK		5
+#define R9A08G046_CA55_TSCLK		6
+#define R9A08G046_CA55_CORECLK0		7
+#define R9A08G046_CA55_CORECLK1		8
+#define R9A08G046_CA55_CORECLK2		9
+#define R9A08G046_CA55_CORECLK3		10
+#define R9A08G046_SRAM_ACPU_ACLK0	11
+#define R9A08G046_SRAM_ACPU_ACLK1	12
+#define R9A08G046_SRAM_ACPU_ACLK2	13
+#define R9A08G046_GIC600_GICCLK		14
+#define R9A08G046_IA55_CLK		15
+#define R9A08G046_IA55_PCLK		16
+#define R9A08G046_MHU_PCLK		17
+#define R9A08G046_SYC_CNT_CLK		18
+#define R9A08G046_DMAC_ACLK		19
+#define R9A08G046_DMAC_PCLK		20
+#define R9A08G046_OSTM0_PCLK		21
+#define R9A08G046_OSTM1_PCLK		22
+#define R9A08G046_OSTM2_PCLK		23
+#define R9A08G046_MTU_X_MCK_MTU3	24
+#define R9A08G046_POE3_CLKM_POE		25
+#define R9A08G046_GPT_PCLK		26
+#define R9A08G046_POEG_A_CLKP		27
+#define R9A08G046_POEG_B_CLKP		28
+#define R9A08G046_POEG_C_CLKP		29
+#define R9A08G046_POEG_D_CLKP		30
+#define R9A08G046_WDT0_PCLK		31
+#define R9A08G046_WDT0_CLK		32
+#define R9A08G046_WDT1_PCLK		33
+#define R9A08G046_WDT1_CLK		34
+#define R9A08G046_WDT2_PCLK		35
+#define R9A08G046_WDT2_CLK		36
+#define R9A08G046_XSPI_HCLK		37
+#define R9A08G046_XSPI_ACLK		38
+#define R9A08G046_XSPI_CLK		39
+#define R9A08G046_XSPI_CLKX2		40
+#define R9A08G046_SDHI0_IMCLK		41
+#define R9A08G046_SDHI0_IMCLK2		42
+#define R9A08G046_SDHI0_CLK_HS		43
+#define R9A08G046_SDHI0_IACLKS		44
+#define R9A08G046_SDHI0_IACLKM		45
+#define R9A08G046_SDHI1_IMCLK		46
+#define R9A08G046_SDHI1_IMCLK2		47
+#define R9A08G046_SDHI1_CLK_HS		48
+#define R9A08G046_SDHI1_IACLKS		49
+#define R9A08G046_SDHI1_IACLKM		50
+#define R9A08G046_SDHI2_IMCLK		51
+#define R9A08G046_SDHI2_IMCLK2		52
+#define R9A08G046_SDHI2_CLK_HS		53
+#define R9A08G046_SDHI2_IACLKS		54
+#define R9A08G046_SDHI2_IACLKM		55
+#define R9A08G046_GE3D_CLK		56
+#define R9A08G046_GE3D_AXI_CLK		57
+#define R9A08G046_GE3D_ACE_CLK		58
+#define R9A08G046_ISU_ACLK		59
+#define R9A08G046_ISU_PCLK		60
+#define R9A08G046_H264_CLK_A		61
+#define R9A08G046_H264_CLK_P		62
+#define R9A08G046_CRU_SYSCLK		63
+#define R9A08G046_CRU_VCLK		64
+#define R9A08G046_CRU_PCLK		65
+#define R9A08G046_CRU_ACLK		66
+#define R9A08G046_MIPI_DSI_SYSCLK	67
+#define R9A08G046_MIPI_DSI_ACLK		68
+#define R9A08G046_MIPI_DSI_PCLK		69
+#define R9A08G046_MIPI_DSI_VCLK		70
+#define R9A08G046_MIPI_DSI_LPCLK	71
+#define R9A08G046_LVDS_PLLCLK		72
+#define R9A08G046_LVDS_CLK_DOT0		73
+#define R9A08G046_LCDC_CLK_A		74
+#define R9A08G046_LCDC_CLK_D		75
+#define R9A08G046_LCDC_CLK_P		76
+#define R9A08G046_SSI0_PCLK2		77
+#define R9A08G046_SSI0_PCLK_SFR		78
+#define R9A08G046_SSI1_PCLK2		79
+#define R9A08G046_SSI1_PCLK_SFR		80
+#define R9A08G046_SSI2_PCLK2		81
+#define R9A08G046_SSI2_PCLK_SFR		82
+#define R9A08G046_SSI3_PCLK2		83
+#define R9A08G046_SSI3_PCLK_SFR		84
+#define R9A08G046_USB_U2H0_HCLK		85
+#define R9A08G046_USB_U2H1_HCLK		86
+#define R9A08G046_USB_U2P0_EXR_CPUCLK	87
+#define R9A08G046_USB_U2P1_EXR_CPUCLK	88
+#define R9A08G046_USB_PCLK		89
+#define R9A08G046_ETH0_CLK_AXI		90
+#define R9A08G046_ETH0_CLK_CHI		91
+#define R9A08G046_ETH0_CLK_TX_I		92
+#define R9A08G046_ETH0_CLK_RX_I		93
+#define R9A08G046_ETH0_CLK_TX_180_I	94
+#define R9A08G046_ETH0_CLK_RX_180_I	95
+#define R9A08G046_ETH0_CLK_RMII_I	96
+#define R9A08G046_ETH0_CLK_PTP_REF_I	97
+#define R9A08G046_ETH0_CLK_TX_I_RMII	98
+#define R9A08G046_ETH0_CLK_RX_I_RMII	99
+#define R9A08G046_ETH1_CLK_AXI		100
+#define R9A08G046_ETH1_CLK_CHI		101
+#define R9A08G046_ETH1_CLK_TX_I		102
+#define R9A08G046_ETH1_CLK_RX_I		103
+#define R9A08G046_ETH1_CLK_TX_180_I	104
+#define R9A08G046_ETH1_CLK_RX_180_I	105
+#define R9A08G046_ETH1_CLK_RMII_I	106
+#define R9A08G046_ETH1_CLK_PTP_REF_I	107
+#define R9A08G046_ETH1_CLK_TX_I_RMII	108
+#define R9A08G046_ETH1_CLK_RX_I_RMII	109
+#define R9A08G046_I2C0_PCLK		110
+#define R9A08G046_I2C1_PCLK		111
+#define R9A08G046_I2C2_PCLK		112
+#define R9A08G046_I2C3_PCLK		113
+#define R9A08G046_SCIF0_CLK_PCK		114
+#define R9A08G046_SCIF1_CLK_PCK		115
+#define R9A08G046_SCIF2_CLK_PCK		116
+#define R9A08G046_SCIF3_CLK_PCK		117
+#define R9A08G046_SCIF4_CLK_PCK		118
+#define R9A08G046_SCIF5_CLK_PCK		119
+#define R9A08G046_RSCI0_PCLK		120
+#define R9A08G046_RSCI0_TCLK		121
+#define R9A08G046_RSCI1_PCLK		122
+#define R9A08G046_RSCI1_TCLK		123
+#define R9A08G046_RSCI2_PCLK		124
+#define R9A08G046_RSCI2_TCLK		125
+#define R9A08G046_RSCI3_PCLK		126
+#define R9A08G046_RSCI3_TCLK		127
+#define R9A08G046_RSPI0_PCLK		128
+#define R9A08G046_RSPI0_TCLK		129
+#define R9A08G046_RSPI1_PCLK		130
+#define R9A08G046_RSPI1_TCLK		131
+#define R9A08G046_RSPI2_PCLK		132
+#define R9A08G046_RSPI2_TCLK		133
+#define R9A08G046_CANFD_PCLK		134
+#define R9A08G046_CANFD_CLK_RAM		135
+#define R9A08G046_GPIO_HCLK		136
+#define R9A08G046_ADC0_ADCLK		137
+#define R9A08G046_ADC0_PCLK		138
+#define R9A08G046_ADC1_ADCLK		139
+#define R9A08G046_ADC1_PCLK		140
+#define R9A08G046_TSU_PCLK		141
+#define R9A08G046_PDM_PCLK		142
+#define R9A08G046_PDM_CCLK		143
+#define R9A08G046_PCI_ACLK		144
+#define R9A08G046_PCI_CLKL1PM		145
+#define R9A08G046_PCI_CLK_PMU		146
+#define R9A08G046_SPDIF_PCLK		147
+#define R9A08G046_I3C_TCLK		148
+#define R9A08G046_I3C_PCLK		149
+#define R9A08G046_VBAT_BCLK		150
+#define R9A08G046_BSC_X_BCK_BSC		151
+
+/* R9A08G046 Resets */
+#define R9A08G046_CA55_RST0_0		0
+#define R9A08G046_CA55_RST0_1		1
+#define R9A08G046_CA55_RST0_2		2
+#define R9A08G046_CA55_RST0_3		3
+#define R9A08G046_CA55_RST4_0		4
+#define R9A08G046_CA55_RST4_1		5
+#define R9A08G046_CA55_RST4_2		6
+#define R9A08G046_CA55_RST4_3		7
+#define R9A08G046_CA55_RST8		8
+#define R9A08G046_CA55_RST9		9
+#define R9A08G046_CA55_RST10		10
+#define R9A08G046_CA55_RST11		11
+#define R9A08G046_CA55_RST12		12
+#define R9A08G046_CA55_RST13		13
+#define R9A08G046_CA55_RST14		14
+#define R9A08G046_CA55_RST15		15
+#define R9A08G046_CA55_RST16		16
+#define R9A08G046_SRAM_ACPU_ARESETN0	17
+#define R9A08G046_SRAM_ACPU_ARESETN1	18
+#define R9A08G046_SRAM_ACPU_ARESETN2	19
+#define R9A08G046_GIC600_GICRESET_N	20
+#define R9A08G046_GIC600_DBG_GICRESET_N	21
+#define R9A08G046_IA55_RESETN		22
+#define R9A08G046_MHU_RESETN		23
+#define R9A08G046_SYC_RESETN		24
+#define R9A08G046_DMAC_ARESETN		25
+#define R9A08G046_DMAC_RST_ASYNC	26
+#define R9A08G046_GTM0_PRESETZ		27
+#define R9A08G046_GTM1_PRESETZ		28
+#define R9A08G046_GTM2_PRESETZ		29
+#define R9A08G046_MTU_X_PRESET_MTU3	30
+#define R9A08G046_POE3_RST_M_REG	31
+#define R9A08G046_GPT_RST_C		32
+#define R9A08G046_POEG_A_RST		33
+#define R9A08G046_POEG_B_RST		34
+#define R9A08G046_POEG_C_RST		35
+#define R9A08G046_POEG_D_RST		36
+#define R9A08G046_WDT0_PRESETN		37
+#define R9A08G046_WDT1_PRESETN		38
+#define R9A08G046_WDT2_PRESETN		39
+#define R9A08G046_XSPI_HRESETN		40
+#define R9A08G046_XSPI_ARESETN		41
+#define R9A08G046_SDHI0_IXRST		42
+#define R9A08G046_SDHI1_IXRST		43
+#define R9A08G046_SDHI2_IXRST		44
+#define R9A08G046_SDHI0_IXRSTAXIM	45
+#define R9A08G046_SDHI0_IXRSTAXIS	46
+#define R9A08G046_SDHI1_IXRSTAXIM	47
+#define R9A08G046_SDHI1_IXRSTAXIS	48
+#define R9A08G046_SDHI2_IXRSTAXIM	49
+#define R9A08G046_SDHI2_IXRSTAXIS	50
+#define R9A08G046_GE3D_RESETN		51
+#define R9A08G046_GE3D_AXI_RESETN	52
+#define R9A08G046_GE3D_ACE_RESETN	53
+#define R9A08G046_ISU_ARESETN		54
+#define R9A08G046_ISU_PRESETN		55
+#define R9A08G046_H264_X_RESET_VCP	56
+#define R9A08G046_H264_CP_PRESET_P	57
+#define R9A08G046_CRU_CMN_RSTB		58
+#define R9A08G046_CRU_PRESETN		59
+#define R9A08G046_CRU_ARESETN		60
+#define R9A08G046_MIPI_DSI_CMN_RSTB	61
+#define R9A08G046_MIPI_DSI_ARESET_N	62
+#define R9A08G046_MIPI_DSI_PRESET_N	63
+#define R9A08G046_LCDC_RESET_N		64
+#define R9A08G046_SSI0_RST_M2_REG	65
+#define R9A08G046_SSI1_RST_M2_REG	66
+#define R9A08G046_SSI2_RST_M2_REG	67
+#define R9A08G046_SSI3_RST_M2_REG	68
+#define R9A08G046_USB_U2H0_HRESETN	69
+#define R9A08G046_USB_U2H1_HRESETN	70
+#define R9A08G046_USB_U2P0_EXL_SYSRST	71
+#define R9A08G046_USB_PRESETN		72
+#define R9A08G046_USB_U2P1_EXL_SYSRST	73
+#define R9A08G046_ETH0_ARESET_N		74
+#define R9A08G046_ETH1_ARESET_N		75
+#define R9A08G046_I2C0_MRST		76
+#define R9A08G046_I2C1_MRST		77
+#define R9A08G046_I2C2_MRST		78
+#define R9A08G046_I2C3_MRST		79
+#define R9A08G046_SCIF0_RST_SYSTEM_N	80
+#define R9A08G046_SCIF1_RST_SYSTEM_N	81
+#define R9A08G046_SCIF2_RST_SYSTEM_N	82
+#define R9A08G046_SCIF3_RST_SYSTEM_N	83
+#define R9A08G046_SCIF4_RST_SYSTEM_N	84
+#define R9A08G046_SCIF5_RST_SYSTEM_N	85
+#define R9A08G046_RSPI0_PRESETN		86
+#define R9A08G046_RSPI1_PRESETN		87
+#define R9A08G046_RSPI2_PRESETN		88
+#define R9A08G046_RSPI0_TRESETN		89
+#define R9A08G046_RSPI1_TRESETN		90
+#define R9A08G046_RSPI2_TRESETN		91
+#define R9A08G046_CANFD_RSTP_N		92
+#define R9A08G046_CANFD_RSTC_N		93
+#define R9A08G046_GPIO_RSTN		94
+#define R9A08G046_GPIO_PORT_RESETN	95
+#define R9A08G046_GPIO_SPARE_RESETN	96
+#define R9A08G046_ADC0_PRESETN		97
+#define R9A08G046_ADC0_ADRST_N		98
+#define R9A08G046_ADC1_PRESETN		99
+#define R9A08G046_ADC1_ADRST_N		100
+#define R9A08G046_TSU_PRESETN		101
+#define R9A08G046_PDM_PRESETN		102
+#define R9A08G046_PCI_ARESETN		103
+#define R9A08G046_SPDIF_RST		104
+#define R9A08G046_I3C_TRESETN		105
+#define R9A08G046_I3C_PRESETN		106
+#define R9A08G046_VBAT_BRESETN		107
+#define R9A08G046_RSCI0_PRESETN		108
+#define R9A08G046_RSCI1_PRESETN		109
+#define R9A08G046_RSCI2_PRESETN		110
+#define R9A08G046_RSCI3_PRESETN		111
+#define R9A08G046_RSCI0_TRESETN		112
+#define R9A08G046_RSCI1_TRESETN		113
+#define R9A08G046_RSCI2_TRESETN		114
+#define R9A08G046_RSCI3_TRESETN		115
+#define R9A08G046_LVDS_RESET_N		116
+#define R9A08G046_BSC_X_PRESET_BSC	117
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */
diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
new file mode 100644
index 00000000000..35afdee7e96
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h
@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
+
+#define PLL_GPLL		0
+#define ARMCLK			1
+#define PLL_DPLL		2
+#define XIN_OSC0_HALF		3
+#define CLK_GPLL_DIV24		4
+#define CLK_GPLL_DIV12		5
+#define CLK_GPLL_DIV6		6
+#define CLK_GPLL_DIV4		7
+#define CLK_GPLL_DIV3		8
+#define CLK_GPLL_DIV2P5		9
+#define CLK_GPLL_DIV2		10
+#define CLK_UART0_SRC		11
+#define CLK_UART1_SRC		12
+#define CLK_UART2_SRC		13
+#define CLK_UART0_FRAC		14
+#define CLK_UART1_FRAC		15
+#define CLK_UART2_FRAC		16
+#define CLK_SAI_SRC		17
+#define CLK_SAI_FRAC		18
+#define LSCLK_NPU_SRC		19
+#define CLK_NPU_SRC		20
+#define ACLK_VEPU_SRC		21
+#define CLK_VEPU_SRC		22
+#define ACLK_VI_SRC		23
+#define CLK_ISP_SRC		24
+#define DCLK_VICAP		25
+#define CCLK_EMMC		26
+#define CCLK_SDMMC0		27
+#define SCLK_SFC_2X		28
+#define LSCLK_PERI_SRC		29
+#define ACLK_PERI_SRC		30
+#define HCLK_HPMCU		31
+#define SCLK_UART0		32
+#define SCLK_UART1		33
+#define SCLK_UART2		34
+#define CLK_I2C_PMU		35
+#define CLK_I2C_PERI		36
+#define CLK_SPI0		37
+#define CLK_PWM0_SRC		38
+#define CLK_PWM1		39
+#define CLK_PWM2		40
+#define DCLK_DECOM_SRC		41
+#define CCLK_SDMMC1		42
+#define CLK_CORE_CRYPTO		43
+#define CLK_PKA_CRYPTO		44
+#define CLK_CORE_RGA		45
+#define MCLK_SAI_SRC		46
+#define CLK_FREQ_PWM0_SRC	47
+#define CLK_COUNTER_PWM0_SRC	48
+#define PCLK_TOP_ROOT		49
+#define CLK_REF_MIPI0		50
+#define CLK_MIPI0_OUT2IO	51
+#define CLK_REF_MIPI1		52
+#define CLK_MIPI1_OUT2IO	53
+#define MCLK_SAI_OUT2IO		54
+#define ACLK_NPU_ROOT		55
+#define HCLK_RKNN		56
+#define ACLK_RKNN		57
+#define LSCLK_VEPU_ROOT		58
+#define HCLK_VEPU		59
+#define ACLK_VEPU		60
+#define CLK_CORE_VEPU		61
+#define PCLK_IOC_VCCIO3		62
+#define PCLK_ACODEC		63
+#define PCLK_USBPHY		64
+#define LSCLK_VI_100M		65
+#define LSCLK_VI_ROOT		66
+#define HCLK_ISP		67
+#define ACLK_ISP		68
+#define CLK_CORE_ISP		69
+#define ACLK_VICAP		70
+#define HCLK_VICAP		71
+#define ISP0CLK_VICAP		72
+#define PCLK_CSI2HOST0		73
+#define PCLK_CSI2HOST1		74
+#define HCLK_EMMC		75
+#define HCLK_SFC		76
+#define HCLK_SFC_XIP		77
+#define HCLK_SDMMC0		78
+#define PCLK_CSIPHY		79
+#define PCLK_GPIO1		80
+#define DBCLK_GPIO1		81
+#define PCLK_IOC_VCCIO47	82
+#define LSCLK_DDR_ROOT		83
+#define CLK_TIMER_DDRMON	84
+#define LSCLK_PMU_ROOT		85
+#define PCLK_PMU		86
+#define XIN_RC_DIV		87
+#define CLK_32K			88
+#define PCLK_PMU_GPIO0		89
+#define DBCLK_PMU_GPIO0		90
+#define CLK_DDR_FAIL_SAFE	91
+#define PCLK_PMU_HP_TIMER	92
+#define CLK_PMU_32K_HP_TIMER	93
+#define PCLK_PWM0		94
+#define CLK_PWM0		95
+#define CLK_OSC_PWM0		96
+#define CLK_RC_PWM0		97
+#define CLK_FREQ_PWM0		98
+#define CLK_COUNTER_PWM0	99
+#define PCLK_I2C0		100
+#define CLK_I2C0		101
+#define PCLK_UART0		102
+#define PCLK_IOC_PMUIO0		103
+#define CLK_REFOUT		104
+#define CLK_PREROLL		105
+#define CLK_PREROLL_32K		106
+#define CLK_LPMCU_PMU		107
+#define PCLK_SPI2AHB		108
+#define HCLK_SPI2AHB		109
+#define SCLK_SPI2AHB		110
+#define PCLK_WDT_LPMCU		111
+#define TCLK_WDT_LPMCU		112
+#define HCLK_SFC_PMU1		113
+#define HCLK_SFC_XIP_PMU1	114
+#define SCLK_SFC_2X_PMU1	115
+#define CLK_LPMCU		116
+#define CLK_LPMCU_RTC		117
+#define PCLK_LPMCU_MAILBOX	118
+#define PCLK_IOC_PMUIO1		119
+#define PCLK_CRU_PMU1		120
+#define PCLK_PERI_ROOT		121
+#define PCLK_RTC_ROOT		122
+#define CLK_TIMER_ROOT		123
+#define PCLK_TIMER		124
+#define CLK_TIMER0		125
+#define CLK_TIMER1		126
+#define CLK_TIMER2		127
+#define CLK_TIMER3		128
+#define CLK_TIMER4		129
+#define CLK_TIMER5		130
+#define PCLK_STIMER		131
+#define CLK_STIMER0		132
+#define CLK_STIMER1		133
+#define PCLK_WDT_NS		134
+#define TCLK_WDT_NS		135
+#define PCLK_WDT_S		136
+#define TCLK_WDT_S		137
+#define PCLK_WDT_HPMCU		138
+#define TCLK_WDT_HPMCU		139
+#define PCLK_I2C1		140
+#define CLK_I2C1		141
+#define PCLK_I2C2		142
+#define CLK_I2C2		143
+#define PCLK_I2C3		144
+#define CLK_I2C3		145
+#define PCLK_I2C4		146
+#define CLK_I2C4		147
+#define PCLK_SPI0		148
+#define PCLK_PWM1		149
+#define CLK_OSC_PWM1		150
+#define PCLK_PWM2		151
+#define CLK_OSC_PWM2		152
+#define PCLK_UART2		153
+#define PCLK_UART1		154
+#define ACLK_RKDMA		155
+#define PCLK_TSADC		156
+#define CLK_TSADC		157
+#define CLK_TSADC_TSEN		158
+#define PCLK_SARADC		159
+#define CLK_SARADC		160
+#define PCLK_GPIO2		161
+#define DBCLK_GPIO2		162
+#define PCLK_IOC_VCCIO6		163
+#define ACLK_USBOTG		164
+#define CLK_REF_USBOTG		165
+#define HCLK_SDMMC1		166
+#define HCLK_SAI		167
+#define MCLK_SAI		168
+#define ACLK_CRYPTO		169
+#define HCLK_CRYPTO		170
+#define HCLK_RK_RNG_NS		171
+#define HCLK_RK_RNG_S		172
+#define PCLK_OTPC_NS		173
+#define CLK_OTPC_ROOT_NS	174
+#define CLK_SBPI_OTPC_NS	175
+#define CLK_USER_OTPC_NS	176
+#define PCLK_OTPC_S		177
+#define CLK_OTPC_ROOT_S		178
+#define CLK_SBPI_OTPC_S		179
+#define CLK_USER_OTPC_S		180
+#define CLK_OTPC_ARB		181
+#define PCLK_OTP_MASK		182
+#define HCLK_RGA		183
+#define ACLK_RGA		184
+#define ACLK_MAC		185
+#define PCLK_MAC		186
+#define CLK_MACPHY		187
+#define ACLK_SPINLOCK		188
+#define HCLK_CACHE		189
+#define PCLK_HPMCU_MAILBOX	190
+#define PCLK_HPMCU_INTMUX	191
+#define CLK_HPMCU		192
+#define CLK_HPMCU_RTC		193
+#define DCLK_DECOM		194
+#define ACLK_DECOM		195
+#define PCLK_DECOM		196
+#define ACLK_SYS_SRAM		197
+#define PCLK_DMA2DDR		198
+#define ACLK_DMA2DDR		199
+#define PCLK_DCF		200
+#define ACLK_DCF		201
+#define MCLK_ACODEC_TX		202
+#define SCLK_UART0_SRC		203
+#define SCLK_UART1_SRC		204
+#define SCLK_UART2_SRC		205
+#define XIN_RC_SRC		206
+#define CLK_UTMI_USBOTG		207
+#define CLK_REF_USBPHY		208
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 06dec27a8c7..f2628c220b2 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -309,4 +309,10 @@
 #define CLK_MOUT_MFD_NOC_USER           1
 #define CLK_DOUT_MFD_NOCP               2
 
+/* CMU_G3D */
+#define FOUT_PLL_G3D                    1
+#define CLK_MOUT_G3D_NOC                2
+#define CLK_MOUT_G3D_SWITCH_USER        3
+#define CLK_MOUT_G3D_NOCP_USER          4
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h b/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
new file mode 100644
index 00000000000..c1c875e016f
--- /dev/null
+++ b/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Tenstorrent Atlantis PRCM Clock and Reset Indices
+ *
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#ifndef _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
+#define _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
+
+/*
+ * RCPU Domain Clock IDs
+ */
+#define CLK_RCPU_PLL		0
+#define CLK_RCPU_ROOT		1
+#define CLK_RCPU_DIV2		2
+#define CLK_RCPU_DIV4		3
+#define CLK_RCPU_RTC		4
+#define CLK_SMNDMA0_ACLK	5
+#define CLK_SMNDMA1_ACLK	6
+#define CLK_WDT0_PCLK		7
+#define CLK_WDT1_PCLK		8
+#define CLK_TIMER_PCLK		9
+#define CLK_PVTC_PCLK		10
+#define CLK_PMU_PCLK		11
+#define CLK_MAILBOX_HCLK	12
+#define CLK_SEC_SPACC_HCLK	13
+#define CLK_SEC_OTP_HCLK	14
+#define CLK_TRNG_PCLK		15
+#define CLK_SEC_CRC_HCLK	16
+#define CLK_SMN_HCLK		17
+#define CLK_AHB0_HCLK		18
+#define CLK_SMN_PCLK		19
+#define CLK_SMN_CLK		20
+#define CLK_SCRATCHPAD_CLK	21
+#define CLK_RCPU_CORE_CLK	22
+#define CLK_RCPU_ROM_CLK	23
+#define CLK_OTP_LOAD_CLK	24
+#define CLK_NOC_PLL		25
+#define CLK_NOCC_CLK		26
+#define CLK_NOCC_DIV2		27
+#define CLK_NOCC_DIV4		28
+#define CLK_NOCC_RTC		29
+#define CLK_NOCC_CAN		30
+#define CLK_QSPI_SCLK		31
+#define CLK_QSPI_HCLK		32
+#define CLK_I2C0_PCLK		33
+#define CLK_I2C1_PCLK		34
+#define CLK_I2C2_PCLK		35
+#define CLK_I2C3_PCLK		36
+#define CLK_I2C4_PCLK		37
+#define CLK_UART0_PCLK		38
+#define CLK_UART1_PCLK		39
+#define CLK_UART2_PCLK		40
+#define CLK_UART3_PCLK		41
+#define CLK_UART4_PCLK		42
+#define CLK_SPI0_PCLK		43
+#define CLK_SPI1_PCLK		44
+#define CLK_SPI2_PCLK		45
+#define CLK_SPI3_PCLK		46
+#define CLK_GPIO_PCLK		47
+#define CLK_CAN0_HCLK		48
+#define CLK_CAN0_CLK		49
+#define CLK_CAN1_HCLK		50
+#define CLK_CAN1_CLK		51
+#define CLK_CAN0_TIMER_CLK	52
+#define CLK_CAN1_TIMER_CLK	53
+
+/* RCPU domain reset */
+#define RST_SMNDMA0		0
+#define RST_SMNDMA1		1
+#define RST_WDT0		2
+#define RST_WDT1		3
+#define RST_TMR			4
+#define RST_PVTC		5
+#define RST_PMU			6
+#define RST_MAILBOX		7
+#define RST_SPACC		8
+#define RST_OTP			9
+#define RST_TRNG		10
+#define RST_CRC			11
+#define RST_QSPI		12
+#define RST_I2C0		13
+#define RST_I2C1		14
+#define RST_I2C2		15
+#define RST_I2C3		16
+#define RST_I2C4		17
+#define RST_UART0		18
+#define RST_UART1		19
+#define RST_UART2		20
+#define RST_UART3		21
+#define RST_UART4		22
+#define RST_SPI0		23
+#define RST_SPI1		24
+#define RST_SPI2		25
+#define RST_SPI3		26
+#define RST_GPIO		27
+#define RST_CAN0		28
+#define RST_CAN1		29
+#define RST_I2S0		30
+#define RST_I2S1		31
+
+#endif /* _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 373644e4674..5d94bd561a2 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -197,6 +197,10 @@
 #define VF610_CLK_TCON1			188
 #define VF610_CLK_CAAM			189
 #define VF610_CLK_CRC			190
-#define VF610_CLK_END			191
+#define VF610_CLK_ESW			191
+#define VF610_CLK_ESW_MAC_TAB0		192
+#define VF610_CLK_ESW_MAC_TAB1		193
+#define VF610_CLK_ESW_MAC_TAB2		194
+#define VF610_CLK_ESW_MAC_TAB3		195
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/interconnect/qcom,eliza-rpmh.h b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h
new file mode 100644
index 00000000000..95db2fe647d
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H
+
+#define MASTER_QSPI_0				0
+#define MASTER_QUP_1				1
+#define MASTER_UFS_MEM				2
+#define MASTER_USB3_0				3
+#define SLAVE_A1NOC_SNOC			4
+
+#define MASTER_QUP_2				0
+#define MASTER_CRYPTO				1
+#define MASTER_IPA				2
+#define MASTER_SOCCP_AGGR_NOC			3
+#define MASTER_QDSS_ETR				4
+#define MASTER_QDSS_ETR_1			5
+#define MASTER_SDCC_1				6
+#define MASTER_SDCC_2				7
+#define SLAVE_A2NOC_SNOC			8
+
+#define MASTER_QUP_CORE_1			0
+#define MASTER_QUP_CORE_2			1
+#define SLAVE_QUP_CORE_1			2
+#define SLAVE_QUP_CORE_2			3
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_CRYPTO_0_CFG			5
+#define SLAVE_DISPLAY_CFG			6
+#define SLAVE_GFX3D_CFG				7
+#define SLAVE_I3C_IBI0_CFG			8
+#define SLAVE_I3C_IBI1_CFG			9
+#define SLAVE_IMEM_CFG				10
+#define SLAVE_CNOC_MSS				11
+#define SLAVE_PCIE_0_CFG			12
+#define SLAVE_PRNG				13
+#define SLAVE_QDSS_CFG				14
+#define SLAVE_QSPI_0				15
+#define SLAVE_QUP_1				16
+#define SLAVE_QUP_2				17
+#define SLAVE_SDCC_2				18
+#define SLAVE_TCSR				19
+#define SLAVE_TLMM				20
+#define SLAVE_UFS_MEM_CFG			21
+#define SLAVE_USB3_0				22
+#define SLAVE_VENUS_CFG				23
+#define SLAVE_VSENSE_CTRL_CFG			24
+#define SLAVE_CNOC_MNOC_HF_CFG			25
+#define SLAVE_CNOC_MNOC_SF_CFG			26
+#define SLAVE_PCIE_ANOC_CFG			27
+#define SLAVE_QDSS_STM				28
+#define SLAVE_TCU				29
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_IPA_CFG				3
+#define SLAVE_IPC_ROUTER_CFG			4
+#define SLAVE_SOCCP				5
+#define SLAVE_TME_CFG				6
+#define SLAVE_APPSS				7
+#define SLAVE_CNOC_CFG				8
+#define SLAVE_DDRSS_CFG				9
+#define SLAVE_BOOT_IMEM				10
+#define SLAVE_IMEM				11
+#define SLAVE_BOOT_IMEM_2			12
+#define SLAVE_SERVICE_CNOC			13
+#define SLAVE_PCIE_0				14
+#define SLAVE_PCIE_1				15
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_LPASS_GEM_NOC			4
+#define MASTER_MSS_PROC				5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_SNOC_SF_MEM_NOC			10
+#define MASTER_WLAN_Q6				11
+#define MASTER_GIC				12
+#define SLAVE_GEM_NOC_CNOC			13
+#define SLAVE_LLCC				14
+#define SLAVE_MEM_NOC_PCIE_SNOC			15
+
+#define MASTER_LPIAON_NOC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LPASS_LPINOC			0
+#define SLAVE_LPIAON_NOC_LPASS_AG_NOC		1
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPICX_NOC_LPIAON_NOC		1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_NRT_ICP_SF		0
+#define MASTER_CAMNOC_RT_CDM_SF			1
+#define MASTER_CAMNOC_SF			2
+#define MASTER_VIDEO_MVP			3
+#define MASTER_VIDEO_V_PROC			4
+#define MASTER_CNOC_MNOC_SF_CFG			5
+#define MASTER_CAMNOC_HF			6
+#define MASTER_MDP				7
+#define MASTER_CNOC_MNOC_HF_CFG			8
+#define SLAVE_MNOC_SF_MEM_NOC			9
+#define SLAVE_SERVICE_MNOC_SF			10
+#define SLAVE_MNOC_HF_MEM_NOC			11
+#define SLAVE_SERVICE_MNOC_HF			12
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define MASTER_PCIE_1				2
+#define SLAVE_ANOC_PCIE_GEM_NOC			3
+#define SLAVE_SERVICE_PCIE_ANOC			4
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define MASTER_CNOC_SNOC			2
+#define MASTER_NSINOC_SNOC			3
+#define SLAVE_SNOC_GEM_NOC_SF			4
+
+#endif
diff --git a/include/dt-bindings/power/allwinner,sun60i-a733-pck-600.h b/include/dt-bindings/power/allwinner,sun60i-a733-pck-600.h
new file mode 100644
index 00000000000..cf476a005b5
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun60i-a733-pck-600.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_
+#define _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_
+
+#define PD_VI			0
+#define PD_DE_SYS		1
+#define PD_VE_DEC		2
+#define PD_VE_ENC		3
+#define PD_NPU			4
+#define PD_GPU_TOP		5
+#define PD_GPU_CORE		6
+#define PD_PCIE			7
+#define PD_USB2			8
+#define PD_VO			9
+#define PD_VO1			10
+
+#endif /* _DT_BINDINGS_POWER_SUN60I_A733_PCK600_H_ */
diff --git a/include/dt-bindings/power/marvell,pxa1908-power.h b/include/dt-bindings/power/marvell,pxa1908-power.h
index 19b088351af..173f47e0e69 100644
--- a/include/dt-bindings/power/marvell,pxa1908-power.h
+++ b/include/dt-bindings/power/marvell,pxa1908-power.h
@@ -13,5 +13,6 @@
 #define PXA1908_POWER_DOMAIN_GPU2D	2
 #define PXA1908_POWER_DOMAIN_DSI	3
 #define PXA1908_POWER_DOMAIN_ISP	4
+#define PXA1908_POWER_DOMAIN_AUDIO	5
 
 #endif
diff --git a/include/dt-bindings/power/mediatek,mt8189-power.h b/include/dt-bindings/power/mediatek,mt8189-power.h
new file mode 100644
index 00000000000..70a8c211345
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8189-power.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Qiqi Wang <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
+#define _DT_BINDINGS_POWER_MT8189_POWER_H
+
+/* SPM */
+#define MT8189_POWER_DOMAIN_CONN			0
+#define MT8189_POWER_DOMAIN_AUDIO			1
+#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT		2
+#define MT8189_POWER_DOMAIN_ADSP_INFRA			3
+#define MT8189_POWER_DOMAIN_ADSP_AO			4
+#define MT8189_POWER_DOMAIN_MM_INFRA			5
+#define MT8189_POWER_DOMAIN_ISP_IMG1			6
+#define MT8189_POWER_DOMAIN_ISP_IMG2			7
+#define MT8189_POWER_DOMAIN_ISP_IPE			8
+#define MT8189_POWER_DOMAIN_VDE0			9
+#define MT8189_POWER_DOMAIN_VEN0			10
+#define MT8189_POWER_DOMAIN_CAM_MAIN			11
+#define MT8189_POWER_DOMAIN_CAM_SUBA			12
+#define MT8189_POWER_DOMAIN_CAM_SUBB			13
+#define MT8189_POWER_DOMAIN_MDP0			14
+#define MT8189_POWER_DOMAIN_DISP			15
+#define MT8189_POWER_DOMAIN_DP_TX			16
+#define MT8189_POWER_DOMAIN_CSI_RX			17
+#define MT8189_POWER_DOMAIN_SSUSB			18
+#define MT8189_POWER_DOMAIN_MFG0			19
+#define MT8189_POWER_DOMAIN_MFG1			20
+#define MT8189_POWER_DOMAIN_MFG2			21
+#define MT8189_POWER_DOMAIN_MFG3			22
+#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT		23
+#define MT8189_POWER_DOMAIN_PCIE			24
+#define MT8189_POWER_DOMAIN_PCIE_PHY			25
+
+#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */
diff --git a/include/dt-bindings/power/mt7622-power.h b/include/dt-bindings/power/mt7622-power.h
index ffad81ad3d4..ec244989eeb 100644
--- a/include/dt-bindings/power/mt7622-power.h
+++ b/include/dt-bindings/power/mt7622-power.h
@@ -10,5 +10,6 @@
 #define MT7622_POWER_DOMAIN_HIF0	1
 #define MT7622_POWER_DOMAIN_HIF1	2
 #define MT7622_POWER_DOMAIN_WB		3
+#define MT7622_POWER_DOMAIN_AUDIO	4
 
 #endif /* _DT_BINDINGS_POWER_MT7622_POWER_H */
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 06851363ae0..67e2634fdc9 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -28,15 +28,20 @@
 #define RPMHPD_XO               18
 #define RPMHPD_NSP2             19
 #define RPMHPD_GMXC		20
+#define RPMHPD_DCX		21
+#define RPMHPD_GBX		22
 
 /* RPMh Power Domain performance levels */
 #define RPMH_REGULATOR_LEVEL_RETENTION		16
 #define RPMH_REGULATOR_LEVEL_MIN_SVS		48
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D3_0	49
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D3		50
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1	51
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D2		52
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1	54
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1_0	55
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1		56
+#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0_0	59
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D0		60
 #define RPMH_REGULATOR_LEVEL_LOW_SVS		64
 #define RPMH_REGULATOR_LEVEL_LOW_SVS_P1		72
@@ -47,6 +52,7 @@
 #define RPMH_REGULATOR_LEVEL_SVS_L0		144
 #define RPMH_REGULATOR_LEVEL_SVS_L1		192
 #define RPMH_REGULATOR_LEVEL_SVS_L2		224
+#define RPMH_REGULATOR_LEVEL_SVS_L2_0		225
 #define RPMH_REGULATOR_LEVEL_NOM		256
 #define RPMH_REGULATOR_LEVEL_NOM_L0		288
 #define RPMH_REGULATOR_LEVEL_NOM_L1		320
@@ -54,8 +60,14 @@
 #define RPMH_REGULATOR_LEVEL_TURBO		384
 #define RPMH_REGULATOR_LEVEL_TURBO_L0		400
 #define RPMH_REGULATOR_LEVEL_TURBO_L1		416
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_0		417
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_1		418
+#define RPMH_REGULATOR_LEVEL_TURBO_L1_2		419
 #define RPMH_REGULATOR_LEVEL_TURBO_L2		432
 #define RPMH_REGULATOR_LEVEL_TURBO_L3		448
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_0		449
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_1		450
+#define RPMH_REGULATOR_LEVEL_TURBO_L3_2		451
 #define RPMH_REGULATOR_LEVEL_TURBO_L4		452
 #define RPMH_REGULATOR_LEVEL_TURBO_L5		456
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO	464
diff --git a/include/dt-bindings/reset/cix,sky1-s5-system-control.h b/include/dt-bindings/reset/cix,sky1-s5-system-control.h
new file mode 100644
index 00000000000..808bbcbe0c9
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-s5-system-control.h
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <[email protected]> */
+#ifndef DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H
+#define DT_BINDING_RESET_CIX_SKY1_S5_SYSTEM_CONTROL_H
+
+/* reset for csu_pm */
+#define SKY1_CSU_PM_RESET_N		0
+#define SKY1_SENSORFUSION_RESET_N	1
+#define SKY1_SENSORFUSION_NOC_RESET_N	2
+
+/* reset group0 for s0 domain modules */
+#define SKY1_DDRC_RESET_N		3
+#define SKY1_GIC_RESET_N		4
+#define SKY1_CI700_RESET_N		5
+#define SKY1_SYS_NI700_RESET_N		6
+#define SKY1_MM_NI700_RESET_N		7
+#define SKY1_PCIE_NI700_RESET_N		8
+#define SKY1_GPU_RESET_N		9
+#define SKY1_NPUTOP_RESET_N		10
+#define SKY1_NPUCORE0_RESET_N		11
+#define SKY1_NPUCORE1_RESET_N		12
+#define SKY1_NPUCORE2_RESET_N		13
+#define SKY1_VPU_RESET_N		14
+#define SKY1_ISP_SRESET_N		15
+#define SKY1_ISP_ARESET_N		16
+#define SKY1_ISP_HRESET_N		17
+#define SKY1_ISP_GDCRESET_N		18
+#define SKY1_DPU_RESET0_N		19
+#define SKY1_DPU_RESET1_N		20
+#define SKY1_DPU_RESET2_N		21
+#define SKY1_DPU_RESET3_N		22
+#define SKY1_DPU_RESET4_N		23
+#define SKY1_DP_RESET0_N		24
+#define SKY1_DP_RESET1_N		25
+#define SKY1_DP_RESET2_N		26
+#define SKY1_DP_RESET3_N		27
+#define SKY1_DP_RESET4_N		28
+#define SKY1_DP_PHY_RST_N		29
+
+/* reset group1 for s0 domain modules */
+#define SKY1_AUDIO_HIFI5_RESET_N	30
+#define SKY1_AUDIO_HIFI5_NOC_RESET_N	31
+#define SKY1_CSIDPHY_PRST0_N		32
+#define SKY1_CSIDPHY_CMNRST0_N		33
+#define SKY1_CSI0_RST_N			34
+#define SKY1_CSIDPHY_PRST1_N		35
+#define SKY1_CSIDPHY_CMNRST1_N		36
+#define SKY1_CSI1_RST_N			37
+#define SKY1_CSI2_RST_N			38
+#define SKY1_CSI3_RST_N			39
+#define SKY1_CSIBRDGE0_RST_N		40
+#define SKY1_CSIBRDGE1_RST_N		41
+#define SKY1_CSIBRDGE2_RST_N		42
+#define SKY1_CSIBRDGE3_RST_N		43
+#define SKY1_GMAC0_RST_N		44
+#define SKY1_GMAC1_RST_N		45
+#define SKY1_PCIE0_RESET_N		46
+#define SKY1_PCIE1_RESET_N		47
+#define SKY1_PCIE2_RESET_N		48
+#define SKY1_PCIE3_RESET_N		49
+#define SKY1_PCIE4_RESET_N		50
+
+/* reset group1 for usb phys */
+#define SKY1_USB_DP_PHY0_PRST_N		51
+#define SKY1_USB_DP_PHY1_PRST_N		52
+#define SKY1_USB_DP_PHY2_PRST_N		53
+#define SKY1_USB_DP_PHY3_PRST_N		54
+#define SKY1_USB_DP_PHY0_RST_N		55
+#define SKY1_USB_DP_PHY1_RST_N		56
+#define SKY1_USB_DP_PHY2_RST_N		57
+#define SKY1_USB_DP_PHY3_RST_N		58
+#define SKY1_USBPHY_SS_PST_N		59
+#define SKY1_USBPHY_SS_RST_N		60
+#define SKY1_USBPHY_HS0_PRST_N		61
+#define SKY1_USBPHY_HS1_PRST_N		62
+#define SKY1_USBPHY_HS2_PRST_N		63
+#define SKY1_USBPHY_HS3_PRST_N		64
+#define SKY1_USBPHY_HS4_PRST_N		65
+#define SKY1_USBPHY_HS5_PRST_N		66
+#define SKY1_USBPHY_HS6_PRST_N		67
+#define SKY1_USBPHY_HS7_PRST_N		68
+#define SKY1_USBPHY_HS8_PRST_N		69
+#define SKY1_USBPHY_HS9_PRST_N		70
+
+/* reset group1 for usb controllers */
+#define SKY1_USBC_SS0_PRST_N		71
+#define SKY1_USBC_SS1_PRST_N		72
+#define SKY1_USBC_SS2_PRST_N		73
+#define SKY1_USBC_SS3_PRST_N		74
+#define SKY1_USBC_SS4_PRST_N		75
+#define SKY1_USBC_SS5_PRST_N		76
+#define SKY1_USBC_SS0_RST_N		77
+#define SKY1_USBC_SS1_RST_N		78
+#define SKY1_USBC_SS2_RST_N		79
+#define SKY1_USBC_SS3_RST_N		80
+#define SKY1_USBC_SS4_RST_N		81
+#define SKY1_USBC_SS5_RST_N		82
+#define SKY1_USBC_HS0_PRST_N		83
+#define SKY1_USBC_HS1_PRST_N		84
+#define SKY1_USBC_HS2_PRST_N		85
+#define SKY1_USBC_HS3_PRST_N		86
+#define SKY1_USBC_HS0_RST_N		87
+#define SKY1_USBC_HS1_RST_N		88
+#define SKY1_USBC_HS2_RST_N		89
+#define SKY1_USBC_HS3_RST_N		90
+
+/* reset group0 for rcsu */
+#define SKY1_AUDIO_RCSU_RESET_N			91
+#define SKY1_CI700_RCSU_RESET_N			92
+#define SKY1_CSI_RCSU0_RESET_N			93
+#define SKY1_CSI_RCSU1_RESET_N			94
+#define SKY1_CSU_PM_RCSU_RESET_N		95
+#define SKY1_DDR_BROADCAST_RCSU_RESET_N		96
+#define SKY1_DDR_CTRL_RCSU_0_RESET_N		97
+#define SKY1_DDR_CTRL_RCSU_1_RESET_N		98
+#define SKY1_DDR_CTRL_RCSU_2_RESET_N		99
+#define SKY1_DDR_CTRL_RCSU_3_RESET_N		100
+#define SKY1_DDR_TZC400_RCSU_0_RESET_N		101
+#define SKY1_DDR_TZC400_RCSU_1_RESET_N		102
+#define SKY1_DDR_TZC400_RCSU_2_RESET_N		103
+#define SKY1_DDR_TZC400_RCSU_3_RESET_N		104
+#define SKY1_DP0_RCSU_RESET_N			105
+#define SKY1_DP1_RCSU_RESET_N			106
+#define SKY1_DP2_RCSU_RESET_N			107
+#define SKY1_DP3_RCSU_RESET_N			108
+#define SKY1_DP4_RCSU_RESET_N			109
+#define SKY1_DPU0_RCSU_RESET_N			110
+#define SKY1_DPU1_RCSU_RESET_N			111
+#define SKY1_DPU2_RCSU_RESET_N			112
+#define SKY1_DPU3_RCSU_RESET_N			113
+#define SKY1_DPU4_RCSU_RESET_N			114
+#define SKY1_DSU_RCSU_RESET_N			115
+#define SKY1_FCH_RCSU_RESET_N			116
+#define SKY1_GICD_RCSU_RESET_N			117
+#define SKY1_GMAC_RCSU_RESET_N			118
+#define SKY1_GPU_RCSU_RESET_N			119
+#define SKY1_ISP_RCSU0_RESET_N			120
+#define SKY1_ISP_RCSU1_RESET_N			121
+#define SKY1_NI700_MMHUB_RCSU_RESET_N		122
+
+/* reset group1 for rcsu */
+#define SKY1_NPU_RCSU_RESET_N			123
+#define SKY1_NI700_PCIE_RCSU_RESET_N		124
+#define SKY1_PCIE_X421_RCSU_RESET_N		125
+#define SKY1_PCIE_X8_RCSU_RESET_N		126
+#define SKY1_SF_RCSU_RESET_N			127
+#define SKY1_RCSU_SMMU_MMHUB_RESET_N		128
+#define SKY1_RCSU_SMMU_PCIEHUB_RESET_N		129
+#define SKY1_RCSU_SYSHUB_RESET_N		130
+#define SKY1_NI700_SMN_RCSU_RESET_N		131
+#define SKY1_NI700_SYSHUB_RCSU_RESET_N		132
+#define SKY1_RCSU_USB2_HOST0_RESET_N		133
+#define SKY1_RCSU_USB2_HOST1_RESET_N		134
+#define SKY1_RCSU_USB2_HOST2_RESET_N		135
+#define SKY1_RCSU_USB2_HOST3_RESET_N		136
+#define SKY1_RCSU_USB3_TYPEA_DRD_RESET_N	137
+#define SKY1_RCSU_USB3_TYPEC_DRD_RESET_N	138
+#define SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N	139
+#define SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N	140
+#define SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N	141
+#define SKY1_VPU_RCSU_RESET_N			142
+
+#endif
diff --git a/include/dt-bindings/reset/cix,sky1-system-control.h b/include/dt-bindings/reset/cix,sky1-system-control.h
new file mode 100644
index 00000000000..7a16fc4ef3b
--- /dev/null
+++ b/include/dt-bindings/reset/cix,sky1-system-control.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Author: Jerry Zhu <[email protected]> */
+#ifndef DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H
+#define DT_BINDING_RESET_CIX_SKY1_SYSTEM_CONTROL_H
+
+/* func reset for sky1 fch */
+#define SW_I3C0_RST_FUNC_G_N	0
+#define SW_I3C0_RST_FUNC_I_N	1
+#define SW_I3C1_RST_FUNC_G_N	2
+#define SW_I3C1_RST_FUNC_I_N	3
+#define SW_UART0_RST_FUNC_N	4
+#define SW_UART1_RST_FUNC_N	5
+#define SW_UART2_RST_FUNC_N	6
+#define SW_UART3_RST_FUNC_N	7
+#define SW_TIMER_RST_FUNC_N	8
+
+/* apb reset for sky1 fch */
+#define SW_I3C0_RST_APB_N	9
+#define SW_I3C1_RST_APB_N	10
+#define SW_DMA_RST_AXI_N	11
+#define SW_UART0_RST_APB_N	12
+#define SW_UART1_RST_APB_N	13
+#define SW_UART2_RST_APB_N	14
+#define SW_UART3_RST_APB_N	15
+#define SW_SPI0_RST_APB_N	16
+#define SW_SPI1_RST_APB_N	17
+#define SW_I2C0_RST_APB_N	18
+#define SW_I2C1_RST_APB_N	19
+#define SW_I2C2_RST_APB_N	20
+#define SW_I2C3_RST_APB_N	21
+#define SW_I2C4_RST_APB_N	22
+#define SW_I2C5_RST_APB_N	23
+#define SW_I2C6_RST_APB_N	24
+#define SW_I2C7_RST_APB_N	25
+#define SW_GPIO_RST_APB_N	26
+
+/* fch rst for xspi */
+#define SW_XSPI_REG_RST_N	27
+#define SW_XSPI_SYS_RST_N	28
+
+#endif
diff --git a/include/dt-bindings/reset/econet,en751221-scu.h b/include/dt-bindings/reset/econet,en751221-scu.h
new file mode 100644
index 00000000000..bad499d4d50
--- /dev/null
+++ b/include/dt-bindings/reset/econet,en751221-scu.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+
+#define EN751221_XPON_PHY_RST		 0
+#define EN751221_PCM1_ZSI_ISI_RST	 1
+#define EN751221_FE_QDMA1_RST		 2
+#define EN751221_FE_QDMA2_RST		 3
+#define EN751221_FE_UNZIP_RST		 4
+#define EN751221_PCM2_RST		 5
+#define EN751221_PTM_MAC_RST		 6
+#define EN751221_CRYPTO_RST		 7
+#define EN751221_SAR_RST		 8
+#define EN751221_TIMER_RST		 9
+#define EN751221_INTC_RST		10
+#define EN751221_BONDING_RST		11
+#define EN751221_PCM1_RST		12
+#define EN751221_UART_RST		13
+#define EN751221_GPIO_RST		14
+#define EN751221_GDMA_RST		15
+#define EN751221_I2C_MASTER_RST		16
+#define EN751221_PCM2_ZSI_ISI_RST	17
+#define EN751221_SFC_RST		18
+#define EN751221_UART2_RST		19
+#define EN751221_GDMP_RST		20
+#define EN751221_FE_RST			21
+#define EN751221_USB_HOST_P0_RST	22
+#define EN751221_GSW_RST		23
+#define EN751221_SFC2_PCM_RST		24
+#define EN751221_PCIE0_RST		25
+#define EN751221_PCIE1_RST		26
+#define EN751221_CPU_TIMER_RST		27
+#define EN751221_PCIE_HB_RST		28
+#define EN751221_SIMIF_RST		29
+#define EN751221_XPON_MAC_RST		30
+#define EN751221_GFAST_RST		31
+#define EN751221_CPU_TIMER2_RST		32
+#define EN751221_UART3_RST		33
+#define EN751221_UART4_RST		34
+#define EN751221_UART5_RST		35
+#define EN751221_I2C2_RST		36
+#define EN751221_XSI_MAC_RST		37
+#define EN751221_XSI_PHY_RST		38
+#define EN751221_DMT_RST		39
+#define EN751221_USB_PHY_P0_RST		40
+#define EN751221_USB_PHY_P1_RST		41
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */
diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bindings/reset/qcom,ipq5210-gcc.h
new file mode 100644
index 00000000000..09890a09087
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H
+
+#define GCC_ADSS_BCR						0
+#define GCC_ADSS_PWM_ARES					1
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			2
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES		3
+#define GCC_APSS_AHB_ARES					4
+#define GCC_APSS_ATB_ARES					5
+#define GCC_APSS_AXI_ARES					6
+#define GCC_APSS_TS_ARES					7
+#define GCC_BOOT_ROM_AHB_ARES					8
+#define GCC_BOOT_ROM_BCR					9
+#define GCC_GEPHY_BCR						10
+#define GCC_GEPHY_SYS_ARES					11
+#define GCC_GP1_ARES						12
+#define GCC_GP2_ARES						13
+#define GCC_GP3_ARES						14
+#define GCC_MDIO_AHB_ARES					15
+#define GCC_MDIO_BCR						16
+#define GCC_MDIO_GEPHY_AHB_ARES					17
+#define GCC_NSS_BCR						18
+#define GCC_NSS_TS_ARES						19
+#define GCC_NSSCC_ARES						20
+#define GCC_NSSCFG_ARES						21
+#define GCC_NSSNOC_ATB_ARES					22
+#define GCC_NSSNOC_MEMNOC_1_ARES				23
+#define GCC_NSSNOC_MEMNOC_ARES					24
+#define GCC_NSSNOC_NSSCC_ARES					25
+#define GCC_NSSNOC_PCNOC_1_ARES					26
+#define GCC_NSSNOC_QOSGEN_REF_ARES				27
+#define GCC_NSSNOC_SNOC_1_ARES					28
+#define GCC_NSSNOC_SNOC_ARES					29
+#define GCC_NSSNOC_TIMEOUT_REF_ARES				30
+#define GCC_NSSNOC_XO_DCD_ARES					31
+#define GCC_PCIE0_AHB_ARES					32
+#define GCC_PCIE0_AUX_ARES					33
+#define GCC_PCIE0_AXI_M_ARES					34
+#define GCC_PCIE0_AXI_S_BRIDGE_ARES				35
+#define GCC_PCIE0_AXI_S_ARES					36
+#define GCC_PCIE0_BCR						37
+#define GCC_PCIE0_LINK_DOWN_BCR					38
+#define GCC_PCIE0_PHY_BCR					39
+#define GCC_PCIE0_PIPE_ARES					40
+#define GCC_PCIE0PHY_PHY_BCR					41
+#define GCC_PCIE1_AHB_ARES					42
+#define GCC_PCIE1_AUX_ARES					43
+#define GCC_PCIE1_AXI_M_ARES					44
+#define GCC_PCIE1_AXI_S_BRIDGE_ARES				45
+#define GCC_PCIE1_AXI_S_ARES					46
+#define GCC_PCIE1_BCR						47
+#define GCC_PCIE1_LINK_DOWN_BCR					48
+#define GCC_PCIE1_PHY_BCR					49
+#define GCC_PCIE1_PIPE_ARES					50
+#define GCC_PCIE1PHY_PHY_BCR					51
+#define GCC_QRNG_AHB_ARES					52
+#define GCC_QRNG_BCR						53
+#define GCC_QUPV3_2X_CORE_ARES					54
+#define GCC_QUPV3_AHB_MST_ARES					55
+#define GCC_QUPV3_AHB_SLV_ARES					56
+#define GCC_QUPV3_BCR						57
+#define GCC_QUPV3_CORE_ARES					58
+#define GCC_QUPV3_WRAP_SE0_ARES					59
+#define GCC_QUPV3_WRAP_SE0_BCR					60
+#define GCC_QUPV3_WRAP_SE1_ARES					61
+#define GCC_QUPV3_WRAP_SE1_BCR					62
+#define GCC_QUPV3_WRAP_SE2_ARES					63
+#define GCC_QUPV3_WRAP_SE2_BCR					64
+#define GCC_QUPV3_WRAP_SE3_ARES					65
+#define GCC_QUPV3_WRAP_SE3_BCR					66
+#define GCC_QUPV3_WRAP_SE4_ARES					67
+#define GCC_QUPV3_WRAP_SE4_BCR					68
+#define GCC_QUPV3_WRAP_SE5_ARES					69
+#define GCC_QUPV3_WRAP_SE5_BCR					70
+#define GCC_QUSB2_0_PHY_BCR					71
+#define GCC_SDCC1_AHB_ARES					72
+#define GCC_SDCC1_APPS_ARES					73
+#define GCC_SDCC1_ICE_CORE_ARES					74
+#define GCC_SDCC_BCR						75
+#define GCC_TLMM_AHB_ARES					76
+#define GCC_TLMM_ARES						77
+#define GCC_TLMM_BCR						78
+#define GCC_UNIPHY0_AHB_ARES					79
+#define GCC_UNIPHY0_BCR						80
+#define GCC_UNIPHY0_SYS_ARES					81
+#define GCC_UNIPHY1_AHB_ARES					82
+#define GCC_UNIPHY1_BCR						83
+#define GCC_UNIPHY1_SYS_ARES					84
+#define GCC_UNIPHY2_AHB_ARES					85
+#define GCC_UNIPHY2_BCR						86
+#define GCC_UNIPHY2_SYS_ARES					87
+#define GCC_USB0_AUX_ARES					88
+#define GCC_USB0_MASTER_ARES					89
+#define GCC_USB0_MOCK_UTMI_ARES					90
+#define GCC_USB0_PHY_BCR					91
+#define GCC_USB0_PHY_CFG_AHB_ARES				92
+#define GCC_USB0_PIPE_ARES					93
+#define GCC_USB0_SLEEP_ARES					94
+#define GCC_USB3PHY_0_PHY_BCR					95
+#define GCC_USB_BCR						96
+#define GCC_PCIE0_PIPE_RESET					97
+#define GCC_PCIE0_CORE_STICKY_RESET				98
+#define GCC_PCIE0_AXI_S_STICKY_RESET				99
+#define GCC_PCIE0_AXI_S_RESET					100
+#define GCC_PCIE0_AXI_M_STICKY_RESET				101
+#define GCC_PCIE0_AXI_M_RESET					102
+#define GCC_PCIE0_AUX_RESET					103
+#define GCC_PCIE0_AHB_RESET					104
+#define GCC_PCIE1_PIPE_RESET					105
+#define GCC_PCIE1_CORE_STICKY_RESET				106
+#define GCC_PCIE1_AXI_S_STICKY_RESET				107
+#define GCC_PCIE1_AXI_S_RESET					108
+#define GCC_PCIE1_AXI_M_STICKY_RESET				109
+#define GCC_PCIE1_AXI_M_RESET					110
+#define GCC_PCIE1_AUX_RESET					111
+#define GCC_PCIE1_AHB_RESET					112
+#define GCC_UNIPHY0_XPCS_ARES					113
+#define GCC_UNIPHY1_XPCS_ARES					114
+#define GCC_UNIPHY2_XPCS_ARES					115
+#define GCC_QDSS_BCR						116
+
+#endif
diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
index 6d1ce7f5da5..45850f2d434 100644
--- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
+++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
@@ -140,6 +140,18 @@
 #define DISPLAY_PORT_RX_6	134
 #define DISPLAY_PORT_RX_7	135
 #define USB_RX			136
+#define LPI_MI2S_RX_0		137
+#define LPI_MI2S_TX_0		138
+#define LPI_MI2S_RX_1		139
+#define LPI_MI2S_TX_1		140
+#define LPI_MI2S_RX_2		141
+#define LPI_MI2S_TX_2		142
+#define LPI_MI2S_RX_3		143
+#define LPI_MI2S_TX_3		144
+#define LPI_MI2S_RX_4		145
+#define LPI_MI2S_TX_4		146
+#define SENARY_MI2S_RX		147
+#define SENARY_MI2S_TX		148
 
 #define LPASS_CLK_ID_PRI_MI2S_IBIT	1
 #define LPASS_CLK_ID_PRI_MI2S_EBIT	2
diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h
index e6526b13817..1e64a1f563f 100644
--- a/include/dt-bindings/usb/pd.h
+++ b/include/dt-bindings/usb/pd.h
@@ -60,6 +60,7 @@
 	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
 
 #define APDO_TYPE_PPS		0
+#define APDO_TYPE_SPR_AVS	2
 
 #define PDO_APDO_TYPE_SHIFT	28	/* Only valid value currently is 0x0 - PPS */
 #define PDO_APDO_TYPE_MASK	0x3
@@ -85,6 +86,23 @@
 	 PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) |	\
 	 PDO_PPS_APDO_MAX_CURR(max_ma))
 
+#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR_SHIFT	10	/* 10mA units */
+#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR_SHIFT	0	/* 10mA units */
+#define PDO_SPR_AVS_APDO_MAX_CURR_MASK			0x3ff
+
+#define PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR(max_cur_9v_to_15v_ma)		\
+	((((max_cur_9v_to_15v_ma) / 10) & PDO_SPR_AVS_APDO_MAX_CURR_MASK) <<	\
+	PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR_SHIFT)
+
+#define PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR(max_cur_15v_to_20v_ma)		\
+	((((max_cur_15v_to_20v_ma) / 10) & PDO_SPR_AVS_APDO_MAX_CURR_MASK) <<	\
+	PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR_SHIFT)
+
+#define PDO_SPR_AVS_SNK_APDO(max_cur_9v_to_15v_ma, max_cur_15v_to_20v_ma)	\
+	(PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_SPR_AVS) |		\
+	PDO_SPR_AVS_APDO_9V_TO_15V_MAX_CURR(max_cur_9v_to_15v_ma) |		\
+	PDO_SPR_AVS_APDO_15V_TO_20V_MAX_CURR(max_cur_15v_to_20v_ma))
+
  /*
   * Based on "Table 6-14 Fixed Supply PDO - Sink" of "USB Power Delivery Specification Revision 3.0,
   * Version 1.2"
@@ -465,4 +483,22 @@
 	 | ((vbm) & 0x3) << 15 | (curr) << 14 | ((vbi) & 0x3f) << 7	\
 	 | ((gi) & 0x3f) << 1 | (ct))
 
+/*
+ * Sink Load Characteristics
+ * -------------------------
+ *  <15>    :: Can tolerate vbus voltage droop
+ *  <11:14> :: Duty cycle in 5% increments when bits 4:0 are non-zero
+ *  <10:5>  :: Overload period in 20ms when bits 4:0 are non-zero
+ *  <4:0>   :: Percent overload in 10% increments. Values higher than 25 are
+ *             clipped to 250%
+ */
+#define SINK_LOAD_CHAR(vdroop, duty_cycle, period, percent_ol)		\
+	(((vdroop) & 0x1) << 15 | ((duty_cycle) & 0xf) << 11 |		\
+	 ((period) & 0x3f) << 5 | ((percent_ol) & 0x1f))
+
+/* Compliance */
+#define COMPLIANCE_LPS		(1 << 0)
+#define COMPLIANCE_PS1		(1 << 1)
+#define COMPLIANCE_PS2		(1 << 2)
+
 #endif /* __DT_POWER_DELIVERY_H */