diff options
| author | Marek Vasut <[email protected]> | 2026-05-19 16:28:15 +0200 |
|---|---|---|
| committer | Marek Vasut <[email protected]> | 2026-05-21 21:48:05 +0200 |
| commit | 9d47a5a4d56069915c758c06b0b22b659546f04b (patch) | |
| tree | 95f448c419bf00d66e7c5b57c1e9b923dafef1ae /include | |
| parent | 3b2ce3743c1aaf012d210018eee6bd27a89a24d4 (diff) | |
arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port
Add support for building U-Boot for Cortex-M33 RSIP core in Renesas
R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the
Cortex-M33 RSIP core, which initializes the hardware and then starts
the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware
and applications software respectively. The SCP is responsible for
platform resource management, and is used to start other CPU cores.
The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig
which configures the build for aarch32 instruction set compatible with
the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which
are derived from their non-CM33 counterparts, and add CM33 specifics.
The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic
arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core,
those are entrypoint before vectors, __data_start/__data_end symbols
for data-only relocation, and placement of BSS into read-write SRAM
area.
Signed-off-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/rcar-gen5-common.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 4fbe8994f62..5ff2a76fc05 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -14,7 +14,11 @@ /* Memory */ #define DRAM_RSV_SIZE 0x20600000 +#ifdef CONFIG_RCAR_64_RSIP +#define CFG_SYS_SDRAM_BASE 0xb8400000 +#else #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#endif #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) |